/[PAMELA software]/quicklook/dataToXML/Data/compilationInfo/src/INFN/TS_Test_INFN.c
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Contents of /quicklook/dataToXML/Data/compilationInfo/src/INFN/TS_Test_INFN.c

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Revision 1.1.1.1 - (show annotations) (download) (vendor branch)
Tue Apr 25 09:00:20 2006 UTC (19 years, 2 months ago) by kusanagi
Branch: MAIN
CVS Tags: dataToXML1_02/01, dataToXML1_02/00, dataToXML1_03/00, dataToXML1_03/01, dataToXML1_00/00, firstRelease, dataToXML1_01/00, dataToXML1_03_02, HEAD
Changes since 1.1: +0 -0 lines
File MIME type: text/plain
These program extract in an XML format the info contained into the ROOT files generated by YODA from the PAMELA data. To visualize the XML files in a more human readable format a collection of XSL files are given in the Data subfolder.

1 /* Module : TestUtility */
2 /* C.I. No. : */
3 /* Revision : */
4 /* Date : */
5 /* Belonging to : */
6 /* : */
7 /* File Name : TS_Test_INFN_p.c */
8 /* Program Type : */
9 /* Sub-modules : */
10 /* */
11 /*****************************************************************************/
12 /* S W D e v e l o p m e n t E n v i r o n m e n t */
13 /* */
14 /* Host system : */
15 /* SW Compiler : */
16 /* Author */
17 /* : */
18 /*****************************************************************************/
19 /* U p d a t i n g */
20 /* */
21 /* Revision : */
22 /* */
23 /* */
24 /*****************************************************************************/
25
26
27 /*============================= Include File ================================*/
28
29 #ifdef DEBUG
30 #define DURTY_MODE
31 #else
32 #undef DURTY_MODE
33 #endif
34
35 #include <src/INFN/LU_SourceFileID_INFN.h>
36 #define __FILEID__ _TS_Test_INFN__c
37 #include <src/INFN/PRH_ParamHandler_INFN_auto.h>
38 #include <src/INFN/PRH_ParamHandler_INFN.h>
39 #include <src/INFN/LU_LogUtility_INFN.h>
40
41 LU_DECL_MASK();
42 LU_DECL_TRACE();
43
44
45 #include <src/INFN/TS_Test_INFN.h>
46 #include <src/MCMDManager/MCMDArea/MA_MCMDArea_p.h>
47 #include <src/HKManager/HistoryArea/HA_HistoryArea_p.h>
48 #include <src/ModeManager/ModeCoordinator/MC_ModeCoordinator_p.h>
49 #include <src/SRAMManager/SRAMPageManager/SM_SRAMPageManager_p.h>
50 #include <src/SRAMManager/SRAMDriver/SD_SRAMDriver_p.h>
51 #include <src/FileManager/MMSUManager/FT_MMSUManager_p.h>
52 #include <src/SRAMManager/SRAMDriver/SD_SRAMDriver_p.h>
53 #include <src/BasicSW/TimingInfo/TI_TimingInfo_op.h> /** for TM_CYCLIC_ACQUISITION (TMTC) **/
54
55 #ifdef IOLIB
56 #include <stdio.h>
57 #endif
58
59 #include <src/TM_TCManager/TMTCManager/TM_TMTCManager_op.h>
60 #include <src/FileManager/MMSUManager/FT_MMSUManager_op.h>
61 #include <src/SRAMManager/SRAMPageManager/SM_SRAMPageManager_op.h>
62 #include <src/SRAMManager/SRAMPageManager/SM_SRAMPageManager_p.h>
63
64 #include <src/SRAMManager/SRAMDriver/SD_SRAMDriver_op.h>
65 #include <src/INFN/OS_rtems_INFN_p.h>
66 #include <src/INFN/DAQ_IDAQ_INFN.h>
67 #include <src/MCMDManager/MCMDDispatcher/MD_MCMDDispatcher_p.h>
68 #include <src/FileManager/MMSUManager/FT_MMSUManager_int.h>
69 #include <src/ModeManager/ModeCoordinator/MC_ModeCoordinator_p.h>
70 #include <src/INFN/HB_HKBuffer_INFN.h>
71 #include <src/INFN/LU_LogUtility_INFN.h>
72 #include <src/INFN/SCM_Manager_INFN.h>
73 #include <src/INFN/CH_CommandHandler_INFN.h>
74 #include <src/INFN/MH_ModeHandler_INFN.h>
75 #include <src/INFN/RM_RunManager_INFN.h>
76 #include <src/INFN/PM_PamManager_INFN.h>
77 #include <src/INFN/KHB_Driver_INFN.h>
78 #include <src/INFN/GS_Gas_INFN.h>
79 #include <src/INFN/PWR_PowerHandler_INFN.h>
80 #include <src/INFN/SNS_SensorsBoard_INFN.h>
81 #include <src/INFN/TRK_Tracker_INFN.h>
82 #include <src/INFN/HK_Manager_INFN.h>
83 #include <src/INFN/CAL_Calorimeter_INFN.h>
84 #include <src/INFN/TRG_Trigger_INFN.h>
85 #include <src/QualitySystem/DiagSupervisor/QS_DiagSupervisor_p.h>
86
87 #ifdef SIMULATOR
88 #include <src/BasicSW/Bus1553B/BI_Bus1553B_op.h>
89 #endif
90
91 /*==================================== define ===============================*/
92
93 #define HPC_PEND_INTREG_MASK 0x40
94 #define NCYC_PEND_INTREG_MASK 0x20
95 #define CYC_PEND_INTREG_MASK 0x10
96
97 #define TM_NCYCLIC_BUSY_MASK 0x8000
98 // #define TM_CYCLIC_BUSY_MASK 0x4000
99 #define TM_HPC_STATUS_MASK 0x0400
100 #define TM_NCYC_ERR_MASK 0x0100
101
102 #define TM_HPC_PW_MASK 0x0700
103 #define TM_HPC_PW_MAX 0x0007
104
105 #define PEND_INT_TIMEOUT 1000000
106 #define PEND_CYC_TIMEOUT 500000
107
108 #define TIMEOUT_CMD_LOOP 1000 // time out on CMD I/F
109
110 typedef unsigned char UBYTE;
111 typedef unsigned short int UWORD;
112 typedef unsigned long int UDWORD;
113
114 typedef struct
115 {
116 unsigned int pw;
117 unsigned int par;
118 }
119 HPC_PULSE;
120
121 static HPC_PULSE hpcPulse[8] =
122 {
123 {0x0000, 0x8000}, // 0 ms, no emission
124 {0x0100, 0x0000}, // 12.5 ms
125 {0x0200, 0x0000}, // 25 ms
126 {0x0300, 0x8000}, // 50 ms
127 {0x0400, 0x0000}, // 100 ms
128 {0x0500, 0x8000}, // 200 ms
129 {0x0600, 0x8000}, // 400 ms
130 {0x0700, 0x0000} // 800 ms
131 };
132
133
134 //Global variables
135
136 MA_HEADER_MCMD McMd;
137 static MsgTsk FrameMsg;
138
139 // This CustomPar should be used to allow parametrized operation
140 // without the need to recompile. Please Update the list in case of changes.
141 // Maurizio 09/12/2002
142 // CustomPar[0] ----> First page to cycle on (default = 0x00)
143 // CustomPar[1] ----> Last page to cycle on (default = 0x07)
144 // CustomPar[2] ----> Page size (default = 0x4000)
145 // CustomPar[3] ----> Page offeset (default = 0x0000)
146 // CustomPar[4] ----> Save pages in MM looping CustomPar[3]-times (default = 0x0001)
147 // CustomPar[5] ----> Length of the data packet (default = 0x4000)
148
149 static UINT32 CustomPar [50];
150 static char static_buff [100];
151 static volatile unsigned short confStatRegVal [100];
152
153 static boolean isCycAcqActive;
154
155 extern const unsigned short* TM_TMTCReg []; /* used in case 10 */
156 extern const TM_TC TM_TCtable []; /* used in case 10 */
157 extern const TM_TM TM_TMtable []; /* used in case 12 */
158
159
160
161 #ifdef DURTY_MODE
162
163 static UINT32 errors[2][0x8000];
164
165
166
167
168 static unsigned int checkdata=0;
169 static unsigned char aspettatodisp=0x55;
170 static unsigned char aspettatopari=0xaa;
171 static unsigned char aspettato[]={
172 0x55,
173 0xaa,0x55,
174 0xaa,0x55,
175 0xaa,0x55,
176 0xaa,0x55,
177 0xaa,0x55,
178 0xaa,0x55,
179 0xaa,0x55,
180 0xaa,0x55,
181 0xaa,0x55,
182 0xaa,0x55,
183 0xaa,0x55,
184 0xaa,0x55,
185 0xaa,0x55,
186 0xaa,0x55,
187 0xaa,0x55,
188 0xaa,0x55,
189 0xaa,0x55,
190 0xaa,0x55,
191 0xaa,0x55,
192 0xaa,0x55,
193 0xaa,0x55,
194 0xaa,0x55,
195 0xaa,0x55,
196 0xaa,0x55,
197 0xaa,0x55,
198 0xaa,0x55,
199 0xaa,0x55,
200 0xaa,0x55,
201 0xaa,0x55,
202 0xaa,0x55
203 };
204 static int aspettata_len = 55;
205
206 PRH_EXTERN_VAR(TS_kilo_104);
207 PRH_EXTERN_VAR(TS_readaddr_104);
208 PRH_EXTERN_VAR(TS_writeaddr_104);
209 PRH_EXTERN_VAR(TS_khb_idaq_cmd);
210 PRH_EXTERN_VAR(TS_len);
211 PRH_EXTERN_VAR(TS_104rate_n);
212 PRH_EXTERN_VAR(TS_104rate_wait);
213 PRH_EXTERN_VAR(TS_104pifwrite);
214 PRH_EXTERN_VAR(TS_104ramcopyfreq);
215 /*****************************************************************************/
216
217
218 static rtems_interval FULL_time_start,FULL_time_stop;
219 static rtems_task_priority FULL_priority,FULL_dummy;
220 static UINT32 FULL_level;
221
222 #define FULL_CPU_OBTAIN() do { \
223 rtems_task_set_priority(RTEMS_SELF,1,&FULL_priority); \
224 rtems_interrupt_disable(FULL_level); \
225 rtems_clock_get(RTEMS_CLOCK_GET_TICKS_SINCE_BOOT,&FULL_time_start); \
226 } while(0);
227
228 #define FULL_CPU_RELEASE() do { \
229 rtems_clock_get(RTEMS_CLOCK_GET_TICKS_SINCE_BOOT,&FULL_time_stop); \
230 rtems_interrupt_enable(FULL_level); \
231 rtems_task_set_priority(RTEMS_SELF,FULL_priority,&FULL_dummy); \
232 } while (0)
233
234 #define FULL_CPU_DURATION() (FULL_time_stop-FULL_time_start)
235
236
237 /*============= S W _ T E S T I N T E R N A L F U N C T I O N ===========*/
238
239 /*****************************************************************************/
240 /* prototype
241 *
242 *
243 * Description
244 *
245 *
246 * Input parameters:
247 *
248 *
249 *
250 * Output parameters: rtems_status_code
251 *
252 */
253 /*****************************************************************************/
254
255 #define MIN(A, B) (((A) < (B)) ? (A) : (B))
256
257
258 #endif // DURTY_MODE
259
260 status_code TS_TestInit_INFN (void)
261 {
262 status_code status;
263 unsigned int OldPriority;
264 unsigned int transiz;
265 unsigned char* pRc;
266
267 status =SUCCESSFUL;
268 #ifdef DURTY_MODE
269 status |=OS_piTaskReady_INFN(TS_INFN_TASK,TS_tkTest_INFN);
270 status |=OS_piTaskPriority_INFN(TS_INFN_TASK,20,&OldPriority);
271 #endif // DURTY_MODE
272 isCycAcqActive = FALSE;
273
274 return (status);
275
276 }
277
278
279 DAQ_DECLBUF(hbuf,1024*64);
280 static unsigned int bufsel = 4;
281
282 #ifdef DURTY_MODE
283
284 status_code TS_SndTestCode_INFN(unsigned int code) {
285 MsgTsk SndMsg;
286 SndMsg.Code=code;
287 SndMsg.LlInfo=0;
288 TS_SndMsgTest_INFN(&SndMsg);
289 }
290
291
292 int TS_TM_All(unsigned int s,unsigned int e,TI_TIME *diff) {
293 unsigned int i,c;
294 TI_TIME Time_begin,Time_end,Time_diff;
295 TI_piGetTimeInfo_ms(&Time_begin);
296 for(i=s; i<=e ;i++) {
297 HK_GetTMValue (i,&c);
298 }
299 TI_piGetTimeInfo_ms(&Time_end);
300 *diff = Time_end - Time_begin;
301 }
302
303 unsigned int a,b,c,intLevel,d;
304 SM_ACQMODE oldmode,amode;
305 rtems_event_set evout;
306
307
308
309
310 DAQ_DECLBUF(dest,1024*128);
311 DAQ_DECLBUF(idaqbuf,1024*64);
312
313 DAQ_DECLBUF(cmdbuf,1024*16);
314 DAQ_DECLBUF(ac_idaqbuf,1024);
315 DAQ_DECLBUF(data,1024);
316 DAQ_DECLBUF(data2,1024);
317 DAQ_DECLBUF(idaq2,1024);
318 DAQ_DECLBUF(idaqcmd,16*1024);
319 DAQ_DECLBUF(ram_readdata,1);
320 DAQ_DECLBUF(flash_readdata,1);
321 DAQ_DECLBUF(dsp_readdata,1);
322 DAQ_DECLBUF(release_busy,4+1);
323
324 #endif // DURTY_MODE
325
326 /*****************************************************************************/
327 /* TS_tkTest_INFN
328 *
329 *
330 * Input parameters: NONE
331 *
332 * Output parameters: NONE
333 *
334 */
335 /*****************************************************************************/
336
337
338
339
340 #ifdef DEBUG
341 /* this funcion is used to force break point in case of message timeout */
342 unsigned int TS_FORCE_BREAKPOINT() {
343 unsigned int s=SUCCESSFUL;
344 return s;
345 }
346 #endif
347
348
349 #ifdef DURTY_MODE
350
351 status_code TS_GetCustomReadWriteRamBig(DAQ_CMD_BUF *b,UINT32 addr,UINT32 size,UINT32 *pattern) {
352 DAQ_DECLBUF(all,16*1024);
353 status_code s=0;
354 UINT32 i,j;
355 DAQ_BUFFER_INIT(all);
356 for(i=0;i<size;i++) {
357 all.buf[i]=(BYTE)((*pattern)++);
358 }
359 all.len=size;
360 s|=DAQ_Format_Cmd2Ram_WriteData(b,&all);
361 return s;
362 }
363
364 status_code TS_GetCustomWriteRam(DAQ_CMD_BUF *b,UINT32 addr,
365 UINT16 n,BYTE b1,BYTE b2,BYTE b3,BYTE b4) {
366 DAQ_DECLBUF(all,16*1024);
367 status_code s=0;
368 UINT32 i,j;
369 DAQ_BUFFER_INIT(all);
370 for(i=0,j=0;i<n;i++) {
371 all.buf[j++]=b1;
372 all.buf[j++]=b2;
373 all.buf[j++]=b3;
374 all.buf[j++]=b4;
375 }
376 all.len=n*4;
377 s|=DAQ_Format_CMD_Empty(b);
378 s|=DAQ_Format_Cmd2Ram_SetAddress(b,addr);
379 s|=DAQ_Format_Cmd2Ram_WriteData(b,&all);
380 s|=DAQ_Format_Cmd2Ram_EndBlock(b);
381 return s;
382 }
383
384 status_code TS_GetCustomReadRam(DAQ_CMD_BUF *b,UINT32 addr) {
385 status_code s=0;
386 DAQ_DECLBUF(ram_readdata,10);
387 DAQ_BUFFER_INIT(ram_readdata);
388 s|=DAQ_Format_CMD_Empty(b);
389 s|=DAQ_Format_Cmd2Ram_SetAddress(b,addr);
390 s!=DAQ_Format_Ram2Daq_ReadData(b);
391 return s;
392 }
393
394
395
396
397 void TS_BF(void) {
398 GS_REPLY_STRUCT s;
399 UINT16 *w=(UINT16*)&s;
400 UINT32 size=sizeof(s);
401 UINT16 static x=0xFFFF;
402 UINT16 static y=0xF0F0;
403 UINT32 static dump[12];
404 BYTE *b;
405 UINT32 i;
406 #define DUMP for(b=(BYTE*)&s,i=0;i<12;i++,b++) dump[i]=*b;
407 #define ZERO for(b=(BYTE*)&s,i=0;i<12;i++,b++) *b=0;
408 ZERO;
409 s.valid=x;
410 DUMP;
411
412 ZERO;
413 s.command=x;
414 DUMP;
415
416 ZERO;
417 s.valve_conf=x;
418 DUMP;
419
420 ZERO;
421 s.curr_state=x;
422 DUMP;
423
424 ZERO;
425 s.conf_soglie=x;
426 DUMP;
427
428 ZERO;
429 s.err_fpga=x;
430 DUMP;
431
432 ZERO;
433 s.err_pscu=x;
434 DUMP;
435
436 ZERO;
437 s.cont=x;
438 DUMP;
439
440 ZERO;
441 s.com=x;
442 DUMP;
443
444 y=x;
445 }
446
447 #define LOG_DURATION() do { \
448 t=FULL_CPU_DURATION(); \
449 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,t>>16); \
450 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,t); \
451 } while(0)
452
453
454 void TS_FULL_CPU_TESTS() {
455 rtems_interval t;
456 UINT32 i,j,k;
457 UINT32 n=20;
458 DAQ_BUFFER_INIT(cmdbuf);
459 for(i=0;i<cmdbuf.size;i++)
460 cmdbuf.buf[i]=i;
461 cmdbuf.len=cmdbuf.size;
462
463 FULL_CPU_OBTAIN();
464 // test CRC8 in 16KB buffer
465 for(i=0;i<n;i++)
466 DAQ_Compute_CRC16(&cmdbuf);
467 FULL_CPU_RELEASE();
468 LOG_DURATION();
469
470
471 FULL_CPU_OBTAIN();
472 // test CRC16 in 16KB buffer
473 for(i=0;i<n;i++)
474 DAQ_Compute_CRC16(&cmdbuf);
475 FULL_CPU_RELEASE();
476 LOG_DURATION();
477
478 FULL_CPU_OBTAIN();
479
480
481 }
482
483 void TS_CRC() {
484 static BYTE a[20] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
485 BYTE bcrc = 0,b2;
486 UINT16 wcrc,w2 = 0;
487 static UINT16 x =0;
488 UINT32 i1,i2;
489 static unsigned int len=20;
490 DAQ_CMD_BUF *sub;
491
492 /*
493 CH_GetBuf(CH_data,&sub);
494 w2 = CM_Compute_CRC16(0,sub->buf,sub->len);
495
496 return CM_Compute_CRC16(0,sub->buf,w2);
497 */
498 bcrc = i1 = CM_Compute_CRC8_8(0,a,len);
499 wcrc = i2 = CM_Compute_CRC16(0,a,len);
500
501 b2 = CM_Compute_CRC8_8(0,a,len);
502 w2 = CM_Compute_CRC16(0,a,len);
503 x = bcrc + wcrc + b2 +w2;
504 x++;
505 /*
506 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,bcrc);
507 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,i1);
508 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,wcrc);
509 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,i2);
510 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,b2);
511 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,w2);
512 */
513 }
514
515
516 #endif
517
518 task TS_tkTest_INFN (task_argument unused)
519 {
520
521 #ifdef DURTY_MODE
522
523 #define TEST_DATALEN 1024*128
524 //int databuf[TEST_DATALEN];
525 DAQ_DECLBUF(databuffer,TEST_DATALEN);
526
527 status_code status;
528 unsigned int MsgSize;
529 unsigned int counter;
530 unsigned int level,a,b,c,d,e,f,g,h,i,s;
531 TI_TIME Time_begin,Time_end,Time_diff[10];
532 unsigned int timeout;
533 UINT32 msg_timeout;
534 MsgTsk RxMsg;
535 unsigned char buf[100];
536 SD_DAQ_WRESULT pageInfo;
537
538 #define K 1024
539 static UINT32 pkt_counter=0;
540 static UINT32 pkt_wrong_counter=0;
541 static UINT32 pkt_delta_wrong[K];
542 BYTE fileid=__FILEID__;
543 for(a=0;a<K;a++)
544 pkt_delta_wrong[a]=0;
545
546 LU_INFN_LOG(LU_WARNING,0xffffffff,__FILEID__,__LINE__,PRH_TOTAL_VAR_SIZE);
547 LU_INFN_LOG(LU_WARNING,0xffffffff,__FILEID__,__LINE__,PRH_TOTAL_ARR_SIZE);
548 LU_INFN_LOG(LU_WARNING,0xffffffff,__FILEID__,__LINE__,PRH_TOTAL_TAB_SIZE);
549 LU_INFN_LOG(LU_WARNING,0xffffffff,__FILEID__,__LINE__,PRH_TOTAL_SIZE);
550
551 LU_TRACE(__FILEID__,__LINE__);
552
553 counter =1;
554 FrameMsg.Code = TS_FRAMEWORK;
555 FrameMsg.LlInfo = 0;
556 CustomPar[0] = 0x0000;
557 CustomPar[1] = 0x0007;
558 CustomPar[2] = 0x4000;
559 CustomPar[3] = 0x0000;
560 CustomPar[4] = 0x0001;
561 CustomPar[5] = 0x4000;
562
563
564 DAQ_BUFFER_INIT(idaqbuf);
565 DAQ_BUFFER_INIT(dest);
566 DAQ_BUFFER_INIT(idaq2);
567 DAQ_BUFFER_INIT(data);
568 DAQ_BUFFER_INIT(data2);
569 DAQ_BUFFER_INIT(ram_readdata);
570 DAQ_BUFFER_INIT(dsp_readdata);
571 DAQ_BUFFER_INIT(flash_readdata);
572 DAQ_BUFFER_INIT(release_busy);
573
574 s = DAQ_Format_Ram_ReadData(&ram_readdata);
575 s = DAQ_Format_Dsp_ReadData(&dsp_readdata);
576 s = DAQ_Format_Flash_ReadData(&flash_readdata);
577
578 s = DAQ_Format_ReleaseBusy(&release_busy);
579
580
581 #ifdef DEBUG
582 #ifdef SIMULATOR
583 msg_timeout=5000;
584 #else
585 msg_timeout=0;
586 #endif // SIMULATOR
587 #endif
588
589
590 while( FOREVER )
591 {
592 // Check mailbox queue
593
594 RxMsg.Code =NULL_MSG_TS_INFN;
595
596 status =OS_piMsgQueueReceive_INFN (TS_INFN_MAILBOX,(void*)&RxMsg,&MsgSize,WAIT,msg_timeout);
597 #ifdef DEBUG
598 if(status == RTEMS_TIMEOUT)
599 RxMsg.Code=TS_FORCE_BREAKPOINT();
600 #endif
601 LU_INFN_LOG(LU_WARNING,0xffffffff,__FILEID__,__LINE__,RxMsg.Code);
602
603
604 {
605 switch (RxMsg.Code)
606 {
607 case 1924:
608 s = DAQ_Format_CMD_Fill(&data,300,0xbb);
609 for(i=0;i<100;i++) {
610 /*
611 if(HB_Store((HB_BUF)(i%HB_MAX),(i*123)%1024,data.buf,0) == SUCCESSFUL)
612 s=1;
613 else
614 s=4;
615 */
616 }
617 s = 0;
618 break;
619 case 1923:
620 {
621 volatile int a=0x7fffffff;
622 volatile int m=0xffffffff;
623 volatile unsigned int x=23;
624 volatile unsigned int y=32;
625 volatile int b = x - y;
626 volatile int c = y - x;
627 a++;
628 m++;
629 b++;
630 a=34;
631 b=0;
632 if(a % b == 0)
633 c=0;
634 if(b != 0 && a % b == 0)
635 c=1;
636 c=3;
637 }
638 break;
639 case 444: {
640 unsigned int d;
641 rtems_time_of_day timeb;
642 d=rtems_clock_set(&timeb);
643 OS_piTaskSuspend(1000);
644 d=rtems_clock_get(RTEMS_CLOCK_GET_TOD , &timeb);
645 }
646 break;
647 case TS_FRAMEWORK: {
648
649 // write to PIF, read back and store to MM
650
651 UINT32 loop;
652 UINT32 pageCounter;
653 UINT32 value, tst_value;
654 char * RAMStartAddr;
655 char * runAddr;
656 unsigned int intLevel;
657
658 RAMStartAddr = (char *) malloc(CustomPar[2] * sizeof(char));
659 if (RAMStartAddr == NULL)
660 break;
661
662 if (PM_pi_GetAcqMode() == SM_EXP64/*it was SM_EXPERIMENT*/)
663 {
664 TI_piGetTimeInfo_ms(&Time_begin);
665
666 //SM_EnableStoreET = FALSE;
667 OS_piInterDisable(&intLevel);
668 // SD_piClearInt(SD_DATA_TO);
669 // ERC32_Clear_interrupt(ERC32_INTERRUPT_EXTERNAL_2);
670 SD_piMaskInt(SD_WPB_EOT);
671 OS_piInterEnable(intLevel);
672
673 // Loop on pages
674
675 for(pageCounter=CustomPar[0]; pageCounter <= CustomPar[1]; pageCounter++)
676 {
677
678 // Write to the whole page
679
680 SD_piSetSRAMRWAddress((UINT32)((pageCounter * CustomPar[2]) + CustomPar[3]));
681
682 for(loop=0; loop < CustomPar[2]; loop++) {
683 // SD_piSetSRAMRWAddress((UINT32)((pageCounter * CustomPar[2]) + CustomPar[3] + loop)); // try this ...
684 value=(loop + pageCounter) & 0x000000FF;
685 SD_piWriteSRAM(value);
686 }
687 }
688
689 TI_piGetTimeInfo_ms(&Time_end);
690 Time_end = Time_end - Time_begin;
691
692 //Test what has been written
693
694 for(pageCounter=CustomPar[0]; pageCounter <= CustomPar[1]; pageCounter++)
695 {
696
697 SD_piSetSRAMRWAddress((UINT32)((pageCounter * CustomPar[2]) + CustomPar[3]));
698
699 //Read on the whole page
700 runAddr = RAMStartAddr;
701
702 for(loop=0; loop < CustomPar[2]; loop++)
703 {
704 // SD_piSetSRAMRWAddress((UINT32)((pageCounter * CustomPar[2]) + CustomPar[3] + loop)); // try this ...
705 // *runAddr = SD_piReadSRAM();
706 value = SD_piReadSRAM();
707 // *runAddr = value;
708
709 // if (*runAddr++ != ((loop + pageCounter) & 0xFF))
710 if (value != ((loop + pageCounter) & 0xFF))
711 {
712 // sprintf(buf,"Error on page %02X location: %04X read: %08X", pageCounter, loop, value);
713 // puts(buf);
714 }
715 }
716 }
717
718 // Save to MM , explicit saving
719
720 for (loop = 0; loop < CustomPar[4]; loop++)
721 {
722 for(pageCounter=CustomPar[0]; pageCounter <= CustomPar[1]; pageCounter++)
723 {
724 // Put a save request for the SRAM page in the save queue
725
726 pageInfo = (UINT32)(pageCounter * CustomPar[2]) + CustomPar[2] + CustomPar[3] - 1;
727
728 // force storage to FS_FILE1
729
730 TI_piGetTimeInfo_ms(&Time_begin);
731 if(FT_piSavePage(pageCounter, pageInfo, FS_FILE1) != FT_SUCCESS)
732 {
733 /* The save request was refused */
734 // sprintf(buf,"Page number %02X store request refused ", pageCounter);
735 // puts(buf);
736 }
737 else
738 {
739 /* The save request was accepted */
740 /* so lock the (((skatchboard))) page */
741 // sprintf(buf,"Page number %02X store accepted ", pageCounter);
742 // puts(buf);
743 }
744 TI_piGetTimeInfo_ms(&Time_end);
745 Time_end = Time_end - Time_begin;
746 }
747 }
748
749 /* Disable storage on Event Trigger Interrupt */
750 OS_piInterDisable(&intLevel);
751 SD_piUnMaskInt(SD_WPB_EOT);
752 //SM_EnableStoreET = TRUE;
753 OS_piInterEnable(intLevel);
754
755 }
756
757 free(RAMStartAddr);
758
759 break;
760 }
761
762
763 case 2: {
764
765 // Write flexible to SRAM pages w/o MM
766 // CustomPar:
767 // 0 = start page (0,1,...)
768 // 1 = page offset
769 // 2 = nb.bytes to write
770
771 UINT32 loop;
772 UINT32 * RAMStartAddr;
773 UINT32 * runAddr;
774
775 RAMStartAddr = (UINT32 *) malloc(CustomPar[2] * sizeof(UINT32));
776
777 if (RAMStartAddr == NULL)
778 break;
779
780 if (PM_pi_GetAcqMode() == SM_EXP64/*it was SM_EXPERIMENT*/)
781 {
782 SD_piSetSRAMRWAddress((UINT32)((CustomPar[0] * 0x4000) + CustomPar[1]));
783
784 for(loop=0; loop < CustomPar[2]; loop++)
785 SD_piWriteSRAM((loop + CustomPar[0]) & 0x000000FF);
786
787 // Test what has been written
788
789 SD_piSetSRAMRWAddress((UINT32)((CustomPar[0] * 0x4000) + CustomPar[1]));
790 runAddr = RAMStartAddr;
791
792 for(loop=0; loop < CustomPar[2]; loop++)
793 {
794 *runAddr = SD_piReadSRAM();
795 if ((UINT32) *runAddr != ((loop + CustomPar[0]) & 0xFF))
796 {
797 // sprintf(buf,"Error on location: %04X read: %08X", loop,(UINT32 *) runAddr );
798 }
799 runAddr++;
800 }
801 }
802
803 free(RAMStartAddr);
804 break;
805 }
806
807 case 3: {
808
809 // read back from critical SRAM area (last 0xff)
810 // CustomPar 0=page.nb.; 1=write-offset, 2=nb.bytes, 3=additional read-offset
811
812 UINT32 loop;
813 UINT32 * RAMStartAddr, * RAMStartAddr_1;
814 UINT32 * runAddr, * runAddr_1;
815 UINT32 value;
816
817 RAMStartAddr = (UINT32 *) malloc(0xe0 * sizeof(UINT32));
818 RAMStartAddr_1 = (UINT32 *) malloc(0xe0 * sizeof(UINT32));
819
820 if (RAMStartAddr == NULL)
821 break;
822
823 // Fill test array
824 runAddr = RAMStartAddr;
825 // for(loop = 0; loop < 0xe0; loop++)
826 for(loop = 0; loop < CustomPar[2]; loop++)
827 *runAddr++ = loop & 0xFF;
828
829
830 // write to SRAM
831 // SD_piSetSRAMRWAddress((UINT32)((CustomPar[0] * 0x4000) + 0x3f10));
832 SD_piSetSRAMRWAddress((UINT32)((CustomPar[0] * 0x4000) + CustomPar[1]));
833 runAddr = RAMStartAddr;
834
835 for(loop = 0; loop < CustomPar[2]; loop++)
836 SD_piWriteSRAM((unsigned char) (*runAddr++ & 0x000000FF));
837
838 //Test what has been written : with read-offset
839
840 SD_piSetSRAMRWAddress((UINT32)((CustomPar[0] * 0x4000) + CustomPar[1] + CustomPar[3]));
841 runAddr = RAMStartAddr + CustomPar[3];
842 runAddr_1 = RAMStartAddr_1 + CustomPar[3];
843
844 for(loop = 0; loop < (CustomPar[2]-CustomPar[3]); loop++)
845 {
846 value = (UINT32) SD_piReadSRAM();
847 *(runAddr_1++) = value;
848 if ((UINT32) *(runAddr++) != value) {
849 // sprintf(buf,"Error on location: %04X read: %08X", loop,(UINT32 *) runAddr );
850 }
851 }
852
853 free(RAMStartAddr);
854 free(RAMStartAddr_1);
855 break;
856 }
857
858
859 case 9: {
860
861 // use Store_Packet (inspired by OrbitalData) RW, 12/2002
862
863 status_code status;
864 status_code statusTemp;
865 SM_ACQMODE PrevAcqMode;
866 FS_FILE_DESCR FileInfo;
867 // unsigned char tst_pkt[0x4000];
868 unsigned char * tst_pktPtr,
869 * runAddr;
870 int loop;
871
872 tst_pktPtr = (unsigned char *) malloc(0x4000 * sizeof(char));
873 if (tst_pktPtr == NULL)
874 break;
875
876 //Write on the whole page
877
878 runAddr = tst_pktPtr;
879 for(loop = 0; loop < 0x4000; loop++)
880 *runAddr++ = loop & 0xFF;
881
882 /* eventuali controlli sulla fattibilità dello switch in Experiment */
883 PrevAcqMode = PM_pi_GetAcqMode();
884
885 /* così acq al max 16k */
886 FT_piChangeAcqMode(SM_EXP64/*it was SM_EXPERIMENT*/);
887
888 // sprintf(buf,"Packet filled nbyte=%08X ", loop);
889 // puts(buf);
890 // TS_piPrintMiniCom_INFN (buf);
891
892 if (FS_piGetFileInfo (FS_FILE1, &FileInfo) != FS_FILEISFULL)
893 {
894 if ( (statusTemp = PM_pi_StorePacket (0x4000, tst_pktPtr, FS_FILE1)) != SUCCESSFUL)
895 {
896 status = statusTemp;
897
898 }
899 else
900 status = FS_FILEISFULL;
901
902 }
903
904 /* gli stati dei file possono essere ricavati dal RTF */
905 /* Il codice può salvare i dati nel file di HK (o di experimento) e ritornare FILE_FULL x' uno dei due è pieno */
906
907 FT_piChangeAcqMode(PrevAcqMode);
908
909 // HA_piLogHistoryEntry2 (PtrMcmd->Type,status);
910 // sprintf(buf,"Store Packet finished \n ");
911 // puts(buf);
912 // TS_piPrintMiniCom_INFN (buf);
913
914 free(tst_pktPtr);
915 }
916 break;
917
918 case 20:
919 {
920 int i;
921
922 for (i = 0; i < CustomPar[0]; i++)
923 {
924 // Set Page & End Address
925 SD_piSetCMDBUSReadPage (CustomPar[1]);
926 SD_piSetCMDBUSReadParams (CustomPar[1]*0x4000 + CustomPar[2]);
927 // Start DMA
928 SD_piStartTransferToCMD();
929 // Delay for next DMA
930 OS_piTaskSuspend (CustomPar[3]);
931 }
932
933 break;
934 }
935
936 case 40:
937 {
938 // use Store_Packet to fill 1M of MM THOR, 05/06/2003
939
940 status_code statusTemp;
941 unsigned char * tst_pktPtr,
942 * runAddr;
943 int i;
944 SM_ACQMODE PrevAcqMode;
945 FS_FILE_DESCR FileInfo;
946
947 tst_pktPtr = (unsigned char *) malloc(0x4000 * sizeof(char));
948 if (tst_pktPtr == NULL)
949 break;
950
951 //Write on the whole page
952
953 runAddr = tst_pktPtr;
954
955 for(i = 0; i < 0x4000; i++)
956 *runAddr++ = i & 0xFF;
957
958
959 // eventuali controlli sulla fattibilita dello switch in Experiment
960
961 PrevAcqMode = PM_pi_GetAcqMode();
962
963 FT_piChangeAcqMode(SM_EXP64/*it was SM_EXPERIMENT*/);
964
965 CustomPar[0]=200;
966
967 for (i = 0; i < CustomPar[0]; i++)
968 {
969 if (FS_piGetFileInfo (FS_FILE1, &FileInfo) != FS_FILEISFULL)
970 {
971 if ( (statusTemp = PM_pi_StorePacket (0x4000, tst_pktPtr, FS_HK)) != SUCCESSFUL)
972 {
973 status = FS_FILEISFULL;
974 }
975 }
976
977 CustomPar[1] = 50;
978
979 OS_piTaskSuspend (CustomPar[1]);
980 }
981
982 FT_piChangeAcqMode(PrevAcqMode);
983
984 free(tst_pktPtr);
985 break;
986 }
987
988 case 41:
989 {
990 // use SavePage to fill 1M of MM THOR, 05/06/2003
991
992 status_code statusTemp;
993 unsigned char * runAddr,
994 * RAMStartAddr;
995 int i,
996 loop,
997 page_size;
998 SM_ACQMODE PrevAcqMode;
999 FS_FILE_DESCR FileInfo;
1000 TI_TIME Time_begin,
1001 Time_end;
1002 unsigned int * deltaT_array,
1003 min_val = 0xFFFFFFFF,
1004 max_val = 0,
1005 ave_val = 0;
1006
1007 deltaT_array = (unsigned int *) malloc(CustomPar[2] * sizeof(int));
1008
1009 if (deltaT_array == NULL)
1010 break;
1011
1012 RAMStartAddr = (unsigned char *) malloc(0x4000 * sizeof(char));
1013
1014 if (RAMStartAddr == NULL)
1015 break;
1016
1017 //fill the RAM buffer with zeroes
1018
1019 runAddr = RAMStartAddr;
1020
1021 for(loop = 0; loop < 0x4000; loop++)
1022 *runAddr++ = 0;
1023
1024 //fill the PIF PAGE with a counter or a unique value
1025
1026 SD_piSetSRAMRWAddress ((UINT32) (CustomPar[0] * 0x4000));
1027
1028 for (i = 0; i < 0x4000; i++) {
1029 if (CustomPar[1] == 0xffff) SD_piWriteSRAM ((unsigned char) (0xff & i));
1030 else SD_piWriteSRAM ((unsigned char) (CustomPar[1]));
1031 }
1032
1033 // eventuali controlli sulla fattibilita dello switch in Experiment
1034
1035 PrevAcqMode = PM_pi_GetAcqMode();
1036
1037 FT_piChangeAcqMode(SM_EXP64/*it was SM_EXPERIMENT*/);
1038
1039 for (i = 0; i < CustomPar[2]; i++) // 0x10000 ==> 64 k - Loop over pages
1040 {
1041 SD_piSetSRAMRWAddress ((UINT32) (CustomPar[0] * 0x4000));
1042
1043 // writes boundary word (0xFFFF)
1044
1045 SD_piWriteSRAM ((unsigned char) (0xFF));
1046 SD_piWriteSRAM ((unsigned char) (0xFF));
1047
1048 // writes counter into first and last word of the PIF PAGE
1049
1050 SD_piWriteSRAM ((unsigned char) ((i & 0xFF00) >> 8)); // MOST SIGNIFICANT BYTE of the 16 bit counter
1051 SD_piWriteSRAM ((unsigned char) (i & 0xFF)); // LEAST SIGNIFICANT BYTE of the 16 bit counter
1052
1053 SD_piSetSRAMRWAddress ((UINT32) ((CustomPar[0] + 1) * 0x4000 - 2));
1054
1055 SD_piWriteSRAM ((unsigned char) ((i & 0xFF00) >> 8)); // MOST SIGNIFICANT BYTE of the 16 bit counter
1056 SD_piWriteSRAM ((unsigned char) (i & 0xFF)); // LEAST SIGNIFICANT BYTE of the 16 bit counter
1057
1058 if (CustomPar[3])
1059 {
1060 // Test what has been written
1061
1062 SD_piSetSRAMRWAddress ((UINT32) (CustomPar[0] * 0x4000));
1063
1064 runAddr = RAMStartAddr;
1065
1066 for(loop = 0; loop < 0x4000; loop++)
1067 *runAddr++ = SD_piReadSRAM();
1068 }
1069
1070 //---------------------------------------------------------------------------------------------------------------------
1071
1072 if (CustomPar[5])
1073 TI_piGetTimeInfo_ms(&Time_begin);
1074
1075 page_size=0x4000;
1076 if (CustomPar[6] && (i==0)) page_size=0x2000; // first page = 8kB in special mode
1077
1078 /*
1079 if (FS_piGetFileInfo (FS_FILE1, &FileInfo) != FS_FILEISFULL)
1080 FT_piSavePage (CustomPar[0], (CustomPar[0] + 1) * 0x4000 - 1, FS_FILE1); // force storage to FS_FILE1
1081 else
1082 if (FS_piGetFileInfo (FS_FILE2, &FileInfo) != FS_FILEISFULL)
1083 FT_piSavePage (CustomPar[0], (CustomPar[0] + 1) * 0x4000 - 1, FS_FILE2); // force storage to FS_FILE2
1084 */
1085 if (FS_piGetFileInfo (FS_FILE1, &FileInfo) != FS_FILEISFULL)
1086 FT_piSavePage (CustomPar[0], CustomPar[0]*0x4000 + page_size - 1, FS_FILE1);
1087
1088 if (CustomPar[5])
1089 {
1090 while (FT_opSaveInProgress ())
1091 OS_piTaskSuspend (1);
1092
1093 TI_piGetTimeInfo_ms(&Time_end);
1094
1095 Time_end -= Time_begin; // delta time
1096
1097 deltaT_array [i] = Time_end;
1098
1099 if (min_val > Time_end )
1100 min_val = Time_end;
1101
1102 ave_val = ave_val + Time_end * 100;
1103
1104 if (max_val < Time_end )
1105 max_val = Time_end;
1106 }
1107
1108 //---------------------------------------------------------------------------------------------------------------------
1109
1110 if (!CustomPar[5])
1111 OS_piTaskSuspend (CustomPar[4]);
1112 }
1113
1114 if (CustomPar[5])
1115 ave_val = ave_val / CustomPar[2];
1116
1117 FT_piChangeAcqMode(PrevAcqMode);
1118
1119 free (RAMStartAddr);
1120 free (deltaT_array);
1121 break;
1122 }
1123
1124 case 42:
1125 {
1126 int i;
1127
1128 SD_piSetSRAMRWAddress ((UINT32) (SM_CALEXP0 * 0x4000));
1129
1130 for (i = 0; i < CustomPar[0]; i++)
1131 SD_piWriteSRAM ((unsigned char) (CustomPar[i + 1]));
1132
1133 SD_piSetCMDBUSReadPage (SM_CALEXP0);
1134 SD_piSetCMDBUSReadParams (SM_CALEXP0 * 0x4000 + CustomPar[0] - 1);
1135
1136 SD_piStartTransferToCMD ();
1137 break;
1138 }
1139
1140 case 43:
1141 {
1142 int i;
1143
1144 SD_piSetSRAMRWAddress ((UINT32) (SM_CALPAGE * 0x4000));
1145
1146 for (i = 0; i < 0x4000; i++)
1147 SD_piWriteSRAM ((unsigned char) 0);
1148
1149
1150 SD_piSetSRAMRWAddress ((UINT32) (SM_CALEXP0 * 0x4000));
1151
1152 for (i = 0; i < CustomPar[0]; i++)
1153 SD_piWriteSRAM ((unsigned char) (CustomPar[i + 1]));
1154
1155 SD_piSetCMDBUSReadPage (SM_CALEXP0);
1156 SD_piSetCMDBUSReadParams (SM_CALEXP0 * 0x4000 + CustomPar[0] - 1);
1157
1158 // SD_piStartTransferToCMD ();
1159
1160 SD_piSetDAQWritePage (SM_CALPAGE);
1161 SD_piTrigCalibrationEvent ();
1162 SD_piStartTransferToCMD ();
1163
1164 break;
1165 }
1166 case 44:
1167 {
1168 int i;
1169 // la prima volta:
1170 // devi fare print PM_pi_UseCalibrationPage(SM_CALEXP0) (la8)
1171 // poi source scrivoinramidaq perpcaricare la pagina
1172
1173
1174 // devi fare print PM_pi_UseCalibrationPage(SM_CALEXP1) (la9)
1175 // poi source rileggiramidaqdirettamente (o in rileggiramidaq_reset_44) per pcaricare la pagina
1176 // poi mettere il SW nello stato DAQSETUP (B3)
1177 // poi source tkTest_msg44 per mandare l'opportuno messaggio a questo task
1178
1179 ERC32_Force_interrupt(ERC32_INTERRUPT_EXTERNAL_5);
1180
1181 break;
1182 }
1183
1184 case 45:
1185 {
1186 int i;
1187
1188 SD_piSetSRAMRWAddress ((UINT32) (SM_CALEXP0 * 0x4000));
1189
1190 for (i = 0; i < CustomPar[0]; i++)
1191 SD_piWriteSRAM ((unsigned char) (CustomPar[i + 1]));
1192
1193 SD_piSetCMDBUSReadPage (SM_CALEXP0);
1194 SD_piSetCMDBUSReadParams (SM_CALEXP0 * 0x4000 + CustomPar[0] - 1);
1195
1196 // SD_piStartTransferToCMD ();
1197
1198 SD_piSetDAQWritePage (SM_CALPAGE);
1199 SD_piStartTransferToCMD ();
1200 SD_piTrigCalibrationEvent ();
1201
1202 break;
1203 }
1204
1205 case 46:
1206 {
1207 // Test of the CMD/DAQ BUS : 16 k out / 16 k in; check of bytes recived both in DSP and CPU; check of CMD byte counter at the end of duplex transmission
1208
1209 UINT32 intLevel;
1210 UINT32 i,
1211 loop,
1212 value_pir,
1213 cnt,
1214 pkt_size,
1215 value,
1216 cnt_err,
1217 error_ovr,
1218 cmd_counter_error,
1219 timeOutCMD,
1220 timeOutCMD_max,
1221 timeOutCMD_cnt;
1222 UINT32 * runAddr,
1223 * RAMStartAddr,
1224 cmdCounterLeft;
1225
1226 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1227
1228 // set timeout: DTO & EOT
1229 // set event timeout to maximum (4.26 s)
1230
1231 *((unsigned char *) 0x980003b6) = 0xff;
1232 *((unsigned char *) 0x980003b8) = 0xff;
1233
1234 // set data timeout (LSB bit is 508 ns)
1235
1236 *((unsigned char *) 0x9800039a) = 0x01;
1237 *((unsigned char *) 0x9800039c) = 0x0f;
1238
1239 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1240
1241 // header length = 0
1242
1243 *((unsigned char *) 0x9800039E) = 0x00;
1244
1245 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1246
1247 // Disable ETO / DTO / PAGE OVR Interrupt
1248
1249 OS_piInterDisable(&intLevel);
1250 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
1251 SD_piMaskInt(SD_WPB_EOT | SD_DATA_TO | SD_EVT_TO); // DTO & ETO
1252 OS_piInterEnable(intLevel);
1253
1254 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1255
1256 error_ovr = 0x0;
1257 cnt_err = 0;
1258 cmd_counter_error = 0;
1259 timeOutCMD_max = 0;
1260 timeOutCMD_cnt = 0;
1261
1262 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1263
1264 //fills the CMD PAGE with a counter
1265
1266 SD_piSetSRAMRWAddress ((UINT32) (CustomPar[0] * 0x4000));
1267
1268 for (i = 0; i < (0x4000 / 2); i++)
1269 {
1270 SD_piWriteSRAM ((unsigned char) (((i & 0xFF00) >> 8))); // MOST SIGNIFICANT BYTE of the 16 bit counter
1271 SD_piWriteSRAM ((unsigned char) (i & 0xFF)); // LEAST SIGNIFICANT BYTE of the 16 bit counter
1272 }
1273
1274 for (loop = 0; loop < CustomPar[5]; loop++)
1275 {
1276 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1277
1278 //fills the DAQ PAGE with a unique value
1279
1280 SD_piSetSRAMRWAddress ((UINT32) (CustomPar[2] * 0x4000));
1281
1282 for (i = 0; i < 0x4000; i++)
1283 SD_piWriteSRAM ((unsigned char) (CustomPar[3]));
1284
1285 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1286
1287 // select pages
1288
1289 SD_piSetCMDBUSReadPage (CustomPar[0]); // CMD
1290 SD_piSetCMDBUSReadParams (CustomPar[0] * 0x4000 + CustomPar[1] - 1);
1291
1292 *((unsigned char *) 0x980003A2) = CustomPar[2]; // DAQ
1293
1294 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1295
1296 // Start DMA-DAQ -- DAQ Mode
1297
1298 *((unsigned char *) 0x98000396) = 0xff;
1299
1300 // Start CMD-DMA
1301
1302 SD_piStartTransferToCMD();
1303
1304 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1305
1306 // wait for DTO IR
1307
1308 value_pir = 0x0;
1309 cnt = 0;
1310
1311 while (!(value_pir & 0x01) && (cnt < CustomPar[4]))
1312 {
1313 value_pir = (unsigned int) (*(unsigned char *) 0x98000394);
1314
1315 if (value_pir & 0x10) // OVR
1316 {
1317 error_ovr++;
1318 break;
1319 }
1320
1321 cnt++;
1322 }
1323
1324 if (cnt >= CustomPar[4])
1325 timeOutCMD = 0; // use as dummy instruction to break at timeout
1326
1327 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1328
1329 if ((cnt < CustomPar[4]) && !error_ovr) // NO TIMEOUT, NO OVR
1330 {
1331 // wait until the buffer on CMD I/F is empty
1332
1333 timeOutCMD = 0;
1334
1335 while (SD_piGetCMDCounterLeft() != 0)
1336 timeOutCMD++;
1337
1338 if (timeOutCMD > timeOutCMD_max)
1339 {
1340 timeOutCMD_cnt++;
1341 timeOutCMD_max = timeOutCMD;
1342 }
1343
1344 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1345
1346 pkt_size = 0;
1347 pkt_size = SD_piGetDAQWriteResult() + 1;
1348
1349 SD_piSetSRAMRWAddress((UINT32) (CustomPar[2] * 0x4000));
1350
1351 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1352
1353 RAMStartAddr = (UINT32 *) malloc(0x4000 * sizeof(UINT32));
1354
1355 if (RAMStartAddr == NULL)
1356 break;
1357
1358 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1359
1360 //fills the RAM buffer with zeroes
1361
1362 runAddr = RAMStartAddr;
1363
1364 for(i = 0; i < 0x4000; i++)
1365 *runAddr++ = 0;
1366
1367 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1368
1369 runAddr = RAMStartAddr;
1370
1371 for (i = 0; i < (pkt_size / 2); i++)
1372 {
1373 value = (SD_piReadSRAM() << 8) & 0xFF00;
1374 value |= SD_piReadSRAM() & 0xFF;
1375
1376 *runAddr++ = value;
1377
1378 if (value != i) // error
1379 {
1380 errors[0][cnt_err] = i;
1381 errors[1][cnt_err] = value;
1382
1383 cnt_err++;
1384 }
1385 }
1386
1387 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1388
1389 cmdCounterLeft = 0;
1390 cmdCounterLeft = SD_opGetCMDCounterLeft ();
1391
1392 if (cmdCounterLeft != 0)
1393 cmd_counter_error++;
1394
1395 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1396
1397 free (RAMStartAddr);
1398 }
1399 }
1400
1401 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1402
1403 // Enable ETO / DTO / PAGE OVR Interrupt
1404
1405 OS_piInterDisable(&intLevel);
1406 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
1407 SD_piUnMaskInt(SD_WPB_EOT | SD_DATA_TO | SD_EVT_TO); // DTO & ETO
1408 OS_piInterEnable(intLevel);
1409
1410 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1411
1412 break;
1413 }
1414
1415 case 47:
1416 {
1417 // Test of the CMD/DAQ BUS : 16 k out (different pages) / 64 k in; check of bytes recived both in DSP and CPU; check of CMD byte counter at the end of CMD transmission
1418
1419 UINT32 intLevel;
1420 UINT32 page,
1421 daq_page,
1422 i,
1423 timeOutCMD,
1424 timeOutCMD_err,
1425 value_pir,
1426 cnt,
1427 pkt_size,
1428 value1,
1429 value2,
1430 value,
1431 cnt_err;
1432 UINT32 * runAddr,
1433 * RAMStartAddr;
1434
1435 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1436
1437 // set timeout: DTO & EOT
1438 // set event timeout to maximum (4.26 s)
1439
1440 *((unsigned char *) 0x980003b6) = 0xff;
1441 *((unsigned char *) 0x980003b8) = 0xff;
1442
1443 // set data timeout (LSB bit is 508 ns)
1444
1445 *((unsigned char *) 0x9800039a) = 0x01;
1446 *((unsigned char *) 0x9800039c) = 0x0f;
1447
1448 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1449
1450 // header length = 0
1451
1452 *((unsigned char *) 0x9800039E) = 0x00;
1453 *((unsigned char *) 0x980003A0) = 0x00; // necessario per azzerare l'header offset nel caso di acquisizione a 64/128 K
1454
1455 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1456
1457 // Disable ETO / DTO / PAGE OVR Interrupt
1458
1459 OS_piInterDisable(&intLevel);
1460 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
1461 SD_piMaskInt(SD_WPB_EOT | SD_DATA_TO | SD_EVT_TO); // DTO & ETO
1462 OS_piInterEnable(intLevel);
1463
1464 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1465
1466 // selects SM_PAGE0..SM_PAGE3 or SM_PAGE4..SM_PAGE7 as DAQ PAGE
1467
1468 if (CustomPar[1] == 1)
1469 daq_page = SM_PAGE0;
1470 else
1471 daq_page = SM_PAGE4;
1472
1473 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1474
1475 // programs DAQ DMA
1476
1477 *((unsigned char *) 0x980003A2) = daq_page;
1478
1479 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1480
1481 //fills the DAQ PAGE with a unique value
1482
1483 SD_piSetSRAMRWAddress ((UINT32) (daq_page * 0x4000));
1484
1485 for (i = 0; i < 0x10000; i++) // 64 k
1486 SD_piWriteSRAM ((unsigned char) (CustomPar[2]));
1487
1488 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1489
1490 // sends the 4 SM_CALEXP pages to the DSP
1491
1492 for (page = SM_CALEXP0; page <= SM_CALEXP3; page++)
1493 {
1494 //fills the CMD PAGE with a counter
1495
1496 SD_piSetSRAMRWAddress ((UINT32) (page * 0x4000));
1497
1498 for (i = 0; i < (0x4000 / 2); i++)
1499 {
1500 SD_piWriteSRAM ((unsigned char) ((((i + (page - SM_CALEXP0) * 0x2000)) & 0xFF00) >> 8)); // MOST SIGNIFICANT BYTE of the 16 bit counter
1501 SD_piWriteSRAM ((unsigned char) ((i + (page - SM_CALEXP0) * 0x2000) & 0xFF)); // LEAST SIGNIFICANT BYTE of the 16 bit counter
1502 }
1503
1504 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1505
1506 // programs CMD DMA
1507
1508 SD_piSetCMDBUSReadPage (page);
1509 SD_piSetCMDBUSReadParams (page * 0x4000 + CustomPar[0] - 1);
1510
1511 // Start CMD-DMA
1512
1513 SD_piStartTransferToCMD();
1514
1515 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1516
1517 // wait until the buffer on CMD I/F is empty
1518
1519 timeOutCMD = 0;
1520
1521 while ((SD_piGetCMDCounterLeft() != 0) && (timeOutCMD < TIMEOUT_CMD_LOOP))
1522 timeOutCMD++;
1523
1524 if (timeOutCMD >= TIMEOUT_CMD_LOOP)
1525 timeOutCMD_err++;
1526 }
1527
1528 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1529
1530 // receives 64 k bytes from the DSP
1531
1532 // Start DMA-DAQ -- DAQ 64 k Mode (DTO/ETO/OVR received)
1533
1534 *((unsigned char *) 0x980003E2) = 0xff;
1535
1536 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1537
1538 // wait for DTO IR
1539
1540 value_pir = 0x0;
1541 cnt = 0;
1542
1543 while (!(value_pir & 0x01) && (cnt < CustomPar[3]))
1544 {
1545 value_pir = (unsigned int) (*(unsigned char *) 0x98000394);
1546 cnt++;
1547 }
1548
1549 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1550
1551 if (cnt < CustomPar[3]) // NO TIMEOUT
1552 {
1553 RAMStartAddr = (UINT32 *) malloc(0x8000 * sizeof(UINT32));
1554
1555 if (RAMStartAddr == NULL)
1556 break;
1557
1558 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1559
1560 //fills the RAM buffer with zeroes
1561
1562 runAddr = RAMStartAddr;
1563
1564 for(i = 0; i < 0x8000; i++)
1565 *runAddr++ = 0;
1566
1567 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1568
1569 pkt_size = 0;
1570
1571 if (CustomPar[1] == 1)
1572 pkt_size = SD_piGetDAQWriteResult() + 1;
1573 else
1574 pkt_size = SD_piGetDAQWriteResult() + 1 - 0x10000;
1575
1576 SD_piSetSRAMRWAddress((UINT32) (daq_page * 0x4000));
1577
1578 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1579
1580 runAddr = RAMStartAddr;
1581 cnt_err = 0;
1582
1583 if (pkt_size > 0x10000)
1584 pkt_size = 0x10000;
1585
1586 for (i = 0; i < (pkt_size / 2); i++)
1587 {
1588 // value = (SD_piReadSRAM() << 24) & 0xFF000000;
1589 // value |= (SD_piReadSRAM() << 16) & 0x00FF0000;
1590 value1 = SD_piReadSRAM();
1591 value2 = SD_piReadSRAM();
1592
1593 value = (value1 << 8) & 0x0000FF00;
1594 value |= value2 & 0xFF;
1595
1596 *runAddr++ = value;
1597
1598 if (value != i) // error
1599 {
1600 errors[0][cnt_err] = i;
1601 errors[1][cnt_err] = value;
1602
1603 cnt_err++;
1604 }
1605 }
1606
1607 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1608
1609 free (RAMStartAddr);
1610 }
1611
1612 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1613
1614 // Enable ETO / DTO / PAGE OVR Interrupt
1615
1616 OS_piInterDisable(&intLevel);
1617 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
1618 SD_piUnMaskInt(SD_WPB_EOT | SD_DATA_TO | SD_EVT_TO); // DTO & ETO
1619 OS_piInterEnable(intLevel);
1620
1621 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1622
1623 break;
1624 }
1625
1626 case 48:
1627 {
1628 // Test of the CMD/DAQ BUS : 1 byte out / 128 k in; check of bytes recived in CPU; check of PAGE OVERRUN
1629
1630 UINT32 intLevel;
1631 UINT32 i,
1632 value_pir,
1633
1634 cnt,
1635 pkt_size,
1636 value,
1637 cnt_err;
1638 char * runAddr,
1639 * RAMStartAddr;
1640 BOOL ovr_detached;
1641
1642 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1643
1644 // set timeout: DTO & EOT
1645 // set event timeout to maximum (4.26 s)
1646
1647 *((unsigned char *) 0x980003b6) = 0xff;
1648 *((unsigned char *) 0x980003b8) = 0xff;
1649
1650 // set data timeout (LSB bit is 508 ns)
1651
1652 *((unsigned char *) 0x9800039a) = 0x01;
1653 *((unsigned char *) 0x9800039c) = 0x0f;
1654
1655 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1656
1657 // header length = 0
1658
1659 *((unsigned char *) 0x9800039E) = 0x00;
1660 *((unsigned char *) 0x980003A0) = 0x00; // necessario per azzerare l'header offset nel caso di acquisizione a 64/128 K
1661
1662 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1663
1664 // Disable ETO / DTO / PAGE OVR Interrupt
1665
1666 OS_piInterDisable(&intLevel);
1667 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
1668 SD_piMaskInt(SD_WPB_EOT | SD_DATA_TO | SD_EVT_TO); // DTO & ETO
1669 OS_piInterEnable(intLevel);
1670
1671 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1672
1673 // programs DAQ DMA
1674
1675 *((unsigned char *) 0x980003A2) = 0; // partiamo da pagina 0
1676
1677 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1678
1679 //fills the DAQ PAGE with a unique value
1680
1681 SD_piSetSRAMRWAddress ((UINT32) (0)); // partiamo da pagina 0
1682
1683 for (i = 0; i < 0x20000; i++) // 128 k
1684 SD_piWriteSRAM ((unsigned char) (CustomPar[0]));
1685
1686 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1687
1688 //clears the CMD PAGE
1689
1690 SD_piSetSRAMRWAddress ((UINT32) ((UINT32) (SM_CALEXP0 * 0x4000)));
1691
1692 for (i = 0; i < 0x4000; i++) // 128 k
1693 SD_piWriteSRAM ((unsigned char) (0));
1694
1695 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1696
1697 // sends 1 byte to the DSP thru CMD BUS
1698
1699 SD_piSetSRAMRWAddress ((UINT32) (SM_CALEXP0 * 0x4000));
1700 SD_piWriteSRAM ((unsigned char) (0));
1701 SD_piSetCMDBUSReadPage (SM_CALEXP0);
1702 SD_piSetCMDBUSReadParams (SM_CALEXP0 * 0x4000 + 1 - 1);
1703
1704 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1705
1706 // receives 128 k bytes from the DSP
1707
1708 // Start DAQ-DMA -- DAQ 128 k Mode (DTO/ETO/OVR received)
1709
1710 *((unsigned char *) 0x98000398) = 0x00;
1711
1712 // Start CMD-DMA
1713
1714 SD_piStartTransferToCMD ();
1715
1716 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1717
1718 // wait for DTO IR
1719
1720 value_pir = 0x0;
1721 cnt = 0;
1722 ovr_detached = FALSE;
1723
1724 while (!(value_pir & 0x01) && (cnt < CustomPar[1]))
1725 {
1726 value_pir = (unsigned int) (*(unsigned char *) 0x98000394);
1727
1728 if (value_pir & 0x10) // OVR
1729 ovr_detached = TRUE;
1730
1731 cnt++;
1732 }
1733
1734 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1735
1736 if (cnt < CustomPar[1]) // NO TIMEOUT
1737 {
1738 RAMStartAddr = (char *) malloc (0x20000 * sizeof(char));
1739
1740 if (RAMStartAddr == NULL)
1741 break;
1742
1743 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1744
1745 //fills the RAM buffer with zeroes
1746
1747 runAddr = RAMStartAddr;
1748
1749 for(i = 0; i < 0x20000; i++)
1750 *runAddr++ = 0;
1751
1752 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1753
1754 pkt_size = 0;
1755 pkt_size = SD_piGetDAQWriteResult() + 1;
1756
1757 if (pkt_size > 0x20000)
1758 pkt_size = 0x20000;
1759
1760 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1761
1762 runAddr = RAMStartAddr;
1763 cnt_err = 0;
1764
1765 SD_piSetSRAMRWAddress((UINT32) (0)); // partiamo da pagina 0
1766
1767 for (i = 0; i < pkt_size; i++)
1768 {
1769 value = SD_piReadSRAM();
1770
1771 *runAddr++ = value;
1772
1773 if (value != (i & 0xFF)) // error
1774 {
1775 errors[0][cnt_err] = i;
1776 errors[1][cnt_err] = value;
1777
1778 cnt_err++;
1779 }
1780 }
1781
1782 // ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1783
1784 free (RAMStartAddr);
1785 }
1786
1787 // -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1788
1789 if (ovr_detached == TRUE) // PAGE OVERRUN
1790 {
1791 // controlla che non sia stata sovrascritta la pagina successiva SM_PAGE7
1792
1793 // errors[0][cnt_err] = 0xFF;
1794 // errors[1][cnt_err++] = 0xFF;
1795
1796 SD_piSetSRAMRWAddress((UINT32) (SM_CALEXP0 * 0x4000));
1797
1798 for (i = 0; i < 0x4000; i++)
1799 {
1800 value = SD_piReadSRAM();
1801
1802 if (value != 0) // error
1803 {
1804 errors[0][cnt_err] = i;
1805 errors[1][cnt_err] = value;
1806
1807 cnt_err++;
1808 }
1809 }
1810 }
1811
1812 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1813
1814 // Enable ETO / DTO / PAGE OVR Interrupt
1815
1816 OS_piInterDisable(&intLevel);
1817 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
1818 SD_piUnMaskInt(SD_WPB_EOT | SD_DATA_TO | SD_EVT_TO); // DTO & ETO
1819 OS_piInterEnable(intLevel);
1820
1821 // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1822
1823 break;
1824 }
1825 case 49:
1826 b=1000;
1827 TI_piGetTimeInfo_ms(&Time_begin);
1828 for(a=0;a<b;a++) {
1829 TS_TM_All( TM_DEA_ANA_1 ,TM_DEA_ANA_16 ,&Time_diff[0]);
1830 TS_TM_All( TM_TH_ANA_1 ,TM_TH_ANA_16 ,&Time_diff[1]);
1831 TS_TM_All( TM_BIL_DIAG_ACQ_1 , TM_BIL_DIAG_ACQ_8 ,&Time_diff[2]);
1832 TS_TM_All( TM_CC_DIAG_ACQ_1 , TM_CC_DIAG_ACQ_32 ,&Time_diff[3]);
1833 TS_TM_All( TM_DBL_ACQ_3 , TM_DBL_ACQ_8 ,&Time_diff[4]);
1834 TS_TM_All( TM_DS_16_ACQ_1 , TM_DS_16_ACQ_2 ,&Time_diff[5]);
1835 }
1836 TI_piGetTimeInfo_ms(&Time_end);
1837 Time_diff[6]=Time_end - Time_begin;
1838 break;
1839
1840 case 50:
1841 {
1842 // test abbinato al DSP SW TAM_chk_match : riempio una pagina con una rampa crescente e la successiva con una rampa discendente
1843
1844 FS_FILE_DESCR FileInfo;
1845 int i;
1846 SM_ACQMODE PrevAcqMode;
1847
1848 PrevAcqMode = PM_pi_GetAcqMode();
1849
1850 FT_piChangeAcqMode(SM_EXP64/*it was SM_EXPERIMENT*/);
1851
1852 SD_piSetSRAMRWAddress ((UINT32) (SM_SKETCHBOARD * SM_SRAMPAGESIZE)); // prima pagina riempita con una rampa ascendente (contatore a 16 bit)
1853
1854 for (i = 0; i < (SM_SRAMPAGESIZE/2); i++)
1855 {
1856 SD_piWriteSRAM ((unsigned char) ((i & 0xFF00) >> 8)); // MOST SIGNIFICANT BYTE of the 16 bit counter
1857 SD_piWriteSRAM ((unsigned char) (i & 0xFF)); // LEAST SIGNIFICANT BYTE of the 16 bit counter
1858 }
1859
1860 SD_piSetSRAMRWAddress ((UINT32) ((SM_SKETCHBOARD + 1) * SM_SRAMPAGESIZE)); // seconda pagina riempita con una rampa discendente (contatore a 16 bit)
1861
1862 for ((i = (SM_SRAMPAGESIZE/2 - 1)); i >= 0; i--)
1863 {
1864 SD_piWriteSRAM ((unsigned char) ((i & 0xFF00) >> 8)); // MOST SIGNIFICANT BYTE of the 16 bit counter
1865 SD_piWriteSRAM ((unsigned char) (i & 0xFF)); // LEAST SIGNIFICANT BYTE of the 16 bit counter
1866 }
1867
1868 // riempiamo multipli di 4M byte della MM con queste 2 pagine
1869
1870 for (i = 0; i < (CustomPar[0] * 0x100); i++)
1871 {
1872 if (FS_piGetFileInfo (FS_FILE1, &FileInfo) != FS_FILEISFULL)
1873 {
1874 if (!(i % 2))
1875 FT_piSavePage (SM_SKETCHBOARD, (SM_SKETCHBOARD + 1) * SM_SRAMPAGESIZE - 1, FS_FILE1); // force storage to FS_FILE1
1876 else
1877 FT_piSavePage ((SM_SKETCHBOARD + 1), (SM_SKETCHBOARD + 2) * SM_SRAMPAGESIZE - 1, FS_FILE1);
1878 }
1879
1880 }
1881
1882 FT_piChangeAcqMode(PrevAcqMode);
1883 }
1884 break;
1885
1886 case 51:
1887 {
1888 // TEST RUSSI #1
1889 // 1) PREPARO IL GB IN MM
1890 // 2) DOWNLOAD DEL GB VERSO IL VRL
1891 // A) SWITCH ON DEL VRL (HL_CMD_1)
1892 // B) WAIT 6 SEC
1893 // C) START DEL VRL (HL_CMD_2)
1894 // D) DOWNLOAD GB
1895 // E) SWITCH OFF DEL VRL (HL_CMD_3)
1896 rtems_event_set unused;
1897 unsigned int code;
1898 unsigned char pattern [128] = { 0x00, 0x00, 0x00, 0x00,
1899 0x00, 0x00, 0x00, 0x00,
1900 0x00, 0x00, 0x00, 0x00,
1901 0x00, 0x00, 0x00, 0x00,
1902 0xFF, 0xFF, 0xFF, 0xFF,
1903 0xFF, 0xFF, 0xFF, 0xFF,
1904 0xFF, 0xFF, 0xFF, 0xFF,
1905 0xFF, 0xFF, 0xFF, 0xFF,
1906 0xAA, 0x55, 0xAA, 0x55,
1907 0xAA, 0x55, 0xAA, 0x55,
1908 0xAA, 0x55, 0xAA, 0x55,
1909 0xAA, 0x55, 0xAA, 0x55,
1910 0x55, 0xAA, 0x55, 0xAA,
1911 0x55, 0xAA, 0x55, 0xAA,
1912 0x55, 0xAA, 0x55, 0xAA,
1913 0x55, 0xAA, 0x55, 0xAA,
1914 0x55, 0xAA, 0x55, 0xAA,
1915 0x55, 0xAA, 0x55, 0xAA,
1916 0x55, 0xAA, 0x55, 0xAA,
1917 0x55, 0xAA, 0x55, 0xAA,
1918 0xAA, 0x55, 0xAA, 0x55,
1919 0xAA, 0x55, 0xAA, 0x55,
1920 0xAA, 0x55, 0xAA, 0x55,
1921 0xAA, 0x55, 0xAA, 0x55,
1922 0xFF, 0xFF, 0xFF, 0xFF,
1923 0xFF, 0xFF, 0xFF, 0xFF,
1924 0xFF, 0xFF, 0xFF, 0xFF,
1925 0xFF, 0xFF, 0xFF, 0xFF,
1926 0x00, 0x00, 0x00, 0x00,
1927 0x00, 0x00, 0x00, 0x00,
1928 0x00, 0x00, 0x00, 0x00,
1929 0x00, 0x00, 0x00, 0x00
1930 };
1931 unsigned int i,
1932 j;
1933 FS_FILE_DESCR FileInfo;
1934 SM_ACQMODE PrevAcqMode;
1935 unsigned short nSects;
1936 unsigned short mcmd [] = { 0x0001,
1937 0x0082,
1938 0x000A,
1939 0x0000,
1940 0x0000,
1941 0x3E8A,
1942 0x0000,
1943 0x0000
1944 };
1945 rtems_status_code status;
1946 static MsgTsk sndMsg;
1947 static MA_HEADER_MCMD mcmdHeader;
1948
1949 // -----------------------------------------------------------------------------------------------------------------------------------------------
1950
1951 nSects = CustomPar[0];
1952
1953 if (nSects < FT_MINDLSECTORS)
1954 nSects = FT_MINDLSECTORS;
1955
1956 // -----------------------------------------------------------------------------------------------------------------------------------------------
1957
1958 FT_opChangeOpMode (MC_MAINTENANCE_STATE);
1959 FT_opChangeOpMode (MC_ACTIVE_STATE);
1960
1961 PrevAcqMode = PM_pi_GetAcqMode();
1962
1963 FT_piChangeAcqMode(SM_EXP64/*it was SM_EXPERIMENT*/);
1964
1965 switch (CustomPar[1]) // scelta del pattern di riempimento della PIF SRAM
1966 {
1967 case 0 :
1968 // -----------------------------------------------------------------------------------------------------------------------------------------------
1969 // test preliminare con riempimento dei 256k della PIF SRAM con un contatore ad 8 bit
1970
1971 SD_piSetSRAMRWAddress ((UINT32) (SM_CALPAGE * SM_SRAMPAGESIZE));
1972
1973 for (j = 0; j < 1024; j++) // 256 k = 256 * 1024 (256 = lunghezza del pattern)
1974 for (i = 0; i < 256; i++)
1975 SD_piWriteSRAM ((unsigned char) (i & 0xFF));
1976 break;
1977
1978 case 1 :
1979 // -----------------------------------------------------------------------------------------------------------------------------------------------
1980 // test preliminare con riempimento dei 256k della PIF SRAM con un contatore a 16 bit
1981
1982 SD_piSetSRAMRWAddress ((UINT32) (SM_CALPAGE * SM_SRAMPAGESIZE));
1983
1984 for (j = 0; j < 1024; j++) // 256 k = 256 * 1024 (256 = lunghezza del pattern)
1985 for (i = 0; i < 128; i++)
1986 {
1987 SD_piWriteSRAM ((unsigned char) (((j * i) & 0xFF00) >> 8)); // MOST SIGNIFICANT BYTE of the 16 bit counter
1988 SD_piWriteSRAM ((unsigned char) ((j * i) & 0xFF)); // LEAST SIGNIFICANT BYTE of the 16 bit counter
1989 }
1990 break;
1991
1992 case 2 :
1993 // -----------------------------------------------------------------------------------------------------------------------------------------------
1994 // riempimento di una pagina della PIF con un PATTERN DI TEST (riempiamo tutta la SRAM della PIF : 256 k)
1995
1996 SD_piSetSRAMRWAddress ((UINT32) (SM_CALPAGE * SM_SRAMPAGESIZE));
1997
1998 // for (j = 0; j < 64; j++)
1999 for (j = 0; j < 1024; j++) // 256 k = 256 * 1024 (256 = lunghezza del pattern)
2000 {
2001 for (i = 0; i < 64; i++)
2002 SD_piWriteSRAM (pattern [i]);
2003
2004 for (i = 0; i < 128; i++)
2005 SD_piWriteSRAM ((unsigned char) (i & 0xFF));
2006
2007 for (i = 64; i < 128; i++)
2008 SD_piWriteSRAM (pattern [i]);
2009 }
2010 break;
2011 }
2012
2013 // -----------------------------------------------------------------------------------------------------------------------------------------------
2014 // riempio 1 GB di MM con i pattern contenuti nella PIF SRAM
2015
2016 // for (i = 0; i < (64 * nSects); i++)
2017 for (i = 0; i < (4 * nSects); i++) // 1 M = 4 * 256 k
2018 {
2019 FT_piSavePage (SM_CALPAGE, 256 * 1024 - 1, FS_FILE1); // scrive 256 k nel file di HOUSEKEEPING
2020
2021 while (FT_opSaveInProgress ())
2022 OS_piTaskSuspend (1);
2023 }
2024
2025 // -----------------------------------------------------------------------------------------------------------------------------------------------
2026 // SET START to 0 : START HLC 4
2027
2028 HK_SendTC (TM_HL_CMD_4, 0x1);
2029 OS_piTaskSuspend (110);
2030
2031 // -----------------------------------------------------------------------------------------------------------------------------------------------
2032 // SWITCH ON VRL : START HLC 2 + WAIT FOR 6 sec
2033
2034 HK_SendTC (TM_HL_CMD_2, 0x1);
2035 OS_piTaskSuspend (6000);
2036
2037 // -----------------------------------------------------------------------------------------------------------------------------------------------
2038 // SET START to 1 : START HLC 3
2039
2040 HK_SendTC (TM_HL_CMD_3, 0x1);
2041
2042 // -----------------------------------------------------------------------------------------------------------------------------------------------
2043 // wait some msecs before sending MCMD
2044
2045 if (CustomPar[3])
2046 OS_piTaskSuspend (CustomPar[3]);
2047
2048 // -----------------------------------------------------------------------------------------------------------------------------------------------
2049 // send DOWNLINK MCMD
2050
2051 mcmd [5] = (nSects << 4) | 0x000A;
2052
2053 MC_piSetState (MC_ACTIVE_STATE);
2054
2055 sndMsg.Code = MD_MCMD_EXEC;
2056
2057 mcmdHeader.Type = DOWN_LINK;
2058 mcmdHeader.TimeTag = 0x0000;
2059 mcmdHeader.PtrMCMD = (void *) mcmd;
2060 mcmdHeader.Length = 0x000A;
2061
2062 memcpy((void *) sndMsg.Info, (void *) &mcmdHeader, 16);
2063
2064 sndMsg.LlInfo = 16;
2065
2066 OS_piEventClear (OS_EVENT_END_OF_DOWNLINK);
2067 FT_opSetTask2Notify_EOD (TS_INFN_TASK);
2068 //HK_SendTC (TM_DBL_CMD, 0x0);
2069
2070 //while (1)
2071 // {
2072 status = MD_piSndMsgMCMDDispatcher (&sndMsg);
2073
2074 // per effettuare il download di 4 settori da 1015x1024 byte, ci vogliono circa 4 secondi
2075
2076 code = OS_piEventReceive (OS_EVENT_END_OF_DOWNLINK,WAIT, CustomPar[2], &unused);
2077
2078 // -----------------------------------------------------------------------------------------------------------------------------------------------
2079 // SET START to 0 : START HLC 4
2080
2081 HK_SendTC (TM_HL_CMD_4, 0x1);
2082 OS_piTaskSuspend (110);
2083
2084 // -----------------------------------------------------------------------------------------------------------------------------------------------
2085 // SWITCH OFF VRL : START HLC 1
2086
2087 HK_SendTC (TM_HL_CMD_1, 0x1);
2088 // }
2089 // -----------------------------------------------------------------------------------------------------------------------------------------------
2090
2091 FT_piChangeAcqMode (PrevAcqMode);
2092 //free (RAMStartAddr);
2093 }
2094 break;
2095
2096
2097 case 60:
2098 {
2099 unsigned int value_pir = 0x0;
2100 unsigned int cnt = 0;
2101 unsigned int ovr_detached = FALSE;
2102 unsigned int eto = 0xfffff;
2103 unsigned short *us;
2104 #define MAX_LEN_BUF 3000
2105 static int LEN_BUF[MAX_LEN_BUF];
2106 unsigned int N_LEN_BUF,gen_init;
2107 int com,success=0,unsuccess=0,very_success=0,nexit,susp,expected_len,mode;
2108 status_code s;
2109 SM_STRSTAT stat;
2110 DAQ_CMD_BUF *sub;
2111
2112 /* fill the body of the command data */
2113 a=1;
2114 b=idaqbuf.len;
2115 c=100000;
2116 d=7000;
2117 g=1;
2118 amode=SM_DIRECT;
2119 susp= 50;
2120
2121 SD_piSetEventTimeout(eto);
2122 OS_piInterDisable(&intLevel);
2123 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2124 SD_piUnMaskInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2125 OS_piInterEnable(intLevel);
2126
2127 PM_opSetNotifyTask_PKT_READY(TS_INFN_TASK);
2128 com=13;
2129 nexit=100;
2130 expected_len=16732;
2131 N_LEN_BUF=0;
2132 gen_init=1;
2133 mode=1;
2134 while(nexit--) {
2135 OS_piTaskSuspend(susp);
2136 DAQ_Format_CMD_Empty(&idaqbuf);
2137 switch(com) {
2138 case 1:
2139 /* scrivi ram, leggi ram */
2140 s = DAQ_Format_CMD_Fill(&data,300,0xbb);
2141 s = DAQ_Format_CMD_Fill(&data2,3,0xcc);
2142
2143 s = DAQ_Format_Cmd2Ram_SetAddress(&idaqbuf,0);
2144 s = DAQ_Format_Cmd2Ram_WriteData(&idaqbuf,&data2);
2145 s = DAQ_Format_Cmd2Ram_EndBlock(&idaqbuf);
2146 s = DAQ_Format_Ram2Daq(&idaqbuf,&ram_readdata);
2147 break;
2148 case 2:
2149 s = DAQ_Format_CMD_Fill(&data,300,0xEE);
2150 s = DAQ_Format_Cmd2Fe(&idaqbuf,&data,DAQ_FE_TRK_1);
2151 s = DAQ_Format_CMD_Fill(&data,500,0x15);
2152 s = DAQ_Format_Cmd2Fe(&idaqbuf,&data,DAQ_FE_CAL_1);
2153 s = DAQ_Format_ReleaseBusy(&idaqbuf);
2154 break;
2155 case 3:
2156 s = DAQ_Format_ReleaseBusy(&idaqbuf);
2157 break;
2158 case 4:
2159 // CH_GetBuf(CH_SUBLIMINALE,&sub);
2160 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2161 break;
2162 case 5:
2163
2164 switch(gen_init) {
2165 case 1:
2166 // CH_GetBuf(CH_default_assembled_0,&sub);
2167 break;
2168 case 2:
2169 // CH_GetBuf(CH_default_assembled_0bis,&sub);
2170 break;
2171 case 3:
2172 // CH_GetBuf(CH_default_assembled_1,&sub);
2173 break;
2174 case 4:
2175 // CH_GetBuf(CH_default_assembled_2,&sub);
2176 break;
2177 case 5:
2178 // CH_GetBuf(CH_default_assembled_2_0,&sub);
2179 break;
2180 case 6:
2181 // CH_GetBuf(CH_default_assembled_2bis,&sub);
2182 break;
2183 case 7:
2184 // CH_GetBuf(CH_default_assembled_3,&sub);
2185 break;
2186 case 8:
2187 // CH_GetBuf(CH_default_assembled_4,&sub);
2188 break;
2189 case 9:
2190 // CH_GetBuf(CH_default_assembled_4_0,&sub);
2191 break;
2192 case 10:
2193 // CH_GetBuf(CH_default_assembled_4_bis,&sub);
2194 break;
2195 case 11:
2196 // CH_GetBuf(CH_default_assembled_5,&sub);
2197 break;
2198 case 12:
2199 // CH_GetBuf(CH_default_assembled_5_0,&sub);
2200 break;
2201 case 13:
2202 // CH_GetBuf(CH_default_assembled_5_bis,&sub);
2203 break;
2204 case 14:
2205 // CH_GetBuf(CH_default_assembled_6,&sub);
2206 break;
2207 default:
2208 s=0xFFF;
2209 break;
2210 }
2211
2212 gen_init++;
2213
2214 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2215 break;
2216 case 6:
2217 // CH_GetBuf(CH_TRACKER_DUMMY_WITH_TRIGGER,&sub);
2218 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2219 break;
2220 case 7:
2221 // CH_GetBuf(CH_elena_load_program_dsp0link1,&sub);
2222 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2223 break;
2224 case 8:
2225 // CH_GetBuf(CH_elena_start_acq_full,&sub);
2226 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2227 case 9:
2228 // CH_GetBuf(CH_elena_read_buffer,&sub);
2229 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2230 break;
2231 case 10:
2232 // CH_GetBuf(CH_flash_non_funziona,&sub);
2233 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2234 break;
2235 case 11:
2236 // CH_GetBuf(CH_ram_funziona,&sub);
2237 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2238 break;
2239 case 12:
2240 CH_GetBuf(CH_assembled_subliminale_scrittura,&sub);
2241 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2242 break;
2243 case 13:
2244 CH_GetBuf(CH_assembled_subliminale_lettura,&sub);
2245 s = DAQ_Format_AppendBuffer(&idaqbuf,sub);
2246 break;
2247
2248 }
2249 if(s != SUCCESSFUL) {
2250 LU_INFN_LOG(LU_WARNING,0xffffffff,__FILEID__,__LINE__,s);
2251 continue;
2252 }
2253
2254
2255 oldmode=PM_pi_GetAcqMode();
2256
2257 if(mode=1) {
2258
2259 PM_pi_SetAcqMode(amode);
2260 PM_pi_SetExpPktCpyFlag(a);
2261 PM_pi_UseCalibrationPage(SM_CALEXP0);
2262 stat=PM_pi_CopyToSRAM(SM_CALEXP0 , idaqbuf.buf , idaqbuf.len);
2263 if(stat != SM_STR_OK)
2264 continue;
2265
2266 switch(a) {
2267 case 1:
2268 PM_opPreparePage(TRUE);
2269 break;
2270 case 2:
2271 ERC32_Force_interrupt(ERC32_INTERRUPT_EXTERNAL_5);
2272 break;
2273 }
2274 e=OS_piEventReceive(OS_EVENT_PKT_READY,RTEMS_WAIT,d,&evout);
2275 if(e == SUCCESSFUL) {
2276 PM_pi_GetPacket(&dest.len,dest.buf);
2277 success++;
2278 LEN_BUF[N_LEN_BUF]=dest.len;
2279 if(dest.len == expected_len && dest.buf[3] == 1 && dest.buf[5] == 2 && dest.buf[7]== 3)
2280 very_success++;
2281 }else{
2282 LEN_BUF[N_LEN_BUF]=-1;
2283 unsuccess++;
2284 }
2285 }else {
2286 s=DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&idaqbuf);
2287 s=DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&dest,TRUE);
2288 }
2289 PM_pi_SetAcqMode(oldmode);
2290
2291 if(N_LEN_BUF >= MAX_LEN_BUF)
2292 N_LEN_BUF=0;
2293 else
2294 N_LEN_BUF++;
2295 }
2296 susp+=100;
2297 }
2298
2299 break;
2300 case 61:
2301 {
2302 unsigned int value_pir = 0x0;
2303 unsigned int cnt = 0,com;
2304 unsigned int ovr_detached = FALSE;
2305
2306 /* fill the body of the command data */
2307
2308
2309 s |= DAQ_Format_CMD_Fill(&data,300,0xbb);
2310 s |= DAQ_Format_CMD_Fill(&data2,3,0xcc);
2311
2312 s |= DAQ_Format_Cmd2Ram_SetAddress(&idaqbuf,0);
2313 s |= DAQ_Format_Cmd2Ram_WriteData(&idaqbuf,&data2);
2314 s |= DAQ_Format_Cmd2Ram_EndBlock(&idaqbuf);
2315 s |= DAQ_Format_Ram2Daq(&idaqbuf,&ram_readdata);
2316
2317 a=1;
2318 b=idaqbuf.len;
2319 c=100000;
2320 d=7000;
2321
2322
2323 OS_piInterDisable(&intLevel);
2324 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2325 SD_piMaskInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2326 OS_piInterEnable(intLevel);
2327 while(1) {
2328 oldmode=PM_pi_GetAcqMode();
2329 PM_pi_SetAcqMode(SM_DAQSETUP);
2330 PM_pi_SetExpPktCpyFlag(a);
2331 PM_pi_UseCalibrationPage(SM_CALEXP0);
2332 PM_pi_CopyToSRAM(SM_CALEXP0 , idaqbuf.buf , idaqbuf.len);
2333 // ERC32_Force_interrupt(ERC32_INTERRUPT_EXTERNAL_5);
2334 PM_opPreparePage(TRUE);
2335 value_pir = 0x0;
2336 cnt = 0;
2337 ovr_detached = FALSE;
2338
2339 while (!(value_pir & 0x01) && (cnt < c))
2340 {
2341 value_pir = (unsigned int) (*(unsigned char *) 0x98000394);
2342
2343 if (value_pir & 0x10) // OVR
2344 ovr_detached = TRUE;
2345
2346 cnt++;
2347 }
2348 if(cnt < c) {
2349 PM_opSetNotifyTask_PKT_READY(TS_INFN_TASK);
2350 PM_opPageHasData();
2351 e=OS_piEventReceive(1,RTEMS_WAIT,d,&evout);
2352 PM_pi_GetPacket(&dest.len ,dest.buf);
2353 }
2354 PM_pi_SetAcqMode(oldmode);
2355
2356
2357 }
2358 }
2359 break;
2360 // TEST PAMELA SOFTWARE dal 62 al .....
2361 case 62:
2362 // Test HB function
2363 {
2364 s = DAQ_Format_CMD_Fill(&data,1024,0xa5);
2365 //s = HB_Store(HB_LOG,1024,data.buf,0);
2366 HB_WriteToPIF();
2367 }
2368 break;
2369 case 63:
2370 // fill MM
2371 {
2372
2373 int i,nt,ns,to;
2374 int cicli=4000;
2375 int c=1;
2376 int s=0,t;
2377 unsigned int pattern=0xF1CAF0CA;
2378 SM_STRSTAT stat;
2379 rtems_event_set out;
2380 SM_ACQMODE m = SM_DAQSETUP;
2381
2382 DAQ_BUFFER_INIT(databuffer);
2383 MC_piSetState(MC_ACTIVE_STATE);
2384 FT_piChangeAcqMode(m);
2385 PM_opSetNotifyTask_SKETCHBOARD_FREE(TS_INFN_TASK);
2386 t=2;
2387 switch(t) {
2388 case 0:
2389 for(i=0;i<TEST_DATALEN;i++)
2390 databuffer.buf[i]= TEST_DATALEN-i;
2391 databuffer.len=1024*20;
2392 break;
2393 case 1:
2394 for(i=0;i<TEST_DATALEN/4;i++)
2395 ((unsigned int*)databuffer.buf) [i]= pattern;
2396 databuffer.len=1024*20;
2397 break;
2398 case 2:
2399 for(i=0;i<TEST_DATALEN;i++)
2400 databuffer.buf[i]= i;
2401 databuffer.len=1024*20;
2402 break;
2403 }
2404 if(c) {
2405 ns=0;
2406 nt=0;
2407 to=2000;
2408 for(i=0;i<cicli;i++) {
2409 OS_piTaskSuspend(s);
2410 s=OS_piEventReceive(OS_EVENT_SKETCHBOARD_FREE,RTEMS_WAIT,to,&out);
2411
2412 if(s!=SUCCESSFUL)
2413 ns++;
2414
2415 stat = PM_pi_StorePacket(databuffer.len,i<2 ? databuffer.buf : NULL,FS_HK);
2416 if(stat != SM_STR_OK)
2417 nt++;
2418 }
2419
2420 }else {
2421 for(i=0;i<cicli;i++)
2422 status = DAQ_SaveBuffer2MM(&databuffer,FS_HK,1000);
2423
2424
2425 }
2426
2427 }
2428 break;
2429 case 64:
2430 {
2431 int i=0;
2432 int w=30000;
2433 SM_ACQMODE m = SM_DAQSETUP;
2434 MC_piSetState(MC_ACTIVE_STATE);
2435 FT_piChangeAcqMode(m);
2436 PM_opSetNotifyTask_SKETCHBOARD_FREE(TS_INFN_TASK);
2437 while(i<1000) {
2438 OS_piTaskSuspend(w);
2439 HB_WriteToPIF();
2440 i++;
2441 }
2442 }
2443 break;
2444 case 65:
2445 /* invia un macrocomando simulato di test_debug */
2446 {
2447 #ifdef SIMULATOR
2448 unsigned short code = 0;
2449 PM_SIM_send_testdebug(code);
2450 #endif
2451 }
2452 break;
2453 case 99:
2454 TS_FULL_CPU_TESTS();
2455 break;
2456 //TEST FUNZIONALI
2457 case 100:
2458 // fill MM pattern crescente utilizzando DAQ_SaveBuffer2MM
2459 {
2460 DAQ_BUFFER_INIT(databuffer);
2461 }
2462 break;
2463 case 101:
2464 // fill MM pattern crescente utilizzando direttamente StorePacket
2465 {
2466 DAQ_BUFFER_INIT(databuffer);
2467 }
2468 break;
2469 case 102:
2470 // flush di HB buffer su MM
2471 {
2472
2473 }
2474 break;
2475
2476 case 103:
2477 // IDAQ Scrittura-Lettura (subliminale)
2478 {
2479 static unsigned int eto = 0xfffff;
2480 DAQ_CMD_BUF *sub;
2481 SM_STRSTAT stat;
2482 static unsigned int timeout=5000;
2483
2484 static SM_ACQMODE acqmode =SM_DAQSETUP;
2485
2486 // KHB_TestBoard(3); // Reset all FE
2487
2488 SD_piSetEventTimeout(eto);
2489 OS_piInterDisable(&intLevel);
2490 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2491 SD_piUnMaskInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2492 OS_piInterEnable(intLevel);
2493
2494 PM_opSetNotifyTask_PKT_READY(TS_INFN_TASK);
2495 switch(bufsel) {
2496 case 1:
2497 CH_GetBuf(CH_assembled_RAM_RW,&sub);
2498 break;
2499 case 2:
2500 //CH_GetBuf(CH_assembled_RAM_solo_scrittura,&sub);
2501 break;
2502 case 3:
2503 CH_GetBuf(CH_assembled_subliminale_lettura,&sub);
2504 break;
2505 case 4:
2506 CH_GetBuf(CH_assembled_SOLO_RAM,&sub);
2507 break;
2508 case 11:
2509 // CH_GetBuf(CH_calo_techno_all_as,&sub);
2510 break;
2511 case 12:
2512 CH_GetBuf(CH_calo_techno_fer_as,&sub);
2513 break;
2514 case 13:
2515 CH_GetBuf(CH_calo_techno_dsp_as,&sub);
2516 break;
2517 case 14:
2518 CH_GetBuf(CH_calo_techno_on_as,&sub);
2519 break;
2520 case 15:
2521 CH_GetBuf(CH_calo_techno_all_only_10_as,&sub);
2522 break;
2523
2524 case 16:
2525 // CH_GetBuf(CH_int_vec_crc_as,&sub);
2526 break;
2527 case 17:
2528 CH_GetBuf(CH_rampa_crc_as,&sub);
2529 break;
2530 case 18:
2531 CH_GetBuf(CH_res_vec_crc_as,&sub);
2532 break;
2533 case 19:
2534 CH_GetBuf(CH_rileggi_crc_as,&sub);
2535 break;
2536
2537 /*
2538 case X:
2539 // il primo argomento e' CH_ + "il nome del file punto dat senza estensione nella dir INFN/commands
2540 CH_GetBuf(CH_nomefiledat,&sub);
2541 break;
2542 */
2543 default:
2544 CH_GetBuf(CH_assembled_SOLO_RAM,&sub);
2545 break;
2546 }
2547 //acqmode = SM_DIRECT;
2548
2549 PM_pi_SetAcqMode(acqmode);
2550
2551 OS_piEventReceive(OS_EVENT_PKT_READY,RTEMS_NO_WAIT,0,&evout);
2552 OS_piEventReceive(OS_EVENT_ETO ,RTEMS_NO_WAIT,0,&evout);
2553
2554 PM_pi_SetExpPktCpyFlag(1); // copy in ram ogni volta
2555 PM_pi_UseCalibrationPage(SM_CALEXP0);
2556 stat=PM_pi_CopyToSRAM(SM_CALEXP0 , sub->buf , sub->len);
2557 if(stat != SM_STR_OK)
2558 {
2559 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,stat);
2560 }
2561
2562 OS_piInterDisable(&intLevel);
2563 PM_opPreparePage(TRUE);
2564 OS_piInterEnable(intLevel);
2565
2566 e=OS_piEventReceive(OS_EVENT_PKT_READY | OS_EVENT_ETO ,RTEMS_WAIT|RTEMS_EVENT_ANY,timeout,&evout);
2567 if(e == SUCCESSFUL) {
2568 if(evout & OS_EVENT_PKT_READY)
2569 PM_pi_GetPacket(&dest.len,dest.buf);
2570 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,dest.len);
2571 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,evout);
2572 }else{
2573 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,e);
2574 }
2575 }
2576 break;
2577
2578 case 104:
2579 // check IDAQ BUS: write and read a buffer on IDAQ MEMORY
2580 {
2581 static unsigned int eto = 0xfffff;
2582 static unsigned int reset_flag=0;
2583 static unsigned int ramcopyfreq = 1000;
2584 DAQ_CMD_BUF *sub;
2585 SM_STRSTAT stat;
2586 BOOL answer = TRUE;
2587 BOOL error;
2588 UINT32 i,j,k,prec,last_error;
2589 static unsigned int timeout=5000;
2590 static BYTE pattern[4] = {0xAA,0x55,0xAA,0x55};
2591 BYTE byte;
2592 BYTE *pbyte;
2593 static SM_ACQMODE acqmode =SM_DAQSETUP;
2594 static UINT32 counter=0;
2595 DAQ_BUFFER_INIT(idaqcmd);
2596
2597 /*
2598 if(reset_flag)
2599 KHB_TestBoard(3); // Reset all FE
2600 */
2601 MC_piSetState(MC_ACTIVE_STATE);
2602 SD_piSetEventTimeout(eto);
2603 OS_piInterDisable(&intLevel);
2604 SD_piClearInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2605 SD_piUnMaskInt(SD_DATA_TO | SD_PAGE_OVR | SD_EVT_TO);
2606 OS_piInterEnable(intLevel);
2607 PM_pi_SetPktType(HB_PKTTYPE_FORCED_FECMD);
2608 PM_pi_SetNotifyTask_PKT_READY(TS_INFN_TASK);
2609
2610 if(PRH_VAR_TS_104pifwrite>0) {
2611 SD_piSetSRAMRWAddress(0);
2612 for(i=0;i<PRH_VAR_TS_104pifwrite;i++)
2613 SD_piWriteSRAM(0x00);
2614 }
2615
2616 switch(bufsel) {
2617 case 1:
2618 CH_GetBuf(CH_assembled_RAM_RW,&sub);
2619 break;
2620 case 2:
2621 //CH_GetBuf(CH_assembled_RAM_solo_scrittura,&sub);
2622 answer=FALSE;
2623 break;
2624 case 3:
2625 CH_GetBuf(CH_assembled_subliminale_lettura,&sub);
2626 break;
2627 case 4:
2628 CH_GetBuf(CH_assembled_SOLO_RAM,&sub);
2629 break;
2630 case 5:
2631 CH_GetBuf(CH_buf_make_acq_full,&sub); // scriveva subliminale
2632 break;
2633 case 6:
2634 CH_GetBuf(CH_buf_make_acq,&sub); //legge
2635 break;
2636 case 7:
2637 CH_GetBuf(CH_buf_init_run,&sub); //scrive?
2638 break;
2639 case 11:
2640 // CH_GetBuf(CH_calo_techno_all_as,&sub);
2641 break;
2642 case 12:
2643 CH_GetBuf(CH_calo_techno_fer_as,&sub);
2644 break;
2645 case 13:
2646 CH_GetBuf(CH_calo_techno_dsp_as,&sub);
2647 break;
2648 case 14:
2649 CH_GetBuf(CH_calo_techno_on_as,&sub);
2650 break;
2651 case 15:
2652 CH_GetBuf(CH_calo_techno_all_only_10_as,&sub);
2653 break;
2654 case 16:
2655 // CH_GetBuf(CH_int_vec_crc_as,&sub);
2656 break;
2657 case 17:
2658 CH_GetBuf(CH_rampa_crc_as,&sub);
2659 break;
2660 case 18:
2661 CH_GetBuf(CH_res_vec_crc_as,&sub);
2662 break;
2663 case 19:
2664 CH_GetBuf(CH_rileggi_crc_as,&sub);
2665 break;
2666 case 20:
2667 sub=&idaqcmd;
2668 TS_GetCustomWriteRam(sub,PRH_VAR_TS_writeaddr_104,
2669 PRH_VAR_TS_kilo_104*1024/4,
2670 pattern[0],pattern[1],pattern[2],pattern[3]);
2671 answer=FALSE;
2672 break;
2673 case 21:
2674 sub=&idaqcmd;
2675 TS_GetCustomReadRam(sub,PRH_VAR_TS_readaddr_104);
2676 break;
2677 case 22:
2678 sub=&idaqcmd;
2679 s=0;
2680 s|=DAQ_Format_CMD_Empty(sub);
2681 s|=DAQ_Format_Cmd2Ram_SetAddress(sub,PRH_VAR_TS_writeaddr_104);
2682 s|=TS_GetCustomReadWriteRamBig(sub,PRH_VAR_TS_writeaddr_104,
2683 PRH_VAR_TS_kilo_104*1024,&counter);
2684 PRH_VAR_TS_writeaddr_104+=PRH_VAR_TS_kilo_104*1024;
2685 answer=FALSE;
2686 break;
2687 case 23:
2688 /* End Block */
2689 sub=&idaqcmd;
2690 s=0;
2691 s|=DAQ_Format_CMD_Empty(sub);
2692 s|=DAQ_Format_Cmd2Ram_EndBlock(sub);
2693 answer=FALSE;
2694 break;
2695 case 24:
2696 /* SetAddress(0) + Ram2Daq/ReadData * TS_len */
2697 sub=&idaqcmd;
2698 s=0;
2699 s|=DAQ_Format_CMD_Empty(sub);
2700 s|=DAQ_Format_Cmd2Ram_SetAddress(sub,0);
2701 for(i=0;i<PRH_VAR_TS_104rate_n && s==0 ;i++) {
2702 s|=DAQ_Format_Ram2Daq_ReadData(sub);
2703 }
2704 if(s)
2705 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,s);
2706 break;
2707 case 25:
2708 /* SetAddress(0) + (WriteData(count) + EndBlock) * TS_len */
2709 sub=&idaqcmd;
2710 s=0;
2711 s|=DAQ_Format_CMD_Empty(sub);
2712 s|=DAQ_Format_Cmd2Ram_SetAddress(sub,0);
2713 for(i=0;i<PRH_VAR_TS_104rate_n && s==0;i++) {
2714 s|=DAQ_Format_OneByteCmd(&data,(BYTE)i);
2715 s|=DAQ_Format_Cmd2Ram_WriteData(sub,&data);
2716 s|=DAQ_Format_Cmd2Ram_EndBlock(sub);
2717 }
2718 if(s)
2719 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,s);
2720 answer=FALSE;
2721 break;
2722 case 26:
2723 /* Read Data */
2724 sub=&idaqcmd;
2725 s=0;
2726 s|=DAQ_Format_CMD_Empty(sub);
2727 s|=DAQ_Format_Ram2Daq_ReadData(sub);
2728
2729 if(s)
2730 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,s);
2731 break;
2732 case 27:
2733 /* Set Address 0 */
2734 sub=&idaqcmd;
2735 s=0;
2736 s|=DAQ_Format_CMD_Empty(sub);
2737 s|=DAQ_Format_Cmd2Ram_SetAddress(sub,0);
2738 if(s)
2739 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,s);
2740 answer=FALSE;
2741 break;
2742 case 28:
2743 /* SetAddress(0) + (WriteData(count) + EndBlock) * TS_len */
2744 sub=&idaqcmd;
2745 s=0;
2746 s|=DAQ_Format_CMD_Empty(sub);
2747 s|=DAQ_Format_Cmd2Ram_SetAddress(sub,0);
2748 j=0;
2749 data.len=2;
2750 for(i=0;i<PRH_VAR_TS_104rate_n && s==0;i++) {
2751 data.buf[0]=(BYTE)j;
2752 j++;
2753 data.buf[1]=(BYTE)j;
2754 j++;
2755 s|=DAQ_Format_Cmd2Ram_WriteData(sub,&data);
2756 s|=DAQ_Format_Cmd2Ram_EndBlock(sub);
2757 }
2758 if(s)
2759 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,s);
2760 answer=FALSE;
2761 break;
2762 case 100:
2763 CH_GetBuf(CH_idaq_lettura_ram_0,&sub);
2764 break;
2765 case 101:
2766 CH_GetBuf(CH_idaq_scrittura_a5a5,&sub);
2767 answer=FALSE;
2768 break;
2769 case 102:
2770 //CH_GetBuf(CH_idaq_scrittura_rampa_10K,&sub);
2771 answer=FALSE;
2772 break;
2773 case 103:
2774 CH_GetBuf(CH_idaq_scrittura_text_lettura_0,&sub);
2775 break;
2776 case 104:
2777 //CH_GetBuf(CH_long_ramp_write_read,&sub);
2778 break;
2779 default:
2780 CH_GetBuf(CH_assembled_SOLO_RAM,&sub);
2781 break;
2782 }
2783
2784 // acqmode = SM_DIRECT;
2785 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,bufsel);
2786
2787 PM_pi_SetAcqMode(acqmode);
2788
2789 OS_piEventReceive(OS_EVENT_PKT_READY,RTEMS_NO_WAIT,0,&evout);
2790 OS_piEventReceive(OS_EVENT_ETO ,RTEMS_NO_WAIT,0,&evout);
2791
2792 PM_pi_SetExpPktCpyFlag(PRH_VAR_TS_104ramcopyfreq); // copy in ram ogni volta
2793 PM_pi_UseCalibrationPage(SM_CALEXP0);
2794 stat=PM_pi_CopyToSRAM(SM_CALEXP0 , sub->buf , sub->len);
2795 if(stat != SM_STR_OK)
2796 {
2797 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,stat);
2798 }
2799
2800 if(answer) {
2801 OS_piInterDisable(&intLevel);
2802 PM_opPreparePage(TRUE);
2803 OS_piInterEnable(intLevel);
2804
2805 e=OS_piEventReceive(OS_EVENT_PKT_READY | OS_EVENT_ETO ,RTEMS_WAIT|RTEMS_EVENT_ANY,timeout,&evout);
2806 }else{
2807 e=DAQ_SendCmdQueue2CMDIF(SM_CALEXP0);
2808 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,e);
2809 }
2810
2811 if(e == SUCCESSFUL && answer) {
2812 if(evout & OS_EVENT_PKT_READY)
2813 {
2814 PM_pi_GetPacket(&dest.len,dest.buf);
2815 switch(checkdata) {
2816 case 1:
2817 if(dest.len != aspettata_len)
2818 {
2819 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,dest.len);
2820 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,sub->len);
2821 }
2822 else
2823 { //else same len check data
2824 int cic;
2825 for(cic=0;cic<aspettata_len;cic++){
2826 if(cic%2)
2827 if(aspettatopari!=dest.buf[cic])
2828 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,cic);
2829 else
2830 if(aspettatodisp!=dest.buf[cic])
2831 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,cic);
2832 }
2833 }
2834 break;
2835 case 2:
2836 if(dest.len != aspettata_len)
2837 {
2838 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,dest.len);
2839 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,sub->len);
2840 }
2841 else
2842 { //else same len check data
2843
2844 }
2845 case 3:
2846 pkt_counter++;
2847 if(acqmode == SM_DIRECT)
2848 prec=0;
2849 else
2850 prec=SM_PKTHEADER_LEN;
2851
2852 last_error=0;
2853 for(a=prec+1;a<dest.len;a++,prec++) {
2854 if(dest.buf[prec] == dest.buf[a]) {
2855 pkt_delta_wrong[a-last_error]++;
2856 last_error=a;
2857 }
2858 }
2859 if(last_error!=0)
2860 pkt_wrong_counter++;
2861 break;
2862 default:
2863 break;
2864 }
2865 }
2866 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,dest.len>>16);
2867 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,dest.len);
2868 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,evout);
2869 }else{
2870 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,e);
2871 }
2872 }
2873 break;
2874
2875 case 105:
2876 {
2877 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,pkt_counter>>16);
2878 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,pkt_counter);
2879 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,pkt_wrong_counter>>16);
2880 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,pkt_wrong_counter);
2881 for(a=0;a<K;a++)
2882 if(pkt_delta_wrong[a] != 0) {
2883 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,a);
2884 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,pkt_delta_wrong[a]>>16);
2885 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,pkt_delta_wrong[a]);
2886 }
2887 }
2888 break;
2889 case 106:
2890 {
2891 int i=0;
2892 int w=30000;
2893 SM_ACQMODE m = SM_DAQSETUP;
2894 MC_piSetState(MC_ACTIVE_STATE);
2895 FT_piChangeAcqMode(m);
2896 PM_opSetNotifyTask_SKETCHBOARD_FREE(TS_INFN_TASK);
2897 OS_piTaskSuspend(w);
2898 HB_WriteToPIF();
2899
2900
2901 }
2902 case 107:
2903 {
2904 while(1)
2905 TS_CRC();
2906 }
2907
2908 break;
2909
2910
2911 case 110:
2912 {
2913 static int test = 1;
2914
2915 status_code status;
2916
2917 switch (test)
2918 {
2919 case 1:
2920 {
2921 /*
2922 status = GS_Request();
2923 if (!status)
2924 status = GS_FillBuffer(1);
2925 if (!status)
2926 status = GS_Request();
2927 if (!status)
2928 status = GS_Purge(1);
2929 */
2930 }
2931 break;
2932 case 2 :
2933 {
2934 int i;
2935
2936 for (i=1; i < 4; i++)
2937 {
2938
2939 /* status = GS_Request();
2940 if (!status)
2941 status = GS_FillBuffer(i);
2942 if (!status)
2943 status = GS_Request();
2944 if (!status)
2945 status = GS_Purge(i); */
2946 }
2947 }
2948 break;
2949 case 3:
2950 {
2951 status_code status;
2952
2953 //status = GS_StandBy(GS_STDBY_ON);
2954
2955 //if (!status)
2956 // status = GS_StandBy(GS_STDBY_OFF);
2957 }
2958 }
2959 }
2960 break;
2961 case 111:
2962 while(1)
2963 TS_BF();
2964 break;
2965
2966 case 112:
2967 {
2968 static UINT16 outbuf_T[13];
2969 static UINT16 outbuf_B[13];
2970 status_code status;
2971
2972 status = SNS_ReadTemperature(SNS_ONE,outbuf_T);
2973 status = SNS_ReadB(SNS_ONE,outbuf_B);
2974 }
2975
2976 break;
2977 case 113:
2978 { /* idaq command status via KHB */
2979 static UINT16 combuf[16],outbuf[16];
2980 static int timeout=10000;
2981 static int volte=1000;
2982 status_code status;
2983 combuf[0] = (UINT16)PRH_VAR_TS_khb_idaq_cmd;
2984 volte=1000;
2985 while(volte--){
2986 status = HK_KHB_Cmd2FE(KHB_IDAQ,1,1,combuf,outbuf,10);
2987 if(status)
2988 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
2989 else
2990 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,outbuf[0]);
2991 }
2992 }
2993 break;
2994 case 114:
2995 HK_KHB_HardReset();
2996 break;
2997 #ifdef SIMULATOR
2998 case 115:
2999 {
3000 /*
3001 TS_SendSimulatedMCMD(CH_MCMD_rampa1);
3002 TS_SendSimulatedMCMD(CH_MCMD_rampa2);
3003 TS_SendSimulatedMCMD(CH_MCMD_rampa3);
3004 TS_SendSimulatedMCMD(CH_MCMD_rampa4);
3005 TS_SendSimulatedMCMD(CH_MCMD_rampa5);
3006 TS_SendSimulatedMCMD(CH_MCMD_rampa6);
3007 TS_SendSimulatedMCMD(CH_MCMD_rampa7);
3008 TS_SendSimulatedMCMD(CH_MCMD_rampa8);
3009 TS_SendSimulatedMCMD(CH_MCMD_rampa9);
3010 TS_SendSimulatedMCMD(CH_MCMD_rampa10);
3011 */
3012 }
3013 break;
3014 case 116:
3015 {
3016 // TS_SendSimulatedMCMD(CH_MCMD_rampa11);
3017 }
3018 break;
3019 case 117:
3020 {
3021 // TS_SendSimulatedMCMD(CH_MCMD_rampa12);
3022 }
3023 break;
3024 #endif
3025
3026 case 118:
3027 { /* SENSOR command status via KHB */
3028 static UINT16 sensor_combuf[16]={0x0000,};
3029 static UINT16 outbuf[16];
3030 static int timeout=100;
3031 static BYTE expected=13;
3032 static int volte=1000;
3033 volte=1000;
3034 while(volte--){
3035 status = HK_KHB_Cmd2FE(KHB_TRACKER_SENSORS_2,1,expected,sensor_combuf,outbuf,timeout);
3036 if(status)
3037 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3038 else
3039 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,outbuf[0]);
3040 }
3041 }
3042 break;
3043 case 119:
3044 { /* idaq command status via KHB */
3045 static UINT16 sensor_combuf[16]={0x0380,};
3046 static BYTE expected=7;
3047 static UINT16 outbuf[16];
3048 static int timeout=100;
3049 static int volte=1000;
3050 volte=1000;
3051 while(volte--){
3052 status=HK_KHB_Cmd2FE(KHB_TRACKER_SENSORS_2,1,expected,sensor_combuf,outbuf,timeout);
3053 if(status)
3054 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3055 else
3056 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,outbuf[0]);
3057 }
3058 }
3059 break;
3060
3061 case 120:
3062 { /* idaq command status via KHB */
3063 static UINT16 combuf[16],outbuf[16];
3064 static int timeout=10000;
3065 status_code status;
3066 combuf[0] = (UINT16)PRH_VAR_TS_khb_idaq_cmd;
3067 status = HK_KHB_Cmd2FE(KHB_IDAQ,1,1,combuf,outbuf,10);
3068 if(status)
3069 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3070 else
3071 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,outbuf[0]);
3072 }
3073 break;
3074
3075 case 121:
3076 { /* SENSOR command status via KHB */
3077 static UINT16 sensor_combuf[16]={0x0000,};
3078 static UINT16 outbuf[16];
3079 static int timeout=100;
3080 static BYTE expected=13;
3081 status = HK_KHB_Cmd2FE(KHB_TRACKER_SENSORS_2,1,expected,sensor_combuf,outbuf,timeout);
3082 if(status)
3083 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3084 else
3085 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,outbuf[0]);
3086 }
3087 break;
3088 case 122:
3089 { /* idaq command status via KHB */
3090 static UINT16 sensor_combuf[16]={0x0380,};
3091 static BYTE expected=7;
3092 static UINT16 outbuf[16];
3093 static int timeout=100;
3094 status=HK_KHB_Cmd2FE(KHB_TRACKER_SENSORS_2,1,expected,sensor_combuf,outbuf,timeout);
3095 if(status)
3096 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3097 else
3098 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,outbuf[0]);
3099 }
3100 break;
3101 case 123: {
3102 static int value=0;
3103 static int blen=64*1024;
3104 static UINT32 pattern=0xAA;
3105 PM_pi_SetNotifyTask_SKETCHBOARD_FREE(TS_INFN_TASK);
3106 // s=OS_piEventClear(OS_EVENT_SKETCHBOARD_FREE);
3107 DAQ_BUFFER_INIT(hbuf);
3108 switch(value) {
3109 case 0:
3110 for(i=0;i<hbuf.size;i++)
3111 hbuf.buf[i]=(BYTE)(i & 0xff);
3112 hbuf.len=blen;
3113 break;
3114 case 1:
3115 for(i=0;i<hbuf.size/4;i++)
3116 ((unsigned int*)hbuf.buf) [i]= pattern;
3117 hbuf.len=blen;
3118 break;
3119 }
3120 status = DAQ_SaveBuffer2MM(&hbuf,FS_HK,1000);
3121 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3122 }
3123 break;
3124
3125 case 124:
3126 QS_piCounterCalibration(100000);
3127 break;
3128 case 125:
3129 QS_piUsageStart();
3130 break;
3131 case 126:
3132 {
3133 UINT16 usage;
3134 QS_piUsageStop(&usage);
3135 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,usage);
3136 }
3137 break;
3138 case 127:
3139 {
3140 UINT16 usage,i,j;
3141 static volatile UINT32 susp=2,n=1000,crc=100,calib=100000;
3142 QS_piCounterCalibration(calib);
3143 QS_piUsageStart();
3144 for(i=0;i<n;i++) {
3145 OS_piTaskSuspend(susp);
3146 for(j=0;j<crc;j++)
3147 TS_CRC();
3148 }
3149 QS_piUsageStop(&usage);
3150 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,usage);
3151 }
3152 break;
3153 default:
3154 break;
3155 }
3156
3157 }
3158 }
3159 #endif // DURTY_MODE
3160 }
3161
3162
3163 void TS_RM_Test(UINT32 c1,UINT32 c2,UINT32 c3) {
3164 static UINT32 blen=64*1024;
3165 static UINT32 w=0;
3166 static UINT32 pattern=0xAA;
3167 status_code status,s;
3168 UINT32 i;
3169 UINT16 sw;
3170 SM_ACQMODE oldmode;
3171
3172 switch(c1) {
3173 case 1:
3174 PM_pi_SetNotifyTask_SKETCHBOARD_FREE(RM_INFN_TASK);
3175 //oldmode = PM_pi_GetAcqMode();
3176 FT_piChangeAcqMode(SM_DIRECT);
3177 DAQ_BUFFER_INIT(hbuf);
3178 switch(w) {
3179 case 0:
3180 for(i=0;i<hbuf.size;i++)
3181 hbuf.buf[i]=(BYTE)(i & 0xff);
3182 hbuf.len=blen;
3183 break;
3184 case 1:
3185 for(i=0;i<hbuf.size/4;i++)
3186 ((unsigned int*)hbuf.buf) [i]= pattern;
3187 hbuf.len=blen;
3188 break;
3189 }
3190 status = DAQ_SaveBuffer2MM(&hbuf,FS_HK,1000);
3191 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3192 //FT_piChangeAcqMode(oldmode);
3193 break;
3194 case 2:
3195 TRK_Initialization();
3196 break;
3197 case 3:
3198 TRK_Calibration();
3199 break;
3200 case 4:
3201 {
3202 UINT32 value;
3203 HK_ReadKHBAlarmRegister(&value);
3204 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,value);
3205 }
3206 break;
3207 case 5:
3208 {
3209 UINT16 value;
3210 HK_ReadKHBStatusRegister(&value);
3211 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,value);
3212 }
3213 break;
3214 case 6:
3215 CAL_Initialization();
3216 break;
3217 case 7:
3218 CAL_Calibration();
3219 break;
3220 case 8:
3221 TRG_Initialization();
3222 break;
3223 case 9:
3224 RM_LogBuffer_128_DoLog(c2,c3);
3225 break;
3226 case 10: // formatta eprom quando sto in default mode
3227 status = PRH_FormatEEPROM();
3228 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3229 break;
3230 case 11: // legge i valori correnti della eeprom e li mette in mem
3231 status = PRH_ReadCurrentParam();
3232 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3233 break;
3234 case 12:
3235 status = PRH_ReadDefaultParam();
3236 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3237 break;
3238 case 13:
3239 status = PRH_WriteCurrentParam();
3240 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3241 break;
3242 case 15:
3243 status=DAQ_ReadStatusWord(&sw);
3244 if(status)
3245 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3246 else
3247 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,sw);
3248 break;
3249 default:
3250 break;
3251 }
3252
3253 }
3254
3255
3256
3257 /* this function is executed by PamManager */
3258 void TS_PamManager(unsigned short code,
3259 unsigned short value1,
3260 unsigned short value2,
3261 unsigned short value3,
3262 unsigned short value4) {
3263 UINT32 i;
3264 static UINT32 blen = 24*1024;
3265 UINT32 fid,v;
3266 static UINT32 pattern = 0xCAFECAFE;
3267 status_code status,s;
3268 PWR_IPM6 ipm;
3269 CM_ON_OFF oo;
3270 GS_REPLY_STRUCT gas_status;
3271 UINT16 *gas_word=(UINT16*)&gas_status,sw;
3272 int n;
3273 int sleep;
3274 /*@LOG ciao bello */
3275 // LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,code); /* cicciopasticcio */
3276 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,code); /* frocione */
3277 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,code);
3278 /*@LOG capperi */
3279 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,code);
3280 switch(code) {
3281 case 0:
3282 MH_SetGOM(MH_GOM_FLUSH_HB);
3283 break;
3284 case 1:
3285 MH_SetGOM(MH_GOM_ACQUISITION);
3286 break;
3287 case 2:
3288 MH_SetGOM(MH_GOM_MAINTENANCE);
3289 break;
3290 #ifdef DURTY_MODE
3291 case 3:
3292 TS_SndTestCode_INFN(value1);
3293 break;
3294 #endif // DURTY_MODE
3295 case 4:
3296 PM_pi_EnableStore_In_DataTimeOut();
3297 break;
3298 case 5:
3299 PM_pi_DisableStore_In_DataTimeOut();
3300 break;
3301 case 6:
3302 bufsel=value1;
3303 break;
3304 case 7:
3305 RM_LogStatus();
3306 break;
3307 case 8:
3308 //LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,HB_SpaceLeft());
3309 break;
3310 case 9:
3311 PM_pi_SetNotifyTask_SKETCHBOARD_FREE(TS_INFN_TASK);
3312 PM_opPageWasSaved(FS_HK);
3313 break;
3314 case 10:
3315 RM_SendHBStoreRequest();
3316 break;
3317 case 11:
3318 PM_EnableStoreTMTC();
3319 break;
3320 case 12:
3321 PM_DisableStoreTMTC();
3322 break;
3323 case 13:
3324 PM_EnableTMTC();
3325 break;
3326 case 14:
3327 PM_DisableTMTC();
3328 break;
3329 case 15:
3330 SD_piPIFReset();
3331 break;
3332 case 16:
3333 KHB_InitBoard();
3334 break;
3335 case 17:
3336 FS_piLogInfo();
3337 break;
3338 case 18:
3339 //KHB_TestBoard(value);
3340 break;
3341 case 19:
3342 {
3343 unsigned int DataValue;
3344 int i;
3345 static int min=0,max=4;
3346 for(i = min ; i < max; i++){
3347 HK_GetTMValue (TM_DEA_ANA_1+min, &DataValue);
3348 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,DataValue>>16);
3349 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,DataValue);
3350 }
3351 }
3352 break;
3353 case 20:
3354 KHB_Log();
3355 break;
3356 case 21:
3357 for(fid=0;fid<LU_FILEID_N;fid++)
3358 LU_MASK(fid) |= LU_DEBUG_TRACE;
3359 break;
3360 case 22:
3361 for(fid=0;fid<LU_FILEID_N;fid++)
3362 if(LU_MASK(fid) & LU_DEBUG_TRACE)
3363 LU_MASK(fid) &= ~LU_DEBUG_TRACE;
3364 break;
3365 case 23:
3366 GS_SendCodeGasManager(GS_TEST,NULL);
3367 break;
3368 case 24:
3369 GS_SendCodeGasManager(GS_START_UP,NULL);
3370 break;
3371 case 25:
3372 GS_SendCodeGasManager(GS_FILLINPUT_BUFFER,NULL);
3373 break;
3374 case 29:
3375 GS_SendCodeGasManager(GS_CONTAINER_PURGE,NULL);
3376 break;
3377 case 30:
3378 GS_SendCodeGasManager(GS_TRD_PURGE,NULL);
3379 break;
3380 case 31:
3381 GS_SendCodeGasManager(GS_TECH_PURGE,NULL);
3382 break;
3383 case 32:
3384 GS_SendCodeGasManager(GS_ABORT_OP,NULL);
3385 break;
3386 case 33:
3387 GS_GasResume();
3388 break;
3389 case 34:
3390 GS_InitGasBoard();
3391 break;
3392 case 41:
3393 PWR_SwitchOn_IPM(TM_KRB_IPM1);
3394 break;
3395 case 42:
3396 PWR_SwitchOn_IPM(TM_KRB_IPM2);
3397 break;
3398 case 43:
3399 PWR_SwitchOn_IPM(TM_KRB_IPM3);
3400 break;
3401 case 44:
3402 PWR_SwitchOn_IPM(TM_KRB_IPM4);
3403 break;
3404 case 45:
3405 PWR_SwitchOn_IPM(TM_KRB_IPM5);
3406 break;
3407 case 46:
3408 PWR_SwitchOn_IPM(TM_KRB_IPM6);
3409 break;
3410 case 47:
3411 PWR_SwitchOff_IPM(TM_IPM12_OFF);
3412 break;
3413 case 48:
3414 PWR_SwitchOff_IPM(TM_IPM34_OFF);
3415 break;
3416 case 49:
3417 PWR_SwitchOff_IPM(TM_IPM56_OFF);
3418 break;
3419 case 60:
3420 for(ipm=PWR_IPM_1;ipm<=PWR_IPM_6;ipm++) {
3421 PWR_KRB_IPM(ipm,&oo);
3422 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,oo);
3423 }
3424 case 61:
3425 GS_COMRequest(&gas_status);
3426 gas_word=(UINT16*)&gas_status;
3427 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,*(gas_word++));
3428 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,*(gas_word++));
3429 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,*(gas_word++));
3430 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,*(gas_word++));
3431 break;
3432 case 62:
3433 GS_HLStandBy(GS_STDBY_ON);
3434 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,0);
3435 break;
3436 case 63:
3437 GS_HLStandBy(GS_STDBY_OFF);
3438 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,0);
3439 break;
3440 case 64:
3441 HK_SendTC(TM_GAS_HOT_36V_OFF,1);
3442 break;
3443 case 65:
3444 HK_SendTC(TM_GAS_COLD_36V_OFF,1);
3445 break;
3446 case 66:
3447 HK_SendTC(TM_KHB_PWR_33_HOT_ON,1);
3448 break;
3449 case 67:
3450 HK_SendTC(TM_KHB_PWR_33_COLD_ON,1);
3451 break;
3452 case 68:
3453 HK_SendTC(TM_KHB_PWR_33_OFF,1);
3454 break;
3455 case 69:
3456
3457 #define LOG_TM(id,line) do { \
3458 HK_GetTMValue(id,&v); \
3459 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,line,v); \
3460 } while(0)
3461
3462 LOG_TM(TM_GAS_HOT_ALARM,__LINE__);
3463 LOG_TM(TM_GAS_COLD_ALARM,__LINE__);
3464 LOG_TM(TM_GAS_ENABLED,__LINE__);
3465 LOG_TM(TM_GAS_LPS1,__LINE__);
3466 LOG_TM(TM_GAS_LPS2,__LINE__);
3467 LOG_TM(TM_GAS_LPS3,__LINE__);
3468 LOG_TM(TM_GAS_LPS4,__LINE__);
3469 LOG_TM(TM_GAS_LPS5,__LINE__);
3470 LOG_TM(TM_GAS_LPS6,__LINE__);
3471 LOG_TM(TM_GAS_HPS1,__LINE__);
3472 LOG_TM(TM_GAS_HPS2,__LINE__);
3473 LOG_TM(TM_GAS_TS_OUT_TEMP,__LINE__);
3474 LOG_TM(TM_GAS_TH,__LINE__);
3475
3476 break;
3477 case 80:
3478 s=PRH_var_write2eeprom(PRH_EEPROM_CURRENT,value1);
3479 break;
3480 case 81:
3481 s=PRH_var_write2eeprom(PRH_EEPROM_CURRENT,value1);
3482 break;
3483 case 82:
3484 s=PRH_var_read_eeprom(PRH_EEPROM_CURRENT,value1);
3485 break;
3486 case 83:
3487 s=PRH_arr_write2eeprom(PRH_EEPROM_CURRENT,value1);
3488 break;
3489 case 84:
3490 s=PRH_arr_read_eeprom(PRH_EEPROM_CURRENT,value1);
3491 break;
3492 case 85:
3493 s=PRH_tab_write2eeprom(PRH_EEPROM_CURRENT,value1);
3494 break;
3495 case 86:
3496 s=PRH_tab_read_eeprom(PRH_EEPROM_CURRENT,value1);
3497 break;
3498 case 87:
3499 HK_KHB_HardReset();
3500 break;
3501 case 89:
3502 MH_SetTestParam(value1,value2,value3);
3503 MH_SetGOM(MH_GOM_TEST);
3504 break;
3505 case 90:
3506 HK_KHB_HardReset();
3507 break;
3508 case 91:
3509 MH_SetGOM(MH_GOM_INITIALIZATION);
3510 break;
3511 case 92:
3512 MH_SetGOM(MH_GOM_CALIBRATION);
3513 break;
3514 case 93:
3515 MH_SetGOM(MH_GOM_ACQUISITION);
3516 break;
3517 case 94:
3518 FT_piInitFileSystem();
3519 break;
3520 case 95:
3521 status=DAQ_ReadStatusWord(&sw);
3522 if(status)
3523 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
3524 else
3525 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,sw);
3526 break;
3527 case 96:
3528 QS_piCounterCalibration(value1);
3529 break;
3530 case 97:
3531 QS_piUsageStart();
3532 break;
3533 case 98:
3534 {
3535 UINT16 usage;
3536 QS_piUsageStop(&usage);
3537 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,usage);
3538 }
3539 break;
3540 case 99:
3541 {
3542 static UINT16 usage;
3543 static UINT32 i,j;
3544 static UINT32 susp=2,n=1000,crc=100;
3545 n=value1;
3546 crc=value2;
3547 QS_piUsageStart();
3548 for(i=0;i<n;i++) {
3549 OS_piTaskSuspend(susp);
3550 for(j=0;j<crc;j++)
3551 TS_CRC();
3552 }
3553 QS_piUsageStop(&usage);
3554 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,usage);
3555 }
3556 break;
3557 }
3558 }
3559
3560 #ifdef SIMULATOR
3561
3562 static status_code TS_SwapSimulatedMCMD(CH_COMMANDS bufid) {
3563 int i;
3564 char tmp;
3565 DAQ_CMD_BUF *b;
3566 CH_GetBuf(bufid,&b);
3567
3568 }
3569
3570 status_code TS_SendSimulatedMCMD(CH_COMMANDS bufid) {
3571 /*
3572 BI_if1553BLoadMCMD( unsigned int subaddId,
3573 unsigned short int* BI_1553MCMDBuffer,
3574 unsigned short int* BI_1553MCMDACKWord )
3575 */
3576 MA_HEADER_MCMD mcmdHeader;
3577 UINT16 *BI_1553MCMDBuffer,*w;
3578 UINT32 nwords16;
3579 status_code status;
3580 unsigned int checksum, i;
3581 int mcmdttag_direct;
3582 MsgTsk sndMsg;
3583 BYTE tmp;
3584 unsigned int mcmdType,mcmdId;
3585 unsigned char* pbyte;
3586
3587 DAQ_CMD_BUF *b;
3588 CH_GetBuf(bufid,&b);
3589
3590 /* use the 'crc16' field as flag to see if the swap has already done.
3591 swapping is necessary because Little Endian to Big Endian conversion */
3592
3593 if(b->crc16 != 0x1234)
3594 for(b->crc16=0x1234,i=0;i<(b->len/2);i++) {
3595 tmp=b->buf[2*i];
3596 b->buf[2*i]=b->buf[2*i+1];
3597 b->buf[2*i+1]=tmp;
3598 }
3599
3600 BI_1553MCMDBuffer=(UINT16*)b->buf;
3601 if(b->len & 1) {
3602 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,mcmdType);
3603 return CM_RC_UNDEFINED;
3604 }
3605 nwords16=b->len/2;
3606
3607 mcmdId = BI_1553MCMDBuffer[1] & 0xFF;
3608 MA_piGetMCMDType(mcmdId, &mcmdType);
3609 if( mcmdType == NULL_MCMD ) {
3610 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,mcmdType);
3611 return CM_RC_UNDEFINED;
3612 }
3613
3614 mcmdHeader.Type = mcmdType;
3615
3616 // verifies the checksum
3617 checksum = 0;
3618 for (i=0, pbyte = (unsigned char*)BI_1553MCMDBuffer; i<2*(nwords16-1); pbyte++, i++) {
3619 checksum += *pbyte;
3620 }
3621
3622 if( (checksum & 0xFF) != (BI_1553MCMDBuffer[nwords16-1] & 0xFF) )
3623 {
3624 LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,mcmdType);
3625 return CM_RC_UNDEFINED;
3626 }
3627
3628 if( BI_1553MCMDBuffer[1] & BI_MCMD_TT_MASK )
3629 {
3630 mcmdHeader.TimeTag = BI_1553MCMDBuffer[3]<<16 | BI_1553MCMDBuffer[4];
3631 mcmdttag_direct = TIMETAG_MCMD;
3632 sndMsg.Code = MT_STORE_TIMETAG_MCMD;
3633 }
3634 else
3635 {
3636 mcmdHeader.TimeTag = 0;
3637 mcmdttag_direct = IMMEDIATE_MCMD;
3638 sndMsg.Code = MD_MCMD_EXEC;
3639 }
3640
3641 mcmdHeader.Length = BI_1553MCMDBuffer[2] & 0x0FFF;
3642
3643 if( MA_piGetBufferMCMD(&mcmdHeader.PtrMCMD, mcmdttag_direct)
3644 != SUCCESSFUL )
3645 {
3646 /* internal error: reject the MCMD */
3647 return CM_RC_UNSATISFIED;
3648 }
3649 else
3650 {
3651 memcpy((unsigned short int*)mcmdHeader.PtrMCMD,
3652 BI_1553MCMDBuffer,
3653 2*mcmdHeader.Length);
3654 *(MA_HEADER_MCMD*)sndMsg.Info = mcmdHeader;
3655 sndMsg.LlInfo = sizeof(MA_HEADER_MCMD);
3656 if( mcmdttag_direct == TIMETAG_MCMD )
3657 {
3658 status = MT_piSndMsgTTManager(&sndMsg);
3659
3660 if( status == HA_E1_TIMETAG_NOT_ALLOWED)
3661 {
3662 // BI_1553MCMDACKWord[0] |= BI_MCMD_NOT_OK | BI_MCMD_WRONG_TIMETAG;
3663 *(unsigned short int*)&sndMsg.Info[6] = status;
3664 /* Extract parameters and delete MCMD from partition */
3665 //INFN_PATCH MA_piDelBufferMCMD(mcmdHeader.PtrMCMD,TIMETAG_MCMD,WAIT,NO_TIMEOUT);
3666 MA_piDelBufferMCMD(mcmdHeader.PtrMCMD,TIMETAG_MCMD);
3667 }
3668 else if(status == HA_E1_MCMD_QUEUE_FULL )
3669 {
3670 //BI_1553MCMDACKWord[0] |= BI_MCMD_NOT_OK | BI_MCMD_TTQUEUE_FULL;
3671 *(unsigned short int*)&sndMsg.Info[6] = status;
3672 /* Extract parameters and delete MCMD from partition */
3673 //INFN_PATCH MA_piDelBufferMCMD(mcmdHeader.PtrMCMD,TIMETAG_MCMD,WAIT,NO_TIMEOUT);
3674 MA_piDelBufferMCMD(mcmdHeader.PtrMCMD,TIMETAG_MCMD);
3675 }
3676 }
3677 else
3678 {
3679 status = MD_piSndMsgMCMDDispatcher(&sndMsg);
3680 }
3681 }
3682 }
3683
3684 #endif // ifdef SIMULATOR
3685
3686 /*****************************************************************************/
3687 /* TS_piSndMsgTest_INFN
3688 *
3689 *
3690 * Input parameters: NONE
3691 *
3692 * Output parameters: NONE
3693 *
3694 */
3695 /*****************************************************************************/
3696
3697 status_code TS_SndMsgTest_INFN (MsgTsk* SndMsg)
3698 {
3699 status_code status;
3700
3701 status =OS_piMsgQueueSend_INFN(TS_INFN_MAILBOX,(void*)SndMsg,sizeof(MsgTsk));
3702 return (status);
3703 }
3704
3705
3706

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