/[PAMELA software]/quicklook/dataToXML/Data/compilationInfo/src/INFN/TRK_Tracker_INFN.c
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Annotation of /quicklook/dataToXML/Data/compilationInfo/src/INFN/TRK_Tracker_INFN.c

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Revision 1.1.1.1 - (hide annotations) (download) (vendor branch)
Tue Apr 25 09:00:20 2006 UTC (19 years, 2 months ago) by kusanagi
Branch: MAIN
CVS Tags: dataToXML1_02/01, dataToXML1_02/00, dataToXML1_03/00, dataToXML1_03/01, dataToXML1_00/00, firstRelease, dataToXML1_01/00, dataToXML1_03_02, HEAD
Changes since 1.1: +0 -0 lines
File MIME type: text/plain 
These program extract in an XML format the info contained into the ROOT files generated by YODA from the PAMELA data. To visualize the XML files in a more human readable format a collection of XSL files are given in the Data subfolder.
1 kusanagi 1.1 /****************************************************************************
2     * F i l e D a t a
3     * $Id: TRK_Tracker_INFN.c,v 1.80 2005/03/20 18:27:29 sebastiani Exp $
4     * $Revision: 1.80 $
5     * $Date: 2005/03/20 18:27:29 $
6     * $RCSfile: TRK_Tracker_INFN.c,v $
7     *
8     ****************************************************************************
9     * S W D e v e l o p m e n t E n v i r o n m e n t
10     *
11     * $Author: sebastiani $
12     * :
13     ****************************************************************************
14     * U p d a t i n g
15    
16     * $Log: TRK_Tracker_INFN.c,v $
17     * Revision 1.80 2005/03/20 18:27:29 sebastiani
18     * TRK calibration: many bugs found and fixed in TRK_Check (many & , << , >> errors!)
19     *
20     * Revision 1.79 2005/03/06 14:54:46 sebastiani
21     * version running on 06 03 2005
22     *
23     * Revision 1.78 2005/02/24 17:52:22 sebastiani
24     * PWR_CMD2PSB accept more params cause bugfixing (2) PRH_ARR_PSB_COMMANDS introduced instead of PRH_VAR_xxxxx
25     *
26     * Revision 1.77 2005/02/22 18:09:25 sebastiani
27     * various bugfixes
28     *
29     * Revision 1.76 2005/02/21 14:26:01 sebastiani
30     * TSB bugfixes.
31     *
32     * Revision 1.75 2005/02/21 08:58:29 sebastiani
33     * all log comments completed
34     *
35     * Revision 1.74 2004/12/22 09:35:36 sebastiani
36     * CH_PARAMBUF_SET_ATO_ETO(TRK_TRAILER_PRG[i],8,0) bugfix
37     * should be 0,8 instead
38     *
39     * Revision 1.73 2004/12/21 14:16:35 sebastiani
40     * *** empty log message ***
41     *
42     * Revision 1.72 2004/12/20 14:02:04 faber
43     * @LOG entry introduced in all ALM_WriteLog occurrences
44     *
45     * Revision 1.70 2004/12/15 09:36:23 sebastiani
46     * TRK_WRITE2RAM removed: DAQ_NO_STORE_RAM used instead; TRK_Send_ReadCalibrationCmd and TRK_Assemble_ReadCalibrationCmd introduced; many other fixes and flow little changes in the calibration
47     *
48     * Revision 1.69 2004/11/19 15:41:50 sebastiani
49     * *** empty log message ***
50     *
51     * Revision 1.68 2004/11/19 15:14:52 sebastiani
52     * PRH_EXTERN_{VAR,ARR,TABLE} removed and put them on the autogenerated parameter heeader file
53     *
54     * Revision 1.67 2004/10/08 07:27:23 sebastiani
55     * *** empty log message ***
56     *
57     * Revision 1.66 2004/10/06 16:40:23 faber
58     * Sensor board reading is fixed size in MM (always 13 words)
59     *
60     * Revision 1.65 2004/09/28 15:36:25 sebastiani
61     * interrupt manager fix
62     *
63     * Revision 1.64 2004/09/27 15:42:43 alfarano
64     * tracker sensor board functions
65     *
66     * Revision 1.63 2004/09/22 15:54:54 alfarano
67     * S4 functions
68     *
69     * Revision 1.62 2004/09/17 15:52:00 faber
70     * fix command queue Cmd2Fe/Fe2Daq right invocation for Test funcion inf TOF and TRG
71     *
72     * Revision 1.61 2004/09/17 15:01:00 faber
73     * LU_INFN_LOG flags fixing
74     *
75     * Revision 1.60 2004/09/13 14:16:53 faber
76     * ErrorHandler for TOF/TRG + Test function TOF/TRG
77     *
78     * Revision 1.59 2004/08/31 09:13:20 sebastiani
79     * fix warning
80     *
81     * Revision 1.58 2004/08/31 09:08:35 sebastiani
82     * fix warning
83     *
84     * Revision 1.57 2004/08/27 13:30:39 alfarano
85     * cvs header
86     *
87     * Revision 1.1 2003/10/03 16:12:26 faber
88     * *** empty log message ***
89     *
90     *
91     *****************************************************************************/
92     /*============================= Include File ================================*/
93    
94    
95     #include <src/INFN/LU_SourceFileID_INFN.h>
96     #define __FILEID__ _TRK_Tracker_INFN__c
97     #include <src/INFN/PRH_ParamHandler_INFN.h>
98     #include <src/INFN/LU_LogUtility_INFN.h>
99     #include <src/INFN/PRH_ParamHandler_INFN_auto.h>
100     LU_DECL_MASK();
101    
102     #include <src/INFN/CM_Common_INFN.h>
103     #include <src/INFN/TRK_Tracker_INFN.h>
104     #include <src/INFN/CH_CommandHandler_INFN.h>
105     #include <src/INFN/TRG_Trigger_INFN.h>
106     #include <src/INFN/RM_RunManager_INFN.h>
107     #include <src/INFN/KHB_Driver_INFN.h>
108     #include <src/INFN/HB_HKBuffer_INFN.h>
109     #include <src/SRAMManager/SRAMDriver/SD_SRAMDriver_p.h>
110     #include <src/SRAMManager/SRAMPageManager/SM_SRAMPageManager_p.h>
111     #include <src/FileManager/MMSUManager/FT_MMSUManager_p.h>
112     #include <src/INFN/HK_Manager_INFN.h>
113     #include <src/INFN/ALM_Alarm_INFN.h>
114     #include <src/INFN/MH_ModeHandler_INFN.h>
115     #include <src/INFN/PWR_PowerHandler_INFN.h>
116    
117     /*============================ External define ================================*/
118    
119    
120     DAQ_DECLBUF(TRK_command,1024);
121     DAQ_DECLBUF(TRK_TempPif0,TRK_MAXTEMPBUFFER);
122     DAQ_DECLBUF(TRK_TempPif1,TRK_MAXTEMPBUFFER);
123     DAQ_DECLBUF(TRK_TempPif2,TRK_MAXTEMPBUFFER);
124     DAQ_DECLBUF(TRK_TempPif3,TRK_MAXTEMPBUFFER);
125     DAQ_DECLBUF(TRK_daq_reply0,128*1024);
126     DAQ_DECLBUF(TRK_daq_reply1,128*1024);
127     DAQ_DECLBUF(TRK_tempbuf,TRK_MAX_LOG_SIZE);
128    
129    
130     static DAQ_CMD_BUF TRK_NUMBER_DSP[1+2][6];
131    
132     static DAQ_CMD_BUF TRK_OPMODE_COMP[6];
133    
134     static DAQ_CMD_BUF TRK_OPMODE_SPEC[6];
135    
136     static DAQ_CMD_BUF TRK_PROGRAM;
137    
138     static DAQ_CMD_BUF TRK_TRAILER_PRG[6];
139    
140     static BOOL TRK_Bfield_flag=TRUE;
141    
142     extern BOOL RM_Init_Before_Calib;
143     /*============================ Global define ================================*/
144    
145     #define TRK_SKIP_HEADER SM_PKTHEADER_LEN
146    
147     #define TRK_MASK_BASE_ID CH_TRK_MASK_064
148     #define TRK_MASK_BASE_OFFSET 64
149     #define TRK_PROG_ADR_BASE_ID CH_TRK_PROG_ADR_01
150     #define TRK_LOAD_DATA_BASE_ID CH_TRK_LOAD_DATA_0
151     #define TRK_HEADER_PRG_BASE_ID CH_TRK_HEADER_PRG_0
152     #define TRK_START_BASE_ID CH_TRK_START_0
153     #define TRK_CALIB_ADR_BASE_ID CH_TRK_CALIB_ADR_0_1_101
154     #define TRK_CALIB_ADR_BASE_OFFSET 101
155     #define TRK_SET_CALIB_NORMAL_BASE_ID CH_TRK_SET_CALIB_NORMAL_0
156     #define TRK_SET_CALIB_SPECIAL_BASE_ID CH_TRK_SET_CALIB_SPECIAL_0
157     #define TRK_EVENT_ACQ_BASE_ID CH_TRK_EVENT_ACQ_0
158     #define TRK_READ_HEADER_BASE_ID CH_TRK_READ_HEADER_0
159     #define TRK_READ_LADDER1_BASE_ID CH_TRK_READ_LADDER1_0
160     #define TRK_READ_LADDER2_BASE_ID CH_TRK_READ_LADDER2_0
161     #define TRK_READ_LADDER3_BASE_ID CH_TRK_READ_LADDER3_0
162     #define TRK_READ_INPUT_BASE_ID CH_TRK_READ_INPUT_0
163     #define TRK_WRITE_DMTEST_DSP_BASE_ID CH_TRK_WRITE_DMTEST_DSP_0
164     #define TRK_WRITE_PMTEST_DSP_BASE_ID CH_TRK_WRITE_PMTEST_DSP_0
165     #define TRK_WRITE_PROGTEST_DSP_BASE_ID CH_TRK_WRITE_PROGTEST_DSP_0
166     #define TRK_READ_DMTEST_DSP_BASE_ID CH_TRK_READ_DMTEST_DSP_0
167     #define TRK_READ_PMTEST_DSP_BASE_ID CH_TRK_READ_PMTEST_DSP_0
168     #define TRK_RESET_DSP_BASE_ID CH_TRK_RESET_DSP_0
169    
170    
171    
172    
173    
174     /*============================== global types ==============================*/
175    
176    
177    
178     /*=========================== Structure define ==============================*/
179    
180    
181     /*============================ Enumerate define =============================*/
182    
183    
184     UINT32 TRK_ALARM_MASK[2];
185     static UINT32 TRK_status;
186     static UINT32 TRK_calib_used;
187    
188     static void TRK_Init_TRK_NUMBER_DSP() {
189     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,1,0);
190     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,1,1);
191     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,1,2);
192     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,1,3);
193     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,1,4);
194     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,1,5);
195     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,2,0);
196     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,2,1);
197     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,2,2);
198     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,2,3);
199     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,2,4);
200     DAQ_INIT_BUF_FROM_PARAMBUF_AS_TAB(TRK_NUMBER_DSP,2,5);
201     }
202    
203     status_code TRK_Get_TRK_NUMBER_DSP(BYTE i,BYTE j,DAQ_CMD_BUF **p) {
204     *p= & (TRK_NUMBER_DSP[i][j]);
205     }
206    
207     static void TRK_Init_TRK_OPMODE_SPEC() {
208     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_SPEC,0);
209     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_SPEC,1);
210     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_SPEC,2);
211     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_SPEC,3);
212     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_SPEC,4);
213     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_SPEC,5);
214     }
215    
216     status_code TRK_Get_TRK_OPMODE_SPEC(BYTE i,DAQ_CMD_BUF **p) {
217     *p= & (TRK_OPMODE_SPEC[i]);
218     }
219    
220     static void TRK_Init_TRK_OPMODE_COMP() {
221     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_COMP,0);
222     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_COMP,1);
223     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_COMP,2);
224     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_COMP,3);
225     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_COMP,4);
226     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_OPMODE_COMP,5);
227     }
228    
229     static void TRK_Init_TRK_PROGRAM() {
230     DAQ_INIT_BUF_FROM_PARAMBUF(TRK_PROGRAM);
231     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_TRAILER_PRG,0);
232     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_TRAILER_PRG,1);
233     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_TRAILER_PRG,2);
234     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_TRAILER_PRG,3);
235     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_TRAILER_PRG,4);
236     DAQ_INIT_BUF_FROM_PARAMBUF_AS_ARR(TRK_TRAILER_PRG,5);
237     }
238    
239    
240     status_code TRK_Get_TRK_OPMODE_COMP(BYTE i,DAQ_CMD_BUF **p) {
241     *p= & (TRK_OPMODE_COMP[i]);
242     }
243    
244     void TRK_Init_ParamBuffers() {
245     TRK_Init_TRK_PROGRAM();
246     TRK_Init_TRK_NUMBER_DSP();
247     TRK_Init_TRK_OPMODE_COMP();
248     TRK_Init_TRK_OPMODE_SPEC();
249     }
250    
251    
252     status_code TRK_Init_ETOATO()
253     {
254     int i;
255    
256     for(i=0; i < 6; i++)
257     CH_SetAtoEto(TRK_RESET_DSP_BASE_ID+i,2,3);
258    
259     for(i=0; i < 15; i++)
260     CH_SetAtoEto(TRK_PROG_ADR_BASE_ID+i,2,3);
261    
262     for(i=0; i < 6; i++)
263     CH_SetAtoEto(TRK_LOAD_DATA_BASE_ID+i,0,8);
264    
265     for(i=0; i < 6; i++)
266     CH_SetAtoEto(TRK_HEADER_PRG_BASE_ID+i,0,8);
267    
268    
269     for(i=0; i < 6; i++)
270     {
271     CH_PARAMBUF_SET_ATO_ETO(TRK_NUMBER_DSP[1][i],2,3);
272     CH_PARAMBUF_SET_ATO_ETO(TRK_NUMBER_DSP[2][i],2,3);
273     CH_PARAMBUF_SET_ATO_ETO(TRK_OPMODE_COMP[i],2,3);
274     CH_PARAMBUF_SET_ATO_ETO(TRK_OPMODE_SPEC[i],2,3);
275     CH_PARAMBUF_SET_ATO_ETO(TRK_TRAILER_PRG[i],0,8);
276     }
277    
278     for(i=0; i < 6; i++)
279     {
280     CH_SetAtoEto(TRK_WRITE_DMTEST_DSP_BASE_ID+i,2,3);
281     CH_SetAtoEto(TRK_WRITE_PMTEST_DSP_BASE_ID+i,2,3);
282     CH_SetAtoEto(TRK_READ_DMTEST_DSP_BASE_ID+i,2,3);
283     CH_SetAtoEto(TRK_READ_PMTEST_DSP_BASE_ID+i,2,3);
284     CH_SetAtoEto(TRK_WRITE_PROGTEST_DSP_BASE_ID+i,0,0);
285     }
286    
287     for(i=0; i < 126; i++)
288     CH_SetAtoEto(TRK_CALIB_ADR_BASE_ID+i,2,3);
289    
290     CH_SetAtoEto(CH_TRK_TESTWORD_ADR,2,3);
291    
292     for(i=0; i < 6; i++)
293     {
294     CH_SetAtoEto(TRK_SET_CALIB_NORMAL_BASE_ID+i,2,3);
295     CH_SetAtoEto(TRK_SET_CALIB_SPECIAL_BASE_ID+i,2,3);
296     CH_SetAtoEto(TRK_EVENT_ACQ_BASE_ID+i,2,9);
297     CH_SetAtoEto(TRK_READ_INPUT_BASE_ID+i,2,8);
298     CH_SetAtoEto(TRK_READ_HEADER_BASE_ID+i,2,4);
299     }
300    
301     for(i=0; i < 192; i++)
302     CH_SetAtoEto(TRK_MASK_BASE_ID+i,2,3);
303    
304     CH_SetAtoEto(CH_TRK_GENERAL_RESET,2,3);
305     CH_SetAtoEto(CH_TRK_FLASH_ON,5,6);
306     CH_SetAtoEto(CH_TRK_FLASH_OFF,2,3);
307     CH_SetAtoEto(CH_TRK_RESET_FLASH,2,3);
308    
309     for(i=0; i < 6; i++)
310     {
311     CH_SetAtoEto(TRK_START_BASE_ID+i,2,3);
312     CH_SetAtoEto(TRK_READ_LADDER1_BASE_ID+i,2,8);
313     CH_SetAtoEto(TRK_READ_LADDER2_BASE_ID+i,2,8);
314     CH_SetAtoEto(TRK_READ_LADDER3_BASE_ID+i,2,8);
315     }
316    
317     CH_SetAtoEto(CH_TRK_READ_CR,2,3);
318     CH_SetAtoEto(CH_TB_GIVE_ME_TRIGGER,0,1);
319     }
320    
321     status_code TRK_Get_CalibUsed(UINT32 *calib_used)
322     {
323     *calib_used = TRK_calib_used;
324     }
325    
326     status_code TRK_Init()
327     {
328     DAQ_BUFFER_INIT(TRK_TempPif0);
329     DAQ_BUFFER_INIT(TRK_TempPif1);
330     DAQ_BUFFER_INIT(TRK_TempPif2);
331     DAQ_BUFFER_INIT(TRK_TempPif3);
332     DAQ_BUFFER_INIT(TRK_daq_reply0);
333     DAQ_BUFFER_INIT(TRK_daq_reply1);
334     DAQ_BUFFER_INIT(TRK_tempbuf);
335     memset(TRK_ALARM_MASK,0,sizeof(TRK_ALARM_MASK));
336     TRK_Init_ParamBuffers();
337     TRK_Init_ETOATO();
338    
339     return CM_RC_SUCCESSFUL;
340     }
341    
342     status_code TRK_InitTracker()
343     {
344     return CM_RC_SUCCESSFUL;
345     }
346    
347     status_code TRK_CheckPacket(DAQ_CMD_BUF *buf,DAQ_FE idaqfe)
348     {
349     status_code status;
350     BYTE *take,tmp;
351     UINT32 buflen;
352     UINT16 temp_get,EVENT_CAL,FLAG;
353     UINT16 PED_L[4],SIG_L[4],BAD_L[4];
354     UINT16 cond,i,j;
355    
356     #define TRK_DSP_CALIBPKT_SIZE (6364*2)
357     #define TRK_DSPCALIBPKT_REMAIN (6352*2)
358    
359     take = buf->buf;
360     buflen = buf->len;
361    
362     status = CM_RC_INVALID_BUFFER_SIZE;
363    
364     if(buflen < TRK_SKIP_HEADER)
365     LU_EXIT_IFERROR(status);
366    
367     take+=TRK_SKIP_HEADER;
368     buflen-=TRK_SKIP_HEADER;
369    
370     for(j=0; j < 6; j++)
371     {
372     if (PRH_TAB_TRK_DSP_OK[idaqfe][j])
373     {
374     if(buflen < TRK_DSP_CALIBPKT_SIZE)
375     LU_EXIT_IFERROR(status);
376    
377     buflen -= TRK_DSP_CALIBPKT_SIZE;
378     take+=6;
379     CM_READ_BE_UINT16(take,temp_get,tmp);
380     EVENT_CAL = (temp_get & 0x01FF) << 1;
381     CM_READ_BE_UINT16(take,temp_get,tmp);
382     EVENT_CAL |= (temp_get & 0x8000) >> 15;
383     PED_L[1] = (temp_get & 0x0FFC)>>2;
384     CM_READ_BE_UINT16(take,temp_get,tmp);
385     PED_L[2] = (temp_get & 0x7FE0)>>5;
386     PED_L[3] = (temp_get & 3) << 8;
387     CM_READ_BE_UINT16(take,temp_get,tmp);
388     PED_L[3] |=(temp_get & 0xFF00) >> 8;
389    
390     SIG_L[1] = (temp_get & 0x001F) << 5;
391     CM_READ_BE_UINT16(take,temp_get,tmp);
392     SIG_L[1] |= (temp_get & 0xF800) >> 11;
393     SIG_L[2] = (temp_get & 0x00FF) << 2;
394     CM_READ_BE_UINT16(take,temp_get,tmp);
395     SIG_L[2] |= (temp_get & 0xC000) >> 14;
396     SIG_L[3] = (temp_get & 0x07FE) >> 1;
397     CM_READ_BE_UINT16(take,temp_get,tmp);
398     BAD_L[1] = (temp_get & 0x3FF0) >> 4;
399     BAD_L[2] = (temp_get & 0x0001) << 9;
400     CM_READ_BE_UINT16(take,temp_get,tmp);
401     BAD_L[2] |= (temp_get & 0xFF80) >> 7;
402     BAD_L[3] = (temp_get & 0x000F) << 6;
403     CM_READ_BE_UINT16(take,temp_get,tmp);
404     BAD_L[3] |= (temp_get & 0xFC00) >> 10;
405     FLAG = (temp_get & 0060) >> 5;
406    
407     take+=TRK_DSPCALIBPKT_REMAIN;
408     cond = 1;
409    
410     if (!EVENT_CAL && !FLAG)
411     {
412     if (idaqfe == DAQ_FE_TRK_1)
413     {
414     for (i=1; i < 4; i++)
415     cond = cond && (PED_L[i] > (PRH_TAB_TRK_PED_MIN_0[i-1][j] / 4 ));
416    
417     for (i=1; i < 4; i++)
418     cond = cond && (PED_L[i] < (PRH_TAB_TRK_PED_MAX_0[i-1][j] / 4 ));
419    
420     for (i=1; i < 4; i++)
421     cond = cond && (SIG_L[i] > (PRH_TAB_TRK_SIG_MIN_0[i-1][j] ));
422    
423     for (i=1; i < 4; i++)
424     cond = cond && (SIG_L[i] < (PRH_TAB_TRK_SIG_MAX_0[i-1][j] ));
425    
426     for (i=1; i < 4; i++)
427     cond = cond && (BAD_L[i] < (PRH_TAB_TRK_BAD_MAX_0[i-1][j] ));
428     }
429     else
430     {
431     for (i=1; i < 4; i++)
432     cond = cond && (PED_L[i] > (PRH_TAB_TRK_PED_MIN_1[i-1][j] / 4 ));
433    
434     for (i=1; i < 4; i++)
435     cond = cond && (PED_L[i] < (PRH_TAB_TRK_PED_MAX_1[i-1][j] / 4 ));
436    
437     for (i=1; i < 4; i++)
438     cond = cond && (SIG_L[i] > (PRH_TAB_TRK_SIG_MIN_1[i-1][j] ));
439    
440     for (i=1; i < 4; i++)
441     cond = cond && (SIG_L[i] < (PRH_TAB_TRK_SIG_MAX_1[i-1][j] ));
442    
443     for (i=1; i < 4; i++)
444     cond = cond && (BAD_L[i] < (PRH_TAB_TRK_BAD_MAX_1[i-1][j] ));
445     }
446     if (cond==0)
447     break;
448     }
449     else
450     {
451     cond=0;
452     /*@LOG TRK_CheckPacket: cond set to zero. - FLAG */
453     LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,FLAG);
454     /*@LOG TRK_CheckPacket: cond set to zero. - EVENT_CAL */
455     LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,EVENT_CAL);
456     break;
457     }
458     }
459     }
460     /*@LOG TRK_CheckPacket end - cond */
461     LU_INFN_LOG(LU_DEBUG_TRACE,LU_MASK(__FILEID__),__FILEID__,__LINE__,cond);
462     return ((cond == 1) ? CM_RC_SUCCESSFUL : CM_RC_UNSATISFIED);
463     }
464    
465     status_code TRK_Initialization()
466     {
467     status_code status=CM_RC_SUCCESSFUL;
468     int trk_loop_ini;
469     int j,i,k,x;
470     DAQ_FE idaqfe;
471     UINT16 alarm_reg;
472     DAQ_CMD_BUF* auto_buf;
473    
474     TRK_status = 1;
475     trk_loop_ini = 1;
476    
477     DAQ_Format_CMD_Empty(&TRK_TempPif0);
478    
479     status = DAQ_ResetPIF(DAQ_DEFAULT_ETO_TICS,DAQ_MAX_DTO_TICS,SM_DAQSETUP,HB_PKTTYPE_TRK_INIT);
480    
481     for( i=0,idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
482     {
483     TRK_ALARM_MASK[i] = 0; j = 0;
484    
485     while (j < 6)
486     {
487     if (!PRH_TAB_TRK_DSP_OK[i][j])
488     TRK_ALARM_MASK[i] |= (1 << j);
489     if (PRH_TAB_TRK_DSP_MASK[i][j])
490     TRK_ALARM_MASK[i] |= (1 << j);
491    
492     j++;
493     }
494    
495     TRK_ALARM_MASK[i] |= 0xc0;
496    
497     CH_GetBuf(TRK_MASK_BASE_ID+TRK_ALARM_MASK[i]-TRK_MASK_BASE_OFFSET,&auto_buf );
498     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
499     CH_GetBuf(CH_TRK_GENERAL_RESET,&auto_buf);
500     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
501     }
502    
503     status = DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
504     LU_EXIT_IFERROR(status);
505     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
506     LU_EXIT_IFERROR(status);
507    
508     for(i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
509     {
510     DAQ_Format_CMD_Empty(&TRK_TempPif0);
511     x = PRH_ARR_TRK_LOAD_PRG[i];
512    
513     if (x)
514     {
515     CH_GetBuf(CH_TRK_FLASH_ON,&auto_buf );
516     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
517     status = DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
518     LU_EXIT_IFERROR(status);
519     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
520     LU_EXIT_IFERROR(status);
521     status = RM_TaskSuspendUnlessSINT(100);
522     LU_EXIT_IFERROR(status);
523    
524     DAQ_Format_CMD_Empty(&TRK_TempPif0);
525     CH_GetBuf(CH_TRK_RESET_FLASH,&auto_buf );
526     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
527    
528     for (j=0; j < 6; j++)
529     {
530     if (PRH_TAB_TRK_DSP_OK[i][j])
531     {
532     CH_GetBuf(TRK_PROG_ADR_BASE_ID+x-1,&auto_buf);
533     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
534     {
535     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
536     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
537     LU_EXIT_IFERROR(status);
538     DAQ_Format_CMD_Empty(&TRK_TempPif0);
539     }
540     CH_GetBuf(TRK_LOAD_DATA_BASE_ID+j,&auto_buf);
541     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
542     }
543     }
544    
545     CH_GetBuf(CH_TRK_FLASH_OFF,&auto_buf );
546     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
547    
548     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
549     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
550     LU_EXIT_IFERROR(status);
551     }
552     else
553     {
554     for (j=0; j < 6; j++)
555     {
556     if (PRH_TAB_TRK_DSP_OK[i][j])
557     {
558     DAQ_Format_CMD_Empty(&TRK_TempPif0);
559     DAQ_Format_CMD_Empty(&TRK_TempPif1);
560     CH_GetBuf(TRK_HEADER_PRG_BASE_ID+j,&auto_buf);
561     DAQ_Format_AppendBuffer(&TRK_TempPif1,auto_buf);
562    
563     DAQ_Format_AppendBuffer(&TRK_TempPif1,&TRK_PROGRAM);
564    
565     DAQ_Format_AppendBuffer(&TRK_TempPif1,&TRK_TRAILER_PRG[j]);
566     TRK_TempPif1.ato = TRK_TRAILER_PRG[j].ato;
567     TRK_TempPif1.eto = TRK_TRAILER_PRG[j].eto;
568     DAQ_Format_Fe2Daq(&TRK_TempPif0,&TRK_TempPif1,idaqfe);
569    
570     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
571     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
572     LU_EXIT_IFERROR(status);
573     }
574     }
575     }
576     }
577    
578     DAQ_Format_CMD_Empty(&TRK_TempPif0);
579    
580     for( i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
581     {
582     for(j=0; j < 6; j++)
583     {
584     CH_GetBuf(TRK_START_BASE_ID+j,&auto_buf );
585    
586     if (PRH_TAB_TRK_DSP_OK[i][j])
587     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
588     }
589     }
590    
591     for( i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
592     {
593     for(j=0; j < 6; j++)
594     {
595     if (PRH_TAB_TRK_DSP_OK[i][j])
596     DAQ_Format_Fe2Daq(&TRK_TempPif0,&TRK_NUMBER_DSP[i+1][j],idaqfe);
597     }
598     }
599    
600     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
601     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
602     LU_EXIT_IFERROR(status);
603    
604     if (!RM_Init_Before_Calib)
605     {
606     DAQ_Format_CMD_Empty(&TRK_TempPif0);
607    
608     CH_GetBuf(CH_TRK_FLASH_ON,&auto_buf );
609     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,DAQ_FE_TRK_1);
610    
611     CH_GetBuf(CH_TRK_FLASH_ON,&auto_buf );
612     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,DAQ_FE_TRK_2);
613    
614     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
615     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
616     LU_EXIT_IFERROR(status);
617     status = RM_TaskSuspendUnlessSINT(100);
618     LU_EXIT_IFERROR(status);
619    
620     DAQ_Format_CMD_Empty(&TRK_TempPif0);
621    
622     for(i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
623     {
624     CH_GetBuf(CH_TRK_RESET_FLASH,&auto_buf );
625     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
626    
627     for(k=0; k < 3; k++)
628     for(j=0; j < 6; j++)
629     {
630     if (PRH_TAB_TRK_DSP_OK[i][j])
631     {
632     CH_GetBuf(TRK_CALIB_ADR_BASE_ID+j*21+k*7+(PRH_VAR_TRK_CALIB_INIT-TRK_CALIB_ADR_BASE_OFFSET),&auto_buf );
633     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
634     {
635     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
636     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
637     LU_EXIT_IFERROR(status);
638     DAQ_Format_CMD_Empty(&TRK_TempPif0);
639     }
640     CH_GetBuf(TRK_LOAD_DATA_BASE_ID+j,&auto_buf );
641     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
642     }
643     }
644    
645     CH_GetBuf(CH_TRK_FLASH_OFF,&auto_buf );
646     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
647     }
648    
649     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
650     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
651     LU_EXIT_IFERROR(status);
652     TRK_calib_used = PRH_VAR_TRK_CALIB_INIT;
653     }
654    
655     TRK_status = 0;
656    
657     return status;
658     }
659    
660     status_code TRK_Assemble_ReadCalibrationCmd(DAQ_CMD_BUF* board1,DAQ_CMD_BUF* board2)
661     {
662     int j;
663     DAQ_CMD_BUF* auto_buf;
664    
665     DAQ_Format_CMD_Empty(board1);
666     DAQ_Format_CMD_Empty(board2);
667    
668    
669     for(j=0; j < 6 ; j++)
670     {
671     if (PRH_TAB_TRK_DSP_OK[0][j])
672     {
673     CH_GetBuf(TRK_READ_HEADER_BASE_ID+j,&auto_buf );
674     DAQ_Format_Fe2Daq(board1,auto_buf,DAQ_FE_TRK_1);
675    
676     CH_GetBuf(TRK_READ_LADDER1_BASE_ID+j,&auto_buf );
677     DAQ_Format_Fe2Daq(board1,auto_buf,DAQ_FE_TRK_1);
678    
679     CH_GetBuf(TRK_READ_LADDER2_BASE_ID+j,&auto_buf );
680     DAQ_Format_Fe2Daq(board1,auto_buf,DAQ_FE_TRK_1);
681    
682     CH_GetBuf(TRK_READ_LADDER3_BASE_ID+j,&auto_buf );
683     DAQ_Format_Fe2Daq(board1,auto_buf,DAQ_FE_TRK_1);
684     }
685    
686     if (PRH_TAB_TRK_DSP_OK[1][j])
687     {
688     CH_GetBuf(TRK_READ_HEADER_BASE_ID+j,&auto_buf );
689     DAQ_Format_Fe2Daq(board2,auto_buf,DAQ_FE_TRK_2);
690    
691     CH_GetBuf(TRK_READ_LADDER1_BASE_ID+j,&auto_buf );
692     DAQ_Format_Fe2Daq(board2,auto_buf,DAQ_FE_TRK_2);
693    
694     CH_GetBuf(TRK_READ_LADDER2_BASE_ID+j,&auto_buf );
695     DAQ_Format_Fe2Daq(board2,auto_buf,DAQ_FE_TRK_2);
696    
697     CH_GetBuf(TRK_READ_LADDER3_BASE_ID+j,&auto_buf );
698     DAQ_Format_Fe2Daq(board2,auto_buf,DAQ_FE_TRK_2);
699     }
700     }
701    
702     return CM_RC_SUCCESSFUL;
703     }
704    
705     status_code TRK_Send_ReadCalibrationCmd(SM_PAGEID page1,SM_PAGEID page2,
706     DAQ_CMD_BUF* board1,DAQ_CMD_BUF* board2,
707     DAQ_CMD_BUF* ans1,DAQ_CMD_BUF* ans2)
708     {
709    
710     status_code status;
711     PM_pi_SetPktType(HB_PKTTYPE_CALIB_TRK_1);
712     DAQ_StoreCmdQueue2PIF(page1,board1);
713     status = DAQ_SendCmd2PIFWaitDAQReply(page1,TRUE,ans1,ans1==NULL ? DAQ_NO_STORE_RAM : DAQ_STORE_RAM);
714     LU_EXIT_IFERROR(status);
715    
716     PM_pi_SetPktType(HB_PKTTYPE_CALIB_TRK_2);
717     DAQ_StoreCmdQueue2PIF(page2,board2);
718     status = DAQ_SendCmd2PIFWaitDAQReply(page2,TRUE,ans2,ans2==NULL ? DAQ_NO_STORE_RAM : DAQ_STORE_RAM);
719     LU_EXIT_IFERROR(status);
720    
721     return CM_RC_SUCCESSFUL;
722     }
723    
724    
725     status_code TRK_Calibration(UINT32 trk_calib_mode)
726     {
727     status_code status=CM_RC_SUCCESSFUL,s1,s2;
728     UINT32 TRK_loop_calib,TRK_calib=trk_calib_mode;
729     int i,j,k,n;
730     DAQ_FE idaqfe;
731     DAQ_CMD_BUF* auto_buf;
732     UINT16 alarm_reg;
733     BOOL redo_calib;
734    
735     TRK_status = 2;
736     TRK_loop_calib=0;
737     // TRK_calib = PRH_VAR_TRK_CALIB_MODE;
738    
739    
740     DAQ_ResetPIF(DAQ_DEFAULT_ETO_TICS,DAQ_MAX_DTO_TICS,SM_DAQSETUP,HB_PKTTYPE_CALIB_TRK_BOTH);
741    
742     //TBD set pif 128K
743     //TBD set trigger in calib mode
744    
745     do {
746     redo_calib = FALSE;
747    
748     DAQ_Format_CMD_Empty(&TRK_TempPif0);
749     PM_pi_SetPktType(HB_PKTTYPE_CALIB_TRK_BOTH);
750    
751     for(i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
752     {
753     CH_GetBuf(CH_TRK_GENERAL_RESET,&auto_buf );
754     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
755    
756     for(j=0; j <6; j++)
757     {
758     if (PRH_TAB_TRK_DSP_OK[i][j])
759     {
760     CH_GetBuf(TRK_START_BASE_ID+j,&auto_buf );
761     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
762     DAQ_Format_Fe2Daq(&TRK_TempPif0,&TRK_NUMBER_DSP[i+1][j],idaqfe);
763     }
764     }
765     }
766    
767     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
768    
769     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
770     LU_EXIT_IFERROR(status);
771     TRK_calib_used = TRK_calib;
772    
773     if (TRK_calib > 100)
774     {
775     DAQ_Format_CMD_Empty(&TRK_TempPif0);
776    
777     for(i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
778     {
779    
780     CH_GetBuf(CH_TRK_READ_CR,&auto_buf);
781     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
782    
783     TRK_ALARM_MASK[i]|=0xc0;
784     CH_GetBuf(TRK_MASK_BASE_ID+TRK_ALARM_MASK[i]-TRK_MASK_BASE_OFFSET,&auto_buf );
785    
786     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
787     CH_GetBuf(CH_TRK_FLASH_ON,&auto_buf );
788     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
789     }
790    
791     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
792    
793     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
794     LU_EXIT_IFERROR(status);
795    
796     status = RM_TaskSuspendUnlessSINT(100);
797     LU_EXIT_IFERROR(status);
798    
799     DAQ_Format_CMD_Empty(&TRK_TempPif0);
800    
801     for(i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
802     {
803     CH_GetBuf(CH_TRK_RESET_FLASH,&auto_buf );
804     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
805    
806     for(k=0; k < 3; k++)
807     for(j=0; j < 6; j++)
808     {
809     if (PRH_TAB_TRK_DSP_OK[i][j])
810     {
811     CH_GetBuf(TRK_CALIB_ADR_BASE_ID+j*21+k*7+(PRH_VAR_TRK_CALIB_INIT-TRK_CALIB_ADR_BASE_OFFSET),&auto_buf );
812     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
813     {
814     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
815     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
816     LU_EXIT_IFERROR(status);
817     DAQ_Format_CMD_Empty(&TRK_TempPif0);
818     }
819     CH_GetBuf(TRK_LOAD_DATA_BASE_ID+j,&auto_buf );
820     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
821     }
822     }
823    
824     CH_GetBuf(CH_TRK_FLASH_OFF,&auto_buf );
825     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
826     }
827    
828     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
829     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
830     LU_EXIT_IFERROR(status);
831    
832     /*
833     status=TRK_Assemble_ReadCalibrationCmd(&TRK_TempPif2,&TRK_TempPif3);
834     LU_EXIT_IFERROR(status);
835     status=TRK_Send_ReadCalibrationCmd(SM_CALEXP2,SM_CALEXP3,
836     &TRK_TempPif2,&TRK_TempPif3,
837     NULL,NULL);
838     LU_EXIT_IFERROR(status);
839     */
840     }
841     else
842     {
843     DAQ_Format_CMD_Empty(&TRK_TempPif0);
844     DAQ_Format_CMD_Empty(&TRK_TempPif1);
845     DAQ_Format_CMD_Empty(&TRK_TempPif2);
846     DAQ_Format_CMD_Empty(&TRK_TempPif3);
847    
848     for(i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
849     {
850     TRK_ALARM_MASK[i]|=0xc0;
851     if(PRH_VAR_TB_LINK == 1 /* HOT */)
852     TRK_ALARM_MASK[i] &= 0xBF;
853     else
854     TRK_ALARM_MASK[i] &= 0x7F;
855    
856     CH_GetBuf(TRK_MASK_BASE_ID-TRK_MASK_BASE_OFFSET+TRK_ALARM_MASK[i],&auto_buf );
857     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
858    
859     for(j=0; j < 6 ; j++)
860     {
861     if (PRH_TAB_TRK_DSP_OK[i][j])
862     if (TRK_calib == 1)
863     {
864     CH_GetBuf(TRK_SET_CALIB_NORMAL_BASE_ID+j,&auto_buf );
865     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
866     }
867     else
868     if (TRK_calib == 2)
869     {
870     CH_GetBuf(TRK_SET_CALIB_SPECIAL_BASE_ID+j,&auto_buf );
871     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
872     CH_GetBuf(TRK_EVENT_ACQ_BASE_ID+j,&auto_buf );
873     DAQ_Format_Fe2Daq(&TRK_TempPif1,auto_buf,idaqfe);
874     status = DAQ_StoreCmdQueue2PIF(SM_CALEXP1,&TRK_TempPif1);
875     LU_EXIT_IFERROR(status);
876     }
877     }
878     }
879    
880     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
881     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
882     LU_EXIT_IFERROR(status);
883    
884     DAQ_Format_CMD_Empty(&TRK_TempPif0);
885     CH_GetBuf(CH_TB_GIVE_ME_TRIGGER,&auto_buf );
886     DAQ_Format_Cmd2Fe(&TRK_TempPif0,auto_buf,DAQ_SELECT_TRIG(PRH_VAR_TB_LINK));
887     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
888     if (TRK_calib == 2)
889     {
890     PM_pi_SetPktType(HB_PKTTYPE_EVENT_TRK);
891    
892     for(k=0; k < PRH_VAR_TRK_NLOOP; k++)
893     {
894     for(n=0; n < 128; n++)
895     {
896     status = DAQ_SendCmdQueue2CMDIF(SM_CALEXP0);
897     LU_EXIT_IFERROR(status);
898     status = RM_TaskSuspendUnlessSINT(PRH_VAR_TRK_TIME_SHORT);
899     LU_EXIT_IFERROR(status);
900    
901     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP1,DAQ_STORE_MM,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
902     LU_EXIT_IFERROR(status);
903     }
904     status = RM_TaskSuspendUnlessSINT(PRH_VAR_TRK_TIME_LONG);
905     LU_EXIT_IFERROR(status);
906    
907     }
908     }
909     else
910     if (TRK_calib == 1)
911     {
912     for(k=0; k < PRH_VAR_TRK_NLOOP; k++)
913     {
914     for(n=0; n < 128; n++)
915     {
916     status = DAQ_SendCmdQueue2CMDIF(SM_CALEXP0);
917     LU_EXIT_IFERROR(status);
918     status = RM_TaskSuspendUnlessSINT(PRH_VAR_TRK_TIME_SHORT);
919     LU_EXIT_IFERROR(status);
920     }
921     status = RM_TaskSuspendUnlessSINT(PRH_VAR_TRK_TIME_LONG);
922     LU_EXIT_IFERROR(status);
923    
924     }
925     }
926    
927     PM_pi_SetExpPktCpyFlag(TRUE);
928    
929     status=TRK_Assemble_ReadCalibrationCmd(&TRK_TempPif2,&TRK_TempPif3);
930     LU_EXIT_IFERROR(status);
931    
932     status=TRK_Send_ReadCalibrationCmd(SM_CALEXP2,SM_CALEXP3,
933     &TRK_TempPif2,&TRK_TempPif3,
934     &TRK_daq_reply0,&TRK_daq_reply1);
935     LU_EXIT_IFERROR(status);
936    
937    
938     PM_pi_SetExpPktCpyFlag(FALSE);
939    
940     if (TRK_calib == 2)
941     {
942     #warning To set in EEPROM TRK_CALIB_MODE
943     PRH_VAR_TRK_CALIB_MODE=TRK_calib = 1;
944     }
945     s1 = TRK_CheckPacket(&TRK_daq_reply0,DAQ_FE_TRK_1);
946    
947     s2 = TRK_CheckPacket(&TRK_daq_reply1,DAQ_FE_TRK_2);
948    
949     if (s1 != CM_RC_SUCCESSFUL || s2 != CM_RC_SUCCESSFUL ) // everything is ok
950     {
951     if (TRK_loop_calib >=3)
952     TRK_calib = PRH_VAR_TRK_CALIB_INIT;
953     TRK_loop_calib++;
954     redo_calib = TRUE;
955     }
956     }
957     }while(redo_calib);
958    
959     TRK_status = 0;
960    
961     return status;
962     }
963    
964     #if 0
965     status_code TRK_Alarm()
966     {
967     int alarm_link=0,j,i;
968     DAQ_FE idaqfe;
969     status_code status;
970     DAQ_CMD_BUF* auto_buf;
971    
972     // TDB read KHB alarm register
973     DAQ_Format_CMD_Empty(&TRK_TempPif0);
974    
975     CH_GetBuf(CH_TRK_READ_CR,&auto_buf );
976     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,DAQ_FE_TRK_1+alarm_link);
977    
978     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
979     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
980     LU_EXIT_IFERROR(status);
981    
982     // TBD write in HK reply
983    
984     DAQ_Format_CMD_Empty(&TRK_TempPif0);
985     CH_GetBuf(CH_TRK_GENERAL_RESET,&auto_buf );
986     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,DAQ_FE_TRK_1+alarm_link);
987    
988     CH_GetBuf(CH_TRK_READ_CR,&auto_buf );
989    
990     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,DAQ_FE_TRK_1+alarm_link);
991     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
992     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
993     LU_EXIT_IFERROR(status);
994    
995     // TBD unmasked alarm ?
996    
997     switch(TRK_status)
998     {
999     case 1:
1000     break;
1001     case 2:
1002     break;
1003     default:
1004     //TDB if (DS)
1005     if (1)
1006     {
1007     DAQ_Format_CMD_Empty(&TRK_TempPif0);
1008     for(i=0, idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2; idaqfe++,i++)
1009     {
1010     for(j=0; j < 6 ; j++)
1011     {
1012     CH_GetBuf(TRK_READ_HEADER_BASE_ID+j,&auto_buf );
1013    
1014     if (PRH_TAB_TRK_DSP_OK[i][j])
1015     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
1016     }
1017     }
1018    
1019     DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
1020     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,FALSE,&TRK_daq_reply0,DAQ_NO_STORE_RAM);
1021     LU_EXIT_IFERROR(status);
1022    
1023     }
1024     else
1025     {
1026     TRK_status = 0;
1027     TRK_Reset();
1028     }
1029     }
1030    
1031    
1032     return CM_RC_SUCCESSFUL;
1033     }
1034     #endif
1035    
1036     status_code TRK_Error_Handler()
1037     {
1038     status_code status=CM_RC_SUCCESSFUL;
1039     DAQ_FE idaqfe;
1040     DAQ_CMD_BUF* auto_buf,*daq_reply;
1041     BYTE do_check;
1042     UINT16 status_reg;
1043    
1044    
1045     do_check = 0;
1046    
1047     for(idaqfe = DAQ_FE_TRK_1; idaqfe <= DAQ_FE_TRK_2 ; idaqfe++)
1048     {
1049    
1050     CH_GetBuf(CH_TRK_READ_CR,&auto_buf);
1051     DAQ_Format_CMD_Empty(&TRK_TempPif0);
1052    
1053     DAQ_Format_Fe2Daq(&TRK_TempPif0,auto_buf,idaqfe);
1054    
1055     status = DAQ_StoreCmdQueue2PIF(SM_CALEXP0,&TRK_TempPif0);
1056     if (status)
1057     {
1058     status = CM_RC_DO_RESET_IF_ALM;
1059     return(status);
1060     }
1061    
1062     daq_reply = idaqfe==DAQ_FE_TRK_1 ? &TRK_daq_reply0 : &TRK_daq_reply1;
1063     status = DAQ_SendCmd2PIFWaitDAQReply(SM_CALEXP0,DAQ_STORE_MM,
1064     daq_reply ,
1065     DAQ_STORE_RAM);
1066    
1067     if (status || (daq_reply->len != SM_PKTHEADER_LEN+11 /* must be 27*/))
1068     {
1069     status = CM_RC_DO_RESET_IF_ALM;
1070     return(status);
1071     }
1072    
1073     // some check here
1074    
1075     do_check |=
1076     (daq_reply->buf[SM_PKTHEADER_LEN+1] & (1<<7)) |
1077     daq_reply->buf[SM_PKTHEADER_LEN+2] |
1078     daq_reply->buf[SM_PKTHEADER_LEN+3] |
1079     daq_reply->buf[SM_PKTHEADER_LEN+4] ;
1080    
1081     }
1082    
1083     if (do_check)
1084     {
1085     status = HK_ReadKHBStatusRegister(&status_reg);
1086     if (status)
1087     {
1088     status = CM_RC_DO_RESET_IF_ALM;
1089     return(status);
1090     }
1091    
1092     status_reg&=(KHB_STS_ALARM_IDAQ | KHB_STS_ALARM_TRK);
1093    
1094     if (status_reg == 0)
1095     {
1096    
1097     if (PRH_VAR_GOM_DURING_ALARM == MH_GOM_INITIALIZATION)
1098     status = CM_RC_DO_RESET_IF_ALM;
1099     else
1100     if (PRH_VAR_GOM_DURING_ALARM == MH_GOM_CALIBRATION)
1101     {
1102     if (PRH_VAR_TRK_CALIB_MODE > 100)
1103     status = CM_RC_DO_RESET_IF_ALM;
1104     else
1105     {
1106     // PRH_VAR_TRK_CALIB = PRH_VAR_TRK_CALIB_INIT;
1107     // TRK_Calib = PRH_VAR_TRK_CALIB_INIT;
1108     status = TRK_Calibration(PRH_VAR_TRK_CALIB_INIT);
1109     if (status)
1110     status = CM_RC_DO_RESET_IF_ALM;
1111     else
1112     {
1113     status = HK_ReadKHBStatusRegister(&status_reg);
1114     status_reg&=(KHB_STS_ALARM_IDAQ | KHB_STS_ALARM_TRK | KHB_STS_ALARM_TRG) & PRH_VAR_MASK_ACQ_ALARM;
1115    
1116     if (status || status_reg)
1117     status = CM_RC_DO_RESET_IF_ALM;
1118     }
1119     }
1120     }
1121     else
1122     if (PRH_VAR_GOM_DURING_ALARM == MH_GOM_ACQUISITION)
1123     {
1124     if(
1125     (TRK_daq_reply0.buf[SM_PKTHEADER_LEN+2] & 0x3F) |
1126     (TRK_daq_reply1.buf[SM_PKTHEADER_LEN+2] & 0x3F) )
1127     status = CM_RC_DO_POWER_OFF_ON;
1128     else
1129     status = CM_RC_DO_RESET_IF_ALM;
1130     }
1131     }
1132     else
1133     status = CM_RC_DO_RESET_IF_ALM;
1134     }
1135    
1136     return status;
1137     }
1138    
1139     status_code TRK_ChkSensors(UINT16 command1,UINT16 command2,UINT16 expected,ALM_VAR_ID log_id,UINT16 pkttype_id)
1140     {
1141     UINT16 combuf;
1142     UINT16 outbuf[TRK_TSB_MAX_REPLY];
1143     int i;
1144     BYTE board;
1145     status_code status=CM_RC_SUCCESSFUL,offst;
1146    
1147     if((PRH_ARR_TSB_BOARD_OK[0] | PRH_ARR_TSB_BOARD_OK[1]) == 0)
1148     return CM_RC_SUCCESSFUL;
1149    
1150     #if 0
1151     status = PWR_CMD2PSB(PRH_ARR_PSB_COMMANDS[PWR_PSB_TRACKER_SENSOR_ON],TM_PSB_ALARM,CM_OFF,
1152     log_id,log_id+1,PWR_PSB_STANDARD_ANSWER);
1153     #endif
1154    
1155     for(board=0;board<2;board++)
1156     {
1157     if(PRH_ARR_TSB_BOARD_OK[board]) {
1158     combuf = board==0 ? command1 : command2;
1159     status = HK_KHB_Cmd2FE(board==0 ? KHB_TRACKER_SENSORS_1 : KHB_TRACKER_SENSORS_2 ,
1160     1,expected,&combuf,outbuf,TRK_TSB_TIMEOUT);
1161    
1162     DAQ_BUFFER_EMPTY(TRK_tempbuf);
1163     DAQ_WRITE_BE_UINT8(TRK_tempbuf,status);
1164     switch(status)
1165     {
1166     case CM_RC_KHB_ERROR:
1167     /*@LOG TRK_ChkSensors: TSB0 , KHB Error */
1168     ALM_WriteLog(ALM_TRACE_ID,log_id+2);
1169     status = CM_RC_SUCCESSFUL;
1170     break;
1171     case CM_RC_TIMEOUT:
1172     /*@LOG TRK_ChkSensors: TSB0 , reading Timeout */
1173     ALM_WriteLog(ALM_TRACE_ID,log_id+3);
1174     for(i=0; i < expected; i++)
1175     if(i<outbuf[0])
1176     DAQ_WRITE_BE_UINT16(TRK_tempbuf,outbuf[i+1]);
1177     else
1178     DAQ_WRITE_BE_UINT16(TRK_tempbuf,0xFFFF);
1179     TRK_WriteInLog(pkttype_id,&TRK_tempbuf);
1180     status = CM_RC_SUCCESSFUL;
1181     break;
1182     case CM_RC_SUCCESSFUL:
1183     for(i=0; i < expected; i++)
1184     DAQ_WRITE_BE_UINT16(TRK_tempbuf,outbuf[i]);
1185     TRK_WriteInLog(pkttype_id,&TRK_tempbuf);
1186     break;
1187     default:
1188     /*@LOG TRK_ChkSensors: unrecognized error board 0 - status */
1189     LU_INFN_LOG(LU_CRITICAL|LU_HA,LU_MASK(__FILEID__),__FILEID__,__LINE__,status);
1190     }
1191     }
1192    
1193     }
1194    
1195     #if 0
1196     offst = PWR_CMD2PSB(PRH_ARR_PSB_COMMANDS[PWR_PSB_TRACKER_SENSOR_OFF],TM_PSB_ALARM,CM_OFF,
1197     log_id+6,log_id+7,PWR_PSB_STANDARD_ANSWER);
1198    
1199     if (offst) {
1200     /*@LOG TRK_ChkSensors: TSB OFF, error */
1201     ALM_WriteLog(ALM_TRACE_ID,log_id);
1202     status = CM_RC_DO_POWER_OFF_ON;
1203     }
1204     #endif
1205     return CM_RC_SUCCESSFUL;
1206     }
1207    
1208     status_code TRK_CheckBSensors()
1209     {
1210     return TRK_ChkSensors(TRK_TSB0_READ_B,TRK_TSB1_READ_B,7,ALM_TRK_TSB_ID_8,HB_PKTTYPE_TSB_B);
1211     }
1212    
1213     status_code TRK_CheckTSensors()
1214     {
1215     return(TRK_ChkSensors(TRK_TSB0_READ_T,TRK_TSB1_READ_T,13,ALM_TRK_TSB_ID_0,HB_PKTTYPE_TSB_T));
1216     }
1217    
1218     status_code TRK_WriteInLog(BYTE pkttype,DAQ_CMD_BUF *b)
1219     {
1220     status_code s;
1221     switch(pkttype) {
1222     case HB_PKTTYPE_TSB_T:
1223     s=HB_StoreTSB_T(b);
1224     break;
1225     case HB_PKTTYPE_TSB_B:
1226     s=HB_StoreTSB_B(b);
1227     break;
1228     default:
1229     /*@LOG pkttype error in TRK_WriteInLog - pkttype */
1230     LU_INFN_LOG(LU_INTERNAL|LU_HA,LU_MASK(__FILEID__),__FILEID__,__LINE__,pkttype);
1231     }
1232     return s;
1233     }
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