| 1 |
|
| 2 |
/* PRH_ParamHandler_INFN_auto.c file. |
| 3 |
This file has been automatically generated by gen_params.pl. |
| 4 |
Don't edit manually this file! |
| 5 |
*/ |
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|
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|
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#include <src/INFN/LU_SourceFileID_INFN.h> |
| 9 |
#define __FILEID__ _PRH_ParamHandler_INFN_auto__c |
| 10 |
#include <src/INFN/LU_LogUtility_INFN.h> |
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#include "PRH_ParamHandler_INFN_auto.h" |
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#include "PRH_ParamHandler_INFN_autopri.h" |
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|
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#ifndef I386 |
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LU_DECL_MASK(); |
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#else |
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#define _PRH_ParamHandler_INFN_auto__c 0 |
| 18 |
#endif |
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|
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// include here all the includes for initialization values |
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#include <src/INFN/GS_Gas_INFN.h> |
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#include <src/TM_TCManager/TMTCManager/TM_TMTCManager_p.h> |
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#include <src/INFN/PWR_PowerHandler_INFN.h> |
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|
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#ifndef I386 |
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#include <src/BasicSW/RTEMSInterface/OS_rtems_p.h> |
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#include <src/INFN/LU_LogUtility_INFN.h> |
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#include <src/INFN/DAQ_IDAQ_INFN.h> |
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#include <src/BasicSW/PatchDumpManager/PD_PatchDumpManager_int.h> |
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#endif // I386 |
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|
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#ifdef I386 |
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#include <string.h> |
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#include <stdio.h> |
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#endif // I386 |
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|
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|
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|
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|
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/* |
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* **************************************** BEGIN of declarations *************************** |
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*/ |
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|
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|
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/* |
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* --------- Log Level Parameters : ------------- |
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*/ |
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|
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|
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/* |
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* id : LOG_MASK |
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* type : <array>[113] |
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* log level mask for each module /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_ARR_LOG_MASK[113]={LU_DEFAULT_MASK}; |
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#else |
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PRH_VAR_TYPE PRH_ARR_LOG_MASK[113]; |
| 61 |
#endif |
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|
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|
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/* |
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* id : LU_WRITE_ON_UART |
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* type : <var> |
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* enable[1]/disable[0] the UART writing /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_LU_WRITE_ON_UART=1; |
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#else |
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PRH_VAR_TYPE PRH_VAR_LU_WRITE_ON_UART; |
| 75 |
#endif |
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|
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/* |
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* id : VERBOSE_DEBUG |
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* type : <var> |
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* Verbose Debug mode |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_VERBOSE_DEBUG=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_VERBOSE_DEBUG; |
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#endif |
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|
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/* |
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* id : DOWNLOAD_HEADER |
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* type : <var> |
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* download counter, to be written in Download header info /RW-E2P |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_DOWNLOAD_HEADER=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_DOWNLOAD_HEADER; |
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#endif |
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|
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/* |
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* KHB driver |
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*/ |
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|
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|
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/* |
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* id : KHB_ALARM_REG_LOW_LEVEL_MASK |
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* type : <var> |
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* mask of KHB Alarm register to be low-level masked /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_KHB_ALARM_REG_LOW_LEVEL_MASK=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_KHB_ALARM_REG_LOW_LEVEL_MASK; |
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#endif |
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|
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/* |
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* id : KHB_STATUS_REG_LOW_LEVEL_MASK |
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* type : <var> |
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* mask of KHB status register to be low-level masked /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_KHB_STATUS_REG_LOW_LEVEL_MASK=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_KHB_STATUS_REG_LOW_LEVEL_MASK; |
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#endif |
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|
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/* |
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* id : PULSER_ACTION |
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* type : <var> |
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* pulser action at startup; [0=none,1=Reset,2:0.25Hz,3:100Hz] /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_PULSER_ACTION=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_PULSER_ACTION; |
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#endif |
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|
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/* |
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* --------- General Parameters: ---------------------- |
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*/ |
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|
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|
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/* |
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* id : N_BOOT |
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* type : <var> |
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* Boot Counter /RW-E2P |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_N_BOOT=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_N_BOOT; |
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#endif |
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|
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/* |
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* id : THERMISTORS_CHECK |
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* type : <var> |
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* Check if thermistor are going to be checked /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_THERMISTORS_CHECK=1; |
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#else |
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PRH_VAR_TYPE PRH_VAR_THERMISTORS_CHECK; |
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#endif |
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|
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/* |
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* id : THERM_MASK |
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* type : <var> |
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* Thermistors mask /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_THERM_MASK=65535; |
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#else |
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PRH_VAR_TYPE PRH_VAR_THERM_MASK; |
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#endif |
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|
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/* |
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* id : THERM_LOW |
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* type : <array>[16] |
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* Thermistor low limit /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_ARR_THERM_LOW[16]={93,93,93,93,93,93,93,93,93,93,93,93,84,84,93,93}; |
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#else |
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PRH_VAR_TYPE PRH_ARR_THERM_LOW[16]; |
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#endif |
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|
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|
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/* |
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* id : THERM_HIGH |
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* type : <array>[16] |
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* Thermistor high limit /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_ARR_THERM_HIGH[16]={123,123,123,123,123,123,123,123,123,123,123,123,123,123,123,123}; |
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#else |
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PRH_VAR_TYPE PRH_ARR_THERM_HIGH[16]; |
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#endif |
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|
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|
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/* |
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* id : IPM_VOLTAGES_CHECK |
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* type : <var> |
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* Check if ipm are going to be checked /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_IPM_VOLTAGES_CHECK=1; |
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#else |
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PRH_VAR_TYPE PRH_VAR_IPM_VOLTAGES_CHECK; |
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#endif |
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|
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/* |
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* id : KHB_IDAQ_CHECK |
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* type : <var> |
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* Check if khb&idaq are going to be checked /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_KHB_IDAQ_CHECK=1; |
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#else |
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PRH_VAR_TYPE PRH_VAR_KHB_IDAQ_CHECK; |
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#endif |
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|
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/* |
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* id : NTRIG |
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* type : <var> |
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* Max Number of Lacks of Triggers /RO |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_NTRIG=3; |
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#else |
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PRH_VAR_TYPE PRH_VAR_NTRIG; |
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#endif |
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|
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/* |
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* id : TRIG |
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* type : <var> |
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* Counter of lacks of triggers /RW |
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* location: 2 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_TRIG=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_TRIG=0; |
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#endif |
| 270 |
|
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/* |
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* id : CONF |
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* type : <table>[5][6] |
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* active sensors - first dimention is the number of the incrementing configuration. second dimention is the number of FE /RO |
| 275 |
*/ |
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|
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_TAB_CONF[5][6]={{1,1,1,1,1,1},{1,1,1,1,1,0},{1,1,1,0,0,0},{1,0,1,0,0,0},{0,1,1,0,0,0}}; |
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#else |
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PRH_VAR_TYPE PRH_TAB_CONF[5][6]; |
| 282 |
#endif |
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|
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|
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|
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/* |
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* id : CONF_SEL |
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* type : <var> |
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* active sensor selector /RW |
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* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_CONF_SEL=0; |
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#else |
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PRH_VAR_TYPE PRH_VAR_CONF_SEL; |
| 297 |
#endif |
| 298 |
|
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/* |
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* id : CONFOK |
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* type : <var> |
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* whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON /RO |
| 303 |
* location: 3 |
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*/ |
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|
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#ifdef PRH_DEFAULT_MODE |
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PRH_VAR_TYPE PRH_VAR_CONFOK=1; |
| 308 |
#else |
| 309 |
PRH_VAR_TYPE PRH_VAR_CONFOK; |
| 310 |
#endif |
| 311 |
|
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/* |
| 313 |
* id : OFF |
| 314 |
* type : <var> |
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* Counter of ON/OFF /RW |
| 316 |
* location: 2 |
| 317 |
*/ |
| 318 |
|
| 319 |
#ifdef PRH_DEFAULT_MODE |
| 320 |
PRH_VAR_TYPE PRH_VAR_OFF=0; |
| 321 |
#else |
| 322 |
PRH_VAR_TYPE PRH_VAR_OFF=0; |
| 323 |
#endif |
| 324 |
|
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/* |
| 326 |
* id : NOFF |
| 327 |
* type : <var> |
| 328 |
* Max Number of ON/OFF /RO |
| 329 |
* location: 3 |
| 330 |
*/ |
| 331 |
|
| 332 |
#ifdef PRH_DEFAULT_MODE |
| 333 |
PRH_VAR_TYPE PRH_VAR_NOFF=2; |
| 334 |
#else |
| 335 |
PRH_VAR_TYPE PRH_VAR_NOFF; |
| 336 |
#endif |
| 337 |
|
| 338 |
/* |
| 339 |
* id : NRES |
| 340 |
* type : <var> |
| 341 |
* Max number of reset /RO |
| 342 |
* location: 3 |
| 343 |
*/ |
| 344 |
|
| 345 |
#ifdef PRH_DEFAULT_MODE |
| 346 |
PRH_VAR_TYPE PRH_VAR_NRES=6; |
| 347 |
#else |
| 348 |
PRH_VAR_TYPE PRH_VAR_NRES; |
| 349 |
#endif |
| 350 |
|
| 351 |
/* |
| 352 |
* id : RES |
| 353 |
* type : <var> |
| 354 |
* Counter of reset /RW |
| 355 |
* location: 2 |
| 356 |
*/ |
| 357 |
|
| 358 |
#ifdef PRH_DEFAULT_MODE |
| 359 |
PRH_VAR_TYPE PRH_VAR_RES=0; |
| 360 |
#else |
| 361 |
PRH_VAR_TYPE PRH_VAR_RES=0; |
| 362 |
#endif |
| 363 |
|
| 364 |
/* |
| 365 |
* id : WATCHDOG_RESET_DISABLE |
| 366 |
* type : <var> |
| 367 |
* disable watchdog reset: only for debugging! |
| 368 |
* location: 2 |
| 369 |
*/ |
| 370 |
|
| 371 |
#ifdef PRH_DEFAULT_MODE |
| 372 |
PRH_VAR_TYPE PRH_VAR_WATCHDOG_RESET_DISABLE=0; |
| 373 |
#else |
| 374 |
PRH_VAR_TYPE PRH_VAR_WATCHDOG_RESET_DISABLE=0; |
| 375 |
#endif |
| 376 |
|
| 377 |
/* |
| 378 |
* id : NFAILED_POWER_ON |
| 379 |
* type : <var> |
| 380 |
* max number of failed power_on, before STOP&WAIT /RO |
| 381 |
* location: 3 |
| 382 |
*/ |
| 383 |
|
| 384 |
#ifdef PRH_DEFAULT_MODE |
| 385 |
PRH_VAR_TYPE PRH_VAR_NFAILED_POWER_ON=3; |
| 386 |
#else |
| 387 |
PRH_VAR_TYPE PRH_VAR_NFAILED_POWER_ON; |
| 388 |
#endif |
| 389 |
|
| 390 |
/* |
| 391 |
* id : AUTO_RM_MODE |
| 392 |
* type : <var> |
| 393 |
* define the Automatic Mode for RM /RO |
| 394 |
* location: 2 |
| 395 |
*/ |
| 396 |
|
| 397 |
#ifdef PRH_DEFAULT_MODE |
| 398 |
PRH_VAR_TYPE PRH_VAR_AUTO_RM_MODE=0; |
| 399 |
#else |
| 400 |
PRH_VAR_TYPE PRH_VAR_AUTO_RM_MODE=0; |
| 401 |
#endif |
| 402 |
|
| 403 |
/* |
| 404 |
* id : AUTO_SCM_MODE |
| 405 |
* type : <var> |
| 406 |
* define the Automatic Mode for scm /RO |
| 407 |
* location: 2 |
| 408 |
*/ |
| 409 |
|
| 410 |
#ifdef PRH_DEFAULT_MODE |
| 411 |
PRH_VAR_TYPE PRH_VAR_AUTO_SCM_MODE=1; |
| 412 |
#else |
| 413 |
PRH_VAR_TYPE PRH_VAR_AUTO_SCM_MODE=1; |
| 414 |
#endif |
| 415 |
|
| 416 |
/* |
| 417 |
* id : MASK_ACQ_ALARM |
| 418 |
* type : <var> |
| 419 |
* Alarm mask /RO |
| 420 |
* location: 3 |
| 421 |
*/ |
| 422 |
|
| 423 |
#ifdef PRH_DEFAULT_MODE |
| 424 |
PRH_VAR_TYPE PRH_VAR_MASK_ACQ_ALARM=65535; |
| 425 |
#else |
| 426 |
PRH_VAR_TYPE PRH_VAR_MASK_ACQ_ALARM; |
| 427 |
#endif |
| 428 |
|
| 429 |
/* |
| 430 |
* id : GOM_DURING_ALARM |
| 431 |
* type : <var> |
| 432 |
* General operation mode during alarm revelation /RW |
| 433 |
* location: 2 |
| 434 |
*/ |
| 435 |
|
| 436 |
#ifdef PRH_DEFAULT_MODE |
| 437 |
PRH_VAR_TYPE PRH_VAR_GOM_DURING_ALARM=0; |
| 438 |
#else |
| 439 |
PRH_VAR_TYPE PRH_VAR_GOM_DURING_ALARM=0; |
| 440 |
#endif |
| 441 |
|
| 442 |
/* |
| 443 |
* id : PM_FORCE_RUNNING_TIMEOUT |
| 444 |
* type : <var> |
| 445 |
* waiting for start select mode before force go to running |
| 446 |
* location: 3 |
| 447 |
*/ |
| 448 |
|
| 449 |
#ifdef PRH_DEFAULT_MODE |
| 450 |
PRH_VAR_TYPE PRH_VAR_PM_FORCE_RUNNING_TIMEOUT=3600000; |
| 451 |
#else |
| 452 |
PRH_VAR_TYPE PRH_VAR_PM_FORCE_RUNNING_TIMEOUT; |
| 453 |
#endif |
| 454 |
|
| 455 |
/* |
| 456 |
* id : PAMELA_ON |
| 457 |
* type : <var> |
| 458 |
* Pamela status [0=OFF-1:OFF] /RW |
| 459 |
* location: 2 |
| 460 |
*/ |
| 461 |
|
| 462 |
#ifdef PRH_DEFAULT_MODE |
| 463 |
PRH_VAR_TYPE PRH_VAR_PAMELA_ON=0; |
| 464 |
#else |
| 465 |
PRH_VAR_TYPE PRH_VAR_PAMELA_ON=0; |
| 466 |
#endif |
| 467 |
|
| 468 |
/* |
| 469 |
* id : N_CALIB |
| 470 |
* type : <var> |
| 471 |
* Counter of calibratrion since start up /RW |
| 472 |
* location: 2 |
| 473 |
*/ |
| 474 |
|
| 475 |
#ifdef PRH_DEFAULT_MODE |
| 476 |
PRH_VAR_TYPE PRH_VAR_N_CALIB=0; |
| 477 |
#else |
| 478 |
PRH_VAR_TYPE PRH_VAR_N_CALIB=0; |
| 479 |
#endif |
| 480 |
|
| 481 |
/* |
| 482 |
* id : AC_1_ON |
| 483 |
* type : <var> |
| 484 |
* AC 1 on from initialization /RW |
| 485 |
* location: 2 |
| 486 |
*/ |
| 487 |
|
| 488 |
#ifdef PRH_DEFAULT_MODE |
| 489 |
PRH_VAR_TYPE PRH_VAR_AC_1_ON=0; |
| 490 |
#else |
| 491 |
PRH_VAR_TYPE PRH_VAR_AC_1_ON=0; |
| 492 |
#endif |
| 493 |
|
| 494 |
/* |
| 495 |
* id : AC_2_ON |
| 496 |
* type : <var> |
| 497 |
* AC 2 on from initialization /RW |
| 498 |
* location: 2 |
| 499 |
*/ |
| 500 |
|
| 501 |
#ifdef PRH_DEFAULT_MODE |
| 502 |
PRH_VAR_TYPE PRH_VAR_AC_2_ON=0; |
| 503 |
#else |
| 504 |
PRH_VAR_TYPE PRH_VAR_AC_2_ON=0; |
| 505 |
#endif |
| 506 |
|
| 507 |
/* |
| 508 |
* id : POWER_MODE |
| 509 |
* type : <var> |
| 510 |
* Power mode of PAMELA /RW |
| 511 |
* location: 3 |
| 512 |
*/ |
| 513 |
|
| 514 |
#ifdef PRH_DEFAULT_MODE |
| 515 |
PRH_VAR_TYPE PRH_VAR_POWER_MODE=1; |
| 516 |
#else |
| 517 |
PRH_VAR_TYPE PRH_VAR_POWER_MODE; |
| 518 |
#endif |
| 519 |
|
| 520 |
/* |
| 521 |
* id : TRIG_II |
| 522 |
* type : <var> |
| 523 |
* TRIGGER II level mode on/off /RO |
| 524 |
* location: 3 |
| 525 |
*/ |
| 526 |
|
| 527 |
#ifdef PRH_DEFAULT_MODE |
| 528 |
PRH_VAR_TYPE PRH_VAR_TRIG_II=0; |
| 529 |
#else |
| 530 |
PRH_VAR_TYPE PRH_VAR_TRIG_II; |
| 531 |
#endif |
| 532 |
|
| 533 |
/* |
| 534 |
* id : BUF_LEN_TRIG_II_INIT |
| 535 |
* type : <var> |
| 536 |
* TRIG_II init command queue |
| 537 |
* location: 1 |
| 538 |
*/ |
| 539 |
|
| 540 |
#ifdef PRH_DEFAULT_MODE |
| 541 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRIG_II_INIT=199; |
| 542 |
#else |
| 543 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRIG_II_INIT; |
| 544 |
#endif |
| 545 |
|
| 546 |
/* |
| 547 |
* id : BUF_TRIG_II_INIT |
| 548 |
* type : <array>[3750] |
| 549 |
* TRIG_II init command queue |
| 550 |
* location: 1 |
| 551 |
*/ |
| 552 |
|
| 553 |
#ifdef PRH_DEFAULT_MODE |
| 554 |
PRH_VAR_TYPE PRH_ARR_BUF_TRIG_II_INIT[3750]={0x06D0212D,0x0001AA7F,0xD043330A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F310A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00001803,0x3F000000,0x0A000FAA,0x06D0212D,0x0000AA07,0xD043331C,0x030FAA00}; |
| 555 |
#else |
| 556 |
PRH_VAR_TYPE PRH_ARR_BUF_TRIG_II_INIT[3750]; |
| 557 |
#endif |
| 558 |
|
| 559 |
|
| 560 |
/* |
| 561 |
* id : BUF_LEN_TRIG_II_ACQ |
| 562 |
* type : <var> |
| 563 |
* TRIG_II acq command queue |
| 564 |
* location: 1 |
| 565 |
*/ |
| 566 |
|
| 567 |
#ifdef PRH_DEFAULT_MODE |
| 568 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRIG_II_ACQ=561; |
| 569 |
#else |
| 570 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRIG_II_ACQ; |
| 571 |
#endif |
| 572 |
|
| 573 |
/* |
| 574 |
* id : BUF_TRIG_II_ACQ |
| 575 |
* type : <array>[375] |
| 576 |
* TRIG_II acq command queue |
| 577 |
* location: 1 |
| 578 |
*/ |
| 579 |
|
| 580 |
#ifdef PRH_DEFAULT_MODE |
| 581 |
PRH_VAR_TYPE PRH_ARR_BUF_TRIG_II_ACQ[375]={0x039DF6AA,0x080A2171,0x0006015D,0xAA080A21,0x61000355,0xD0AA080A,0x2171000C,0x11AFAA08,0x0A216100,0x040110AA,0x080A2161,0x00041160,0xAA080A31,0x41003001,0x73AA080A,0x31510030,0x0114AA08,0x0A212100,0x08056BAA,0x080A2111,0x00070214,0xAA080A21,0x11000201,0x5CAA0608,0x21D0C1F3,0xAA060821,0xD0C2FAAA,0x06A810E0,0xC00DAA0D,0xAD100000,0x00000000,0x00000000,0xAA060821,0xD1C1E6AA,0x060821D1,0xC2EFAA06,0xA810E1C0,0x18AA0DAD,0x10000000,0x00000000,0x000000AA,0x060821D2,0xC1D9AA06,0x0821D2C2,0xD0AA06A8,0x10E2C027,0xAA0DAD10,0x00000000,0x00000000,0x0000AA06,0x0821D3C1,0xCCAA0608,0x21D3C2C5,0xAA06A810,0xE3C032AA,0x0DAD1000,0x00000000,0x00000000,0x00AA0608,0x21D4C1A7,0xAA060821,0xD4C2AEAA,0x06A810E4,0xC059AA0D,0xAD100000,0x00000000,0x00000000,0xAA060821,0xD5C1B2AA,0x060821D5,0xC2BBAA06,0xA810E5C0,0x4CAA0DAD,0x10000000,0x00000000,0x000000AA,0x05A8100F,0x2DAA0B09,0x31008100,0x40003F52,0x90AA0B07,0x31008100,0x40003F52,0x90AA0702,0x71E874A7,0x08AA0703,0x71E874A7,0x08AA0704,0x71E874A7,0x08AA0705,0x71E874A7,0x08AA0D00,0x92000708,0x53006000,0x0F709DAA,0x0D009200,0x07182300,0x60000F70,0x03AA0D00,0x92000728,0xB3006000,0x0F70A6AA,0x0D009200,0x0738C300,0x60000F70,0x38AA0D00,0x92000748,0x94006000,0x0F70EBAA,0x0D009200,0x0758E400,0x60000F70,0x75AA0D01,0x92000708,0x53006000,0x0F709DAA,0x0D019200,0x07182300,0x60000F70,0x03AA0D01,0x92000728,0xB3006000,0x0F70A6AA,0x0D019200,0x0738C300,0x60000F70,0x38AA0D01,0x92000748,0x94006000,0x0F70EBAA,0x0D019200,0x0758E400,0x60000F70,0x75AA0806,0x320002D8,0x2C2CAA05,0x0C210000,0xAA050C21,0x0000AA05,0x0C210000,0xAA000000}; |
| 582 |
#else |
| 583 |
PRH_VAR_TYPE PRH_ARR_BUF_TRIG_II_ACQ[375]; |
| 584 |
#endif |
| 585 |
|
| 586 |
|
| 587 |
/* |
| 588 |
* id : EXP64_MODE |
| 589 |
* type : <var> |
| 590 |
* if TRUE, working in exp 64 mode /RO |
| 591 |
* location: 3 |
| 592 |
*/ |
| 593 |
|
| 594 |
#ifdef PRH_DEFAULT_MODE |
| 595 |
PRH_VAR_TYPE PRH_VAR_EXP64_MODE=1; |
| 596 |
#else |
| 597 |
PRH_VAR_TYPE PRH_VAR_EXP64_MODE; |
| 598 |
#endif |
| 599 |
|
| 600 |
/* |
| 601 |
* id : EXP64_MODE_DELAY |
| 602 |
* type : <var> |
| 603 |
* delay for exp 64 mode acquiring /RO |
| 604 |
* location: 3 |
| 605 |
*/ |
| 606 |
|
| 607 |
#ifdef PRH_DEFAULT_MODE |
| 608 |
PRH_VAR_TYPE PRH_VAR_EXP64_MODE_DELAY=0; |
| 609 |
#else |
| 610 |
PRH_VAR_TYPE PRH_VAR_EXP64_MODE_DELAY; |
| 611 |
#endif |
| 612 |
|
| 613 |
/* |
| 614 |
* id : MH_END_OF_DOWNLOAD_TIMEOUT |
| 615 |
* type : <var> |
| 616 |
* time out of the end of download /RO |
| 617 |
* location: 3 |
| 618 |
*/ |
| 619 |
|
| 620 |
#ifdef PRH_DEFAULT_MODE |
| 621 |
PRH_VAR_TYPE PRH_VAR_MH_END_OF_DOWNLOAD_TIMEOUT=60000; |
| 622 |
#else |
| 623 |
PRH_VAR_TYPE PRH_VAR_MH_END_OF_DOWNLOAD_TIMEOUT; |
| 624 |
#endif |
| 625 |
|
| 626 |
/* |
| 627 |
* --------- PAMELA Pam Manager Parameters: ------------- |
| 628 |
*/ |
| 629 |
|
| 630 |
|
| 631 |
/* |
| 632 |
* id : PM_STOP_RUNMANAGER_TIMEOUT |
| 633 |
* type : <var> |
| 634 |
* the maximu time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager /RO |
| 635 |
* location: 3 |
| 636 |
*/ |
| 637 |
|
| 638 |
#ifdef PRH_DEFAULT_MODE |
| 639 |
PRH_VAR_TYPE PRH_VAR_PM_STOP_RUNMANAGER_TIMEOUT=1000; |
| 640 |
#else |
| 641 |
PRH_VAR_TYPE PRH_VAR_PM_STOP_RUNMANAGER_TIMEOUT; |
| 642 |
#endif |
| 643 |
|
| 644 |
/* |
| 645 |
* id : PM_STOP_RUNMANAGER_TIMES_RETRY |
| 646 |
* type : <var> |
| 647 |
* The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle. /RO |
| 648 |
* location: 3 |
| 649 |
*/ |
| 650 |
|
| 651 |
#ifdef PRH_DEFAULT_MODE |
| 652 |
PRH_VAR_TYPE PRH_VAR_PM_STOP_RUNMANAGER_TIMES_RETRY=5; |
| 653 |
#else |
| 654 |
PRH_VAR_TYPE PRH_VAR_PM_STOP_RUNMANAGER_TIMES_RETRY; |
| 655 |
#endif |
| 656 |
|
| 657 |
/* |
| 658 |
* id : PM_N_ORBIT_CALIB |
| 659 |
* type : <var> |
| 660 |
* Number of orbits per calibration /RO |
| 661 |
* location: 3 |
| 662 |
*/ |
| 663 |
|
| 664 |
#ifdef PRH_DEFAULT_MODE |
| 665 |
PRH_VAR_TYPE PRH_VAR_PM_N_ORBIT_CALIB=1; |
| 666 |
#else |
| 667 |
PRH_VAR_TYPE PRH_VAR_PM_N_ORBIT_CALIB; |
| 668 |
#endif |
| 669 |
|
| 670 |
/* |
| 671 |
* --------- PAMELA Working Schedule Module: ------------- |
| 672 |
*/ |
| 673 |
|
| 674 |
|
| 675 |
/* |
| 676 |
* id : WS_1_SETTING |
| 677 |
* type : <array>[5] |
| 678 |
* Define the Working Schedule #1 values in ms /RO |
| 679 |
* location: 3 |
| 680 |
*/ |
| 681 |
|
| 682 |
#ifdef PRH_DEFAULT_MODE |
| 683 |
PRH_VAR_TYPE PRH_ARR_WS_1_SETTING[5]={720000,2160000,2700000,5490000,6390000}; |
| 684 |
#else |
| 685 |
PRH_VAR_TYPE PRH_ARR_WS_1_SETTING[5]; |
| 686 |
#endif |
| 687 |
|
| 688 |
|
| 689 |
/* |
| 690 |
* id : WS_TIME_ORBIT |
| 691 |
* type : <var> |
| 692 |
* The duration in millisencond of the full orbit in ms /RO |
| 693 |
* location: 3 |
| 694 |
*/ |
| 695 |
|
| 696 |
#ifdef PRH_DEFAULT_MODE |
| 697 |
PRH_VAR_TYPE PRH_VAR_WS_TIME_ORBIT=5670000; |
| 698 |
#else |
| 699 |
PRH_VAR_TYPE PRH_VAR_WS_TIME_ORBIT; |
| 700 |
#endif |
| 701 |
|
| 702 |
/* |
| 703 |
* id : WS_FAVOURITE_WS |
| 704 |
* type : <var> |
| 705 |
* The Favourite Pamela Working Schedule /RO |
| 706 |
* location: 3 |
| 707 |
*/ |
| 708 |
|
| 709 |
#ifdef PRH_DEFAULT_MODE |
| 710 |
PRH_VAR_TYPE PRH_VAR_WS_FAVOURITE_WS=0; |
| 711 |
#else |
| 712 |
PRH_VAR_TYPE PRH_VAR_WS_FAVOURITE_WS; |
| 713 |
#endif |
| 714 |
|
| 715 |
/* |
| 716 |
* --------- PAMELA Mode Handler ------------- |
| 717 |
*/ |
| 718 |
|
| 719 |
|
| 720 |
/* |
| 721 |
* --------- PAMELA Run Manager Parameters: ------------- |
| 722 |
*/ |
| 723 |
|
| 724 |
|
| 725 |
/* |
| 726 |
* id : RM_N_TRIES_PREPARE_PAGE |
| 727 |
* type : <var> |
| 728 |
* Number of attempts to try to exec the prepar page before exit from the run procedure with an error /RO |
| 729 |
* location: 3 |
| 730 |
*/ |
| 731 |
|
| 732 |
#ifdef PRH_DEFAULT_MODE |
| 733 |
PRH_VAR_TYPE PRH_VAR_RM_N_TRIES_PREPARE_PAGE=100; |
| 734 |
#else |
| 735 |
PRH_VAR_TYPE PRH_VAR_RM_N_TRIES_PREPARE_PAGE; |
| 736 |
#endif |
| 737 |
|
| 738 |
/* |
| 739 |
* id : RM_TRIES_PREPARE_PAGE_SLEEP |
| 740 |
* type : <var> |
| 741 |
* Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure /RO |
| 742 |
* location: 3 |
| 743 |
*/ |
| 744 |
|
| 745 |
#ifdef PRH_DEFAULT_MODE |
| 746 |
PRH_VAR_TYPE PRH_VAR_RM_TRIES_PREPARE_PAGE_SLEEP=2; |
| 747 |
#else |
| 748 |
PRH_VAR_TYPE PRH_VAR_RM_TRIES_PREPARE_PAGE_SLEEP; |
| 749 |
#endif |
| 750 |
|
| 751 |
/* |
| 752 |
* id : RM_WS3_TIMER_FIRE_AFTER |
| 753 |
* type : <var> |
| 754 |
* Time to wait for the WS3 timer to fire /RO |
| 755 |
* location: 3 |
| 756 |
*/ |
| 757 |
|
| 758 |
#ifdef PRH_DEFAULT_MODE |
| 759 |
PRH_VAR_TYPE PRH_VAR_RM_WS3_TIMER_FIRE_AFTER=8000; |
| 760 |
#else |
| 761 |
PRH_VAR_TYPE PRH_VAR_RM_WS3_TIMER_FIRE_AFTER; |
| 762 |
#endif |
| 763 |
|
| 764 |
/* |
| 765 |
* id : RM_RATE_METER_S1_TRH |
| 766 |
* type : <array>[2] |
| 767 |
* Rate meter s1 register TRH.used to toggle A/B mode in WS3 mode. the index of the array is related to the current ACQ mode (0=A to B,1=B to A) /RO |
| 768 |
* location: 3 |
| 769 |
*/ |
| 770 |
|
| 771 |
#ifdef PRH_DEFAULT_MODE |
| 772 |
PRH_VAR_TYPE PRH_ARR_RM_RATE_METER_S1_TRH[2]={2000,1600}; |
| 773 |
#else |
| 774 |
PRH_VAR_TYPE PRH_ARR_RM_RATE_METER_S1_TRH[2]; |
| 775 |
#endif |
| 776 |
|
| 777 |
|
| 778 |
/* |
| 779 |
* id : RM_TIME_MAX_RUN |
| 780 |
* type : <var> |
| 781 |
* Max duration for an ordinary Run in milliseconds /RO |
| 782 |
* location: 3 |
| 783 |
*/ |
| 784 |
|
| 785 |
#ifdef PRH_DEFAULT_MODE |
| 786 |
PRH_VAR_TYPE PRH_VAR_RM_TIME_MAX_RUN=1800000; |
| 787 |
#else |
| 788 |
PRH_VAR_TYPE PRH_VAR_RM_TIME_MAX_RUN; |
| 789 |
#endif |
| 790 |
|
| 791 |
/* |
| 792 |
* id : RM_TIME_SPECIAL_RUN |
| 793 |
* type : <var> |
| 794 |
* duration for the special run in milliseconds /RO |
| 795 |
* location: 3 |
| 796 |
*/ |
| 797 |
|
| 798 |
#ifdef PRH_DEFAULT_MODE |
| 799 |
PRH_VAR_TYPE PRH_VAR_RM_TIME_SPECIAL_RUN=100000; |
| 800 |
#else |
| 801 |
PRH_VAR_TYPE PRH_VAR_RM_TIME_SPECIAL_RUN; |
| 802 |
#endif |
| 803 |
|
| 804 |
/* |
| 805 |
* id : RM_ACQCHECK_PERIOD |
| 806 |
* type : <var> |
| 807 |
* period of acquisition check in milliseconds /RO |
| 808 |
* location: 3 |
| 809 |
*/ |
| 810 |
|
| 811 |
#ifdef PRH_DEFAULT_MODE |
| 812 |
PRH_VAR_TYPE PRH_VAR_RM_ACQCHECK_PERIOD=1000; |
| 813 |
#else |
| 814 |
PRH_VAR_TYPE PRH_VAR_RM_ACQCHECK_PERIOD; |
| 815 |
#endif |
| 816 |
|
| 817 |
/* |
| 818 |
* id : RM_FLUSH_TIMEOUT |
| 819 |
* type : <var> |
| 820 |
* timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT /RO |
| 821 |
* location: 3 |
| 822 |
*/ |
| 823 |
|
| 824 |
#ifdef PRH_DEFAULT_MODE |
| 825 |
PRH_VAR_TYPE PRH_VAR_RM_FLUSH_TIMEOUT=20000; |
| 826 |
#else |
| 827 |
PRH_VAR_TYPE PRH_VAR_RM_FLUSH_TIMEOUT; |
| 828 |
#endif |
| 829 |
|
| 830 |
/* |
| 831 |
* id : RM_NO_FLUSH_PARAM_DUMP |
| 832 |
* type : <var> |
| 833 |
* Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never. /RO |
| 834 |
* location: 3 |
| 835 |
*/ |
| 836 |
|
| 837 |
#ifdef PRH_DEFAULT_MODE |
| 838 |
PRH_VAR_TYPE PRH_VAR_RM_NO_FLUSH_PARAM_DUMP=200; |
| 839 |
#else |
| 840 |
PRH_VAR_TYPE PRH_VAR_RM_NO_FLUSH_PARAM_DUMP; |
| 841 |
#endif |
| 842 |
|
| 843 |
/* |
| 844 |
* id : RM_DUMP_ALL_PARAMS |
| 845 |
* type : <var> |
| 846 |
* dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs /RO |
| 847 |
* location: 3 |
| 848 |
*/ |
| 849 |
|
| 850 |
#ifdef PRH_DEFAULT_MODE |
| 851 |
PRH_VAR_TYPE PRH_VAR_RM_DUMP_ALL_PARAMS=0; |
| 852 |
#else |
| 853 |
PRH_VAR_TYPE PRH_VAR_RM_DUMP_ALL_PARAMS; |
| 854 |
#endif |
| 855 |
|
| 856 |
/* |
| 857 |
* id : RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ |
| 858 |
* type : <var> |
| 859 |
* number of release busy inserted in the ACQ command queue in After_Calib mode /RO |
| 860 |
* location: 3 |
| 861 |
*/ |
| 862 |
|
| 863 |
#ifdef PRH_DEFAULT_MODE |
| 864 |
PRH_VAR_TYPE PRH_VAR_RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ=70; |
| 865 |
#else |
| 866 |
PRH_VAR_TYPE PRH_VAR_RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ; |
| 867 |
#endif |
| 868 |
|
| 869 |
/* |
| 870 |
* --------- PAMELA System Control Manager Parameters: ------------- |
| 871 |
*/ |
| 872 |
|
| 873 |
|
| 874 |
/* |
| 875 |
* id : PWR_IPM_CONF |
| 876 |
* type : <array>[6] |
| 877 |
* IMP desired configuration for initial poweron 6 bitmask /RO |
| 878 |
* location: 3 |
| 879 |
*/ |
| 880 |
|
| 881 |
#ifdef PRH_DEFAULT_MODE |
| 882 |
PRH_VAR_TYPE PRH_ARR_PWR_IPM_CONF[6]={1,1,1,1,1,1}; |
| 883 |
#else |
| 884 |
PRH_VAR_TYPE PRH_ARR_PWR_IPM_CONF[6]; |
| 885 |
#endif |
| 886 |
|
| 887 |
|
| 888 |
/* |
| 889 |
* id : PWR_WAIT_BEFORE_SENDTC |
| 890 |
* type : <var> |
| 891 |
* time to wait before send 2 successive HL /RO |
| 892 |
* location: 3 |
| 893 |
*/ |
| 894 |
|
| 895 |
#ifdef PRH_DEFAULT_MODE |
| 896 |
PRH_VAR_TYPE PRH_VAR_PWR_WAIT_BEFORE_SENDTC=110; |
| 897 |
#else |
| 898 |
PRH_VAR_TYPE PRH_VAR_PWR_WAIT_BEFORE_SENDTC; |
| 899 |
#endif |
| 900 |
|
| 901 |
/* |
| 902 |
* id : PWR_CMD2PSB_DELAY |
| 903 |
* type : <var> |
| 904 |
* time to wait before every CMD2PSB |
| 905 |
* location: 3 |
| 906 |
*/ |
| 907 |
|
| 908 |
#ifdef PRH_DEFAULT_MODE |
| 909 |
PRH_VAR_TYPE PRH_VAR_PWR_CMD2PSB_DELAY=100; |
| 910 |
#else |
| 911 |
PRH_VAR_TYPE PRH_VAR_PWR_CMD2PSB_DELAY; |
| 912 |
#endif |
| 913 |
|
| 914 |
/* |
| 915 |
* id : PWR_TRB_READ_ATTEMPTS |
| 916 |
* type : <var> |
| 917 |
* number of attempts to sent a command to the TRB before a timeout /RO |
| 918 |
* location: 3 |
| 919 |
*/ |
| 920 |
|
| 921 |
#ifdef PRH_DEFAULT_MODE |
| 922 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB_READ_ATTEMPTS=10; |
| 923 |
#else |
| 924 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB_READ_ATTEMPTS; |
| 925 |
#endif |
| 926 |
|
| 927 |
/* |
| 928 |
* id : PWR_KHB_INITBOARD_TWICE_DELAY |
| 929 |
* type : <var> |
| 930 |
* milliseconds to wait between two KHB Init Board in PWR_DcdcON /RO |
| 931 |
* location: 3 |
| 932 |
*/ |
| 933 |
|
| 934 |
#ifdef PRH_DEFAULT_MODE |
| 935 |
PRH_VAR_TYPE PRH_VAR_PWR_KHB_INITBOARD_TWICE_DELAY=500; |
| 936 |
#else |
| 937 |
PRH_VAR_TYPE PRH_VAR_PWR_KHB_INITBOARD_TWICE_DELAY; |
| 938 |
#endif |
| 939 |
|
| 940 |
|
| 941 |
|
| 942 |
|
| 943 |
|
| 944 |
/* |
| 945 |
* id : PWR_IPM_WAIT_OK_N_ATTEMPT |
| 946 |
* type : <var> |
| 947 |
* attempts of ipm check ok at power on /RO |
| 948 |
* location: 3 |
| 949 |
*/ |
| 950 |
|
| 951 |
#ifdef PRH_DEFAULT_MODE |
| 952 |
PRH_VAR_TYPE PRH_VAR_PWR_IPM_WAIT_OK_N_ATTEMPT=150; |
| 953 |
#else |
| 954 |
PRH_VAR_TYPE PRH_VAR_PWR_IPM_WAIT_OK_N_ATTEMPT; |
| 955 |
#endif |
| 956 |
|
| 957 |
/* |
| 958 |
* id : PWR_IPM_WAIT_OK_DELAY_ATTEMPT |
| 959 |
* type : <var> |
| 960 |
* attempts of ipm check ok at power on /RO |
| 961 |
* location: 3 |
| 962 |
*/ |
| 963 |
|
| 964 |
#ifdef PRH_DEFAULT_MODE |
| 965 |
PRH_VAR_TYPE PRH_VAR_PWR_IPM_WAIT_OK_DELAY_ATTEMPT=1000; |
| 966 |
#else |
| 967 |
PRH_VAR_TYPE PRH_VAR_PWR_IPM_WAIT_OK_DELAY_ATTEMPT; |
| 968 |
#endif |
| 969 |
|
| 970 |
/* |
| 971 |
* id : PWR_VOLTAGE_N_ATTEMPT |
| 972 |
* type : <var> |
| 973 |
* no of millisecond to wait in VOLTAGE IPM procedure /RO |
| 974 |
* location: 3 |
| 975 |
*/ |
| 976 |
|
| 977 |
#ifdef PRH_DEFAULT_MODE |
| 978 |
PRH_VAR_TYPE PRH_VAR_PWR_VOLTAGE_N_ATTEMPT=10; |
| 979 |
#else |
| 980 |
PRH_VAR_TYPE PRH_VAR_PWR_VOLTAGE_N_ATTEMPT; |
| 981 |
#endif |
| 982 |
|
| 983 |
/* |
| 984 |
* id : PWR_VOLTAGE_DELAY_ATTEMPT |
| 985 |
* type : <var> |
| 986 |
* no of millisecond to wain in VOLTAGE IPM procedure /RO |
| 987 |
* location: 3 |
| 988 |
*/ |
| 989 |
|
| 990 |
#ifdef PRH_DEFAULT_MODE |
| 991 |
PRH_VAR_TYPE PRH_VAR_PWR_VOLTAGE_DELAY_ATTEMPT=1000; |
| 992 |
#else |
| 993 |
PRH_VAR_TYPE PRH_VAR_PWR_VOLTAGE_DELAY_ATTEMPT; |
| 994 |
#endif |
| 995 |
|
| 996 |
/* |
| 997 |
* id : PWR_VOLTAGE_IPM_RANGE_ON_MAX |
| 998 |
* type : <array>[6] |
| 999 |
* ADC min voltage values if ON /RO |
| 1000 |
* location: 3 |
| 1001 |
*/ |
| 1002 |
|
| 1003 |
#ifdef PRH_DEFAULT_MODE |
| 1004 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MAX[6]={0xd4,0xd4,0xd4,0xd4,0xd4,0xd4}; |
| 1005 |
#else |
| 1006 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MAX[6]; |
| 1007 |
#endif |
| 1008 |
|
| 1009 |
|
| 1010 |
/* |
| 1011 |
* id : PWR_VOLTAGE_IPM_RANGE_ON_MIN |
| 1012 |
* type : <array>[6] |
| 1013 |
* ADC min voltage values if ON /RO |
| 1014 |
* location: 3 |
| 1015 |
*/ |
| 1016 |
|
| 1017 |
#ifdef PRH_DEFAULT_MODE |
| 1018 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MIN[6]={0x9e,0x9e,0x9e,0x9e,0x9e,0x9e}; |
| 1019 |
#else |
| 1020 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MIN[6]; |
| 1021 |
#endif |
| 1022 |
|
| 1023 |
|
| 1024 |
/* |
| 1025 |
* id : PWR_VOLTAGE_IPM_RANGE_OFF_MAX |
| 1026 |
* type : <array>[6] |
| 1027 |
* ADC min voltage values if OFF /RO |
| 1028 |
* location: 3 |
| 1029 |
*/ |
| 1030 |
|
| 1031 |
#ifdef PRH_DEFAULT_MODE |
| 1032 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MAX[6]={0x20,0x20,0x20,0x20,0x20,0x20}; |
| 1033 |
#else |
| 1034 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MAX[6]; |
| 1035 |
#endif |
| 1036 |
|
| 1037 |
|
| 1038 |
/* |
| 1039 |
* id : PWR_VOLTAGE_IPM_RANGE_OFF_MIN |
| 1040 |
* type : <array>[6] |
| 1041 |
* ADC min voltage values if OFF /RO |
| 1042 |
* location: 3 |
| 1043 |
*/ |
| 1044 |
|
| 1045 |
#ifdef PRH_DEFAULT_MODE |
| 1046 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MIN[6]={ 0, 0, 0, 0, 0, 0}; |
| 1047 |
#else |
| 1048 |
PRH_VAR_TYPE PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MIN[6]; |
| 1049 |
#endif |
| 1050 |
|
| 1051 |
|
| 1052 |
/* |
| 1053 |
* id : PWR_TRB1_SET |
| 1054 |
* type : <var> |
| 1055 |
* trb 1 setting /RO |
| 1056 |
* location: 3 |
| 1057 |
*/ |
| 1058 |
|
| 1059 |
#ifdef PRH_DEFAULT_MODE |
| 1060 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB1_SET=16383; |
| 1061 |
#else |
| 1062 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB1_SET; |
| 1063 |
#endif |
| 1064 |
|
| 1065 |
/* |
| 1066 |
* id : PWR_TRB2_SET |
| 1067 |
* type : <var> |
| 1068 |
* trb 2 setting /RO |
| 1069 |
* location: 3 |
| 1070 |
*/ |
| 1071 |
|
| 1072 |
#ifdef PRH_DEFAULT_MODE |
| 1073 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB2_SET=16383; |
| 1074 |
#else |
| 1075 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB2_SET; |
| 1076 |
#endif |
| 1077 |
|
| 1078 |
/* |
| 1079 |
* id : PWR_TRB_SET_DELAY |
| 1080 |
* type : <var> |
| 1081 |
* delay after trb set cmd /RO |
| 1082 |
* location: 3 |
| 1083 |
*/ |
| 1084 |
|
| 1085 |
#ifdef PRH_DEFAULT_MODE |
| 1086 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB_SET_DELAY=20; |
| 1087 |
#else |
| 1088 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB_SET_DELAY; |
| 1089 |
#endif |
| 1090 |
|
| 1091 |
/* |
| 1092 |
* id : PWR_TRB_READ_DELAY |
| 1093 |
* type : <var> |
| 1094 |
* delay after trb read cmd /RO |
| 1095 |
* location: 3 |
| 1096 |
*/ |
| 1097 |
|
| 1098 |
#ifdef PRH_DEFAULT_MODE |
| 1099 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB_READ_DELAY=20; |
| 1100 |
#else |
| 1101 |
PRH_VAR_TYPE PRH_VAR_PWR_TRB_READ_DELAY; |
| 1102 |
#endif |
| 1103 |
|
| 1104 |
/* |
| 1105 |
* id : PWR_IPM_ACTION |
| 1106 |
* type : <table>[3][64] |
| 1107 |
* Main Table for actions to be done in IPM Check procedure |
| 1108 |
*/ |
| 1109 |
|
| 1110 |
|
| 1111 |
#ifdef PRH_DEFAULT_MODE |
| 1112 |
PRH_VAR_TYPE PRH_TAB_PWR_IPM_ACTION[3][64]={ |
| 1113 |
/* format is: |
| 1114 |
index0 is the couple of ipm (see typedef PWR_IPM3) |
| 1115 |
index1 codes the following info (6 bit map) |
| 1116 |
bit 0: CC[ipm1] read on TM port |
| 1117 |
bit 1: CC[ipm1] read on TM port |
| 1118 |
bit 2: ADC[ipm1] read on TM port |
| 1119 |
bit 3: ADC[ipm2] read on TM port |
| 1120 |
bit 3: PWR_IPM_CONF[ipm1] |
| 1121 |
bit 4: PWR_IPM_CONF[ipm2] |
| 1122 |
|
| 1123 |
Values are coded followind this convetions: |
| 1124 |
bit 8 IPM_TRB (CM_HOT,CM_COLD) |
| 1125 |
bit 4-7 Action (see typedef PWR_IPM_ACTION) |
| 1126 |
bit 0-3 TimeOutAction (seet typedef PWR_IPM_TO_ACTION) |
| 1127 |
|
| 1128 |
typedef enum { |
| 1129 |
PWR_IPM_TO_ACTION_STOP, |
| 1130 |
PWR_IPM_TO_ACTION_CONTINUE, |
| 1131 |
} PWR_IPM_TO_ACTION; |
| 1132 |
|
| 1133 |
typedef enum { |
| 1134 |
PWR_IPM_ACTION_ON_HOT, |
| 1135 |
PWR_IPM_ACTION_ON_COLD, |
| 1136 |
PWR_IPM_ACTION_ON_TOGGLED, |
| 1137 |
PWR_IPM_ACTION_OFF, |
| 1138 |
PWR_IPM_ACTION_EXIT_OK, |
| 1139 |
PWR_IPM_ACTION_EXIT_BAD, |
| 1140 |
} PWR_IPM_ACTION; |
| 1141 |
|
| 1142 |
typedef enum |
| 1143 |
{ |
| 1144 |
CM_HOT, |
| 1145 |
CM_COLD, |
| 1146 |
CM_HOT_COLD_MAX |
| 1147 |
} CM_HOT_COLD; |
| 1148 |
|
| 1149 |
|
| 1150 |
*/ |
| 1151 |
#include "PWR_IPMActionTable.h" |
| 1152 |
, |
| 1153 |
#include "PWR_IPMActionTable.h" |
| 1154 |
, |
| 1155 |
#include "PWR_IPMActionTable.h" |
| 1156 |
|
| 1157 |
}; |
| 1158 |
#else |
| 1159 |
PRH_VAR_TYPE PRH_TAB_PWR_IPM_ACTION[3][64]; |
| 1160 |
#endif |
| 1161 |
|
| 1162 |
|
| 1163 |
|
| 1164 |
/* |
| 1165 |
* --------- HB Module Parameters : ------------- |
| 1166 |
*/ |
| 1167 |
|
| 1168 |
|
| 1169 |
/* |
| 1170 |
* id : HB_N_ATTEMPT_WRITE2PIF |
| 1171 |
* type : <var> |
| 1172 |
* Number of attempt to write on PIF after return an error /RO |
| 1173 |
* location: 3 |
| 1174 |
*/ |
| 1175 |
|
| 1176 |
#ifdef PRH_DEFAULT_MODE |
| 1177 |
PRH_VAR_TYPE PRH_VAR_HB_N_ATTEMPT_WRITE2PIF=2; |
| 1178 |
#else |
| 1179 |
PRH_VAR_TYPE PRH_VAR_HB_N_ATTEMPT_WRITE2PIF; |
| 1180 |
#endif |
| 1181 |
|
| 1182 |
/* |
| 1183 |
* id : HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF |
| 1184 |
* type : <var> |
| 1185 |
* Waint time after a failed attempt on PIF write /RO |
| 1186 |
* location: 3 |
| 1187 |
*/ |
| 1188 |
|
| 1189 |
#ifdef PRH_DEFAULT_MODE |
| 1190 |
PRH_VAR_TYPE PRH_VAR_HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF=100; |
| 1191 |
#else |
| 1192 |
PRH_VAR_TYPE PRH_VAR_HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF; |
| 1193 |
#endif |
| 1194 |
|
| 1195 |
/* |
| 1196 |
* id : HB_WRITE2PIF_TIMEOUT |
| 1197 |
* type : <var> |
| 1198 |
* timeout time time to wait a sketchboard free in Write2PIF /RO |
| 1199 |
* location: 3 |
| 1200 |
*/ |
| 1201 |
|
| 1202 |
#ifdef PRH_DEFAULT_MODE |
| 1203 |
PRH_VAR_TYPE PRH_VAR_HB_WRITE2PIF_TIMEOUT=1000; |
| 1204 |
#else |
| 1205 |
PRH_VAR_TYPE PRH_VAR_HB_WRITE2PIF_TIMEOUT; |
| 1206 |
#endif |
| 1207 |
|
| 1208 |
/* |
| 1209 |
* id : HB_ALMOST_FULL |
| 1210 |
* type : <var> |
| 1211 |
* says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage. /RM |
| 1212 |
* location: 3 |
| 1213 |
*/ |
| 1214 |
|
| 1215 |
#ifdef PRH_DEFAULT_MODE |
| 1216 |
PRH_VAR_TYPE PRH_VAR_HB_ALMOST_FULL=80; |
| 1217 |
#else |
| 1218 |
PRH_VAR_TYPE PRH_VAR_HB_ALMOST_FULL; |
| 1219 |
#endif |
| 1220 |
|
| 1221 |
/* |
| 1222 |
* -------------- TMTC PArameters: --------------- |
| 1223 |
*/ |
| 1224 |
|
| 1225 |
|
| 1226 |
/* |
| 1227 |
* id : TM_FILTER_OPERATION |
| 1228 |
* type : <array>[78] |
| 1229 |
* low level telemetry filter operation: 0->apply no filter 1->set value 2->ORed mask 3->ANDed mask /RO |
| 1230 |
* location: 3 |
| 1231 |
*/ |
| 1232 |
|
| 1233 |
#ifdef PRH_DEFAULT_MODE |
| 1234 |
PRH_VAR_TYPE PRH_ARR_TM_FILTER_OPERATION[78]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; |
| 1235 |
#else |
| 1236 |
PRH_VAR_TYPE PRH_ARR_TM_FILTER_OPERATION[78]; |
| 1237 |
#endif |
| 1238 |
|
| 1239 |
|
| 1240 |
/* |
| 1241 |
* id : TM_FILTER_VALUE |
| 1242 |
* type : <array>[78] |
| 1243 |
* low level telemetry filted values /RO |
| 1244 |
* location: 3 |
| 1245 |
*/ |
| 1246 |
|
| 1247 |
#ifdef PRH_DEFAULT_MODE |
| 1248 |
PRH_VAR_TYPE PRH_ARR_TM_FILTER_VALUE[78]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; |
| 1249 |
#else |
| 1250 |
PRH_VAR_TYPE PRH_ARR_TM_FILTER_VALUE[78]; |
| 1251 |
#endif |
| 1252 |
|
| 1253 |
|
| 1254 |
/* |
| 1255 |
* id : TM_VRL_SUSPEND_HCL |
| 1256 |
* type : <var> |
| 1257 |
* wait time between two HCL commands for the VRL /RO |
| 1258 |
* location: 3 |
| 1259 |
*/ |
| 1260 |
|
| 1261 |
#ifdef PRH_DEFAULT_MODE |
| 1262 |
PRH_VAR_TYPE PRH_VAR_TM_VRL_SUSPEND_HCL=110; |
| 1263 |
#else |
| 1264 |
PRH_VAR_TYPE PRH_VAR_TM_VRL_SUSPEND_HCL; |
| 1265 |
#endif |
| 1266 |
|
| 1267 |
/* |
| 1268 |
* id : TM_VRL_SUSPEND_BEFORE_START |
| 1269 |
* type : <var> |
| 1270 |
* wait time before start VRL /RO |
| 1271 |
* location: 3 |
| 1272 |
*/ |
| 1273 |
|
| 1274 |
#ifdef PRH_DEFAULT_MODE |
| 1275 |
PRH_VAR_TYPE PRH_VAR_TM_VRL_SUSPEND_BEFORE_START=1; |
| 1276 |
#else |
| 1277 |
PRH_VAR_TYPE PRH_VAR_TM_VRL_SUSPEND_BEFORE_START; |
| 1278 |
#endif |
| 1279 |
|
| 1280 |
/* |
| 1281 |
* --------- IDAQ module Parameters : ------------- |
| 1282 |
*/ |
| 1283 |
|
| 1284 |
|
| 1285 |
/* |
| 1286 |
* id : DAQ_EVENT_RECEIVE_TIMEOUT |
| 1287 |
* type : <var> |
| 1288 |
* PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply /RO |
| 1289 |
* location: 3 |
| 1290 |
*/ |
| 1291 |
|
| 1292 |
#ifdef PRH_DEFAULT_MODE |
| 1293 |
PRH_VAR_TYPE PRH_VAR_DAQ_EVENT_RECEIVE_TIMEOUT=20000; |
| 1294 |
#else |
| 1295 |
PRH_VAR_TYPE PRH_VAR_DAQ_EVENT_RECEIVE_TIMEOUT; |
| 1296 |
#endif |
| 1297 |
|
| 1298 |
/* |
| 1299 |
* id : DAQ_WAITFREECMDIF_N |
| 1300 |
* type : <var> |
| 1301 |
* Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched /RO |
| 1302 |
* location: 3 |
| 1303 |
*/ |
| 1304 |
|
| 1305 |
#ifdef PRH_DEFAULT_MODE |
| 1306 |
PRH_VAR_TYPE PRH_VAR_DAQ_WAITFREECMDIF_N=4; |
| 1307 |
#else |
| 1308 |
PRH_VAR_TYPE PRH_VAR_DAQ_WAITFREECMDIF_N; |
| 1309 |
#endif |
| 1310 |
|
| 1311 |
/* |
| 1312 |
* --------- Trigger Board Parameters : ------------- |
| 1313 |
*/ |
| 1314 |
|
| 1315 |
|
| 1316 |
/* |
| 1317 |
* id : TRB_OK |
| 1318 |
* type : <var> |
| 1319 |
* Use ON_OFF tracker in ACQ /RO |
| 1320 |
* location: 3 |
| 1321 |
*/ |
| 1322 |
|
| 1323 |
#ifdef PRH_DEFAULT_MODE |
| 1324 |
PRH_VAR_TYPE PRH_VAR_TRB_OK=1; |
| 1325 |
#else |
| 1326 |
PRH_VAR_TYPE PRH_VAR_TRB_OK; |
| 1327 |
#endif |
| 1328 |
|
| 1329 |
/* |
| 1330 |
* id : TRIGGER_MODE_A |
| 1331 |
* type : <var> |
| 1332 |
* Trigger type for acq mode A /RO |
| 1333 |
* location: 3 |
| 1334 |
*/ |
| 1335 |
|
| 1336 |
#ifdef PRH_DEFAULT_MODE |
| 1337 |
PRH_VAR_TYPE PRH_VAR_TRIGGER_MODE_A=1; |
| 1338 |
#else |
| 1339 |
PRH_VAR_TYPE PRH_VAR_TRIGGER_MODE_A; |
| 1340 |
#endif |
| 1341 |
|
| 1342 |
/* |
| 1343 |
* id : TRIGGER_MODE_B |
| 1344 |
* type : <var> |
| 1345 |
* Trigger type for acq mode B /RO |
| 1346 |
* location: 3 |
| 1347 |
*/ |
| 1348 |
|
| 1349 |
#ifdef PRH_DEFAULT_MODE |
| 1350 |
PRH_VAR_TYPE PRH_VAR_TRIGGER_MODE_B=3; |
| 1351 |
#else |
| 1352 |
PRH_VAR_TYPE PRH_VAR_TRIGGER_MODE_B; |
| 1353 |
#endif |
| 1354 |
|
| 1355 |
/* |
| 1356 |
* id : TRIGGER_BUSY_CONTROL |
| 1357 |
* type : <var> |
| 1358 |
* Select the check mask of the busy alaarm /RO |
| 1359 |
* location: 3 |
| 1360 |
*/ |
| 1361 |
|
| 1362 |
#ifdef PRH_DEFAULT_MODE |
| 1363 |
PRH_VAR_TYPE PRH_VAR_TRIGGER_BUSY_CONTROL=0; |
| 1364 |
#else |
| 1365 |
PRH_VAR_TYPE PRH_VAR_TRIGGER_BUSY_CONTROL; |
| 1366 |
#endif |
| 1367 |
|
| 1368 |
/* |
| 1369 |
* id : TB_LINK |
| 1370 |
* type : <var> |
| 1371 |
* Trigger Board to use 1 or 2 /RO |
| 1372 |
* location: 2 |
| 1373 |
*/ |
| 1374 |
|
| 1375 |
#ifdef PRH_DEFAULT_MODE |
| 1376 |
PRH_VAR_TYPE PRH_VAR_TB_LINK=1; |
| 1377 |
#else |
| 1378 |
PRH_VAR_TYPE PRH_VAR_TB_LINK=1; |
| 1379 |
#endif |
| 1380 |
|
| 1381 |
/* |
| 1382 |
* id : TB_LINK_CUSTOM |
| 1383 |
* type : <var> |
| 1384 |
* Trigger Board CUSTOMto use 1 or 2 /RO |
| 1385 |
* location: 3 |
| 1386 |
*/ |
| 1387 |
|
| 1388 |
#ifdef PRH_DEFAULT_MODE |
| 1389 |
PRH_VAR_TYPE PRH_VAR_TB_LINK_CUSTOM=1; |
| 1390 |
#else |
| 1391 |
PRH_VAR_TYPE PRH_VAR_TB_LINK_CUSTOM; |
| 1392 |
#endif |
| 1393 |
|
| 1394 |
/* |
| 1395 |
* id : BUF_LEN_TB_SET_ALARM_MASK |
| 1396 |
* type : <var> |
| 1397 |
* TRG queue |
| 1398 |
* location: 3 |
| 1399 |
*/ |
| 1400 |
|
| 1401 |
#ifdef PRH_DEFAULT_MODE |
| 1402 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_ALARM_MASK=8; |
| 1403 |
#else |
| 1404 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_ALARM_MASK; |
| 1405 |
#endif |
| 1406 |
|
| 1407 |
/* |
| 1408 |
* id : BUF_TB_SET_ALARM_MASK |
| 1409 |
* type : <array>[2] |
| 1410 |
* TRG queue |
| 1411 |
* location: 3 |
| 1412 |
*/ |
| 1413 |
|
| 1414 |
#ifdef PRH_DEFAULT_MODE |
| 1415 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_ALARM_MASK[2]={0x20000283,0x64FFFF24}; |
| 1416 |
#else |
| 1417 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_ALARM_MASK[2]; |
| 1418 |
#endif |
| 1419 |
|
| 1420 |
|
| 1421 |
/* |
| 1422 |
* id : BUF_LEN_TB_SET_PMT_MASK |
| 1423 |
* type : <var> |
| 1424 |
* TRG queue |
| 1425 |
* location: 3 |
| 1426 |
*/ |
| 1427 |
|
| 1428 |
#ifdef PRH_DEFAULT_MODE |
| 1429 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_PMT_MASK=12; |
| 1430 |
#else |
| 1431 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_PMT_MASK; |
| 1432 |
#endif |
| 1433 |
|
| 1434 |
/* |
| 1435 |
* id : BUF_TB_SET_PMT_MASK |
| 1436 |
* type : <array>[3] |
| 1437 |
* TRG queue |
| 1438 |
* location: 3 |
| 1439 |
*/ |
| 1440 |
|
| 1441 |
#ifdef PRH_DEFAULT_MODE |
| 1442 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_PMT_MASK[3]={0x30000601,0xD0FFFFFF,0xFFFFFF48}; |
| 1443 |
#else |
| 1444 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_PMT_MASK[3]; |
| 1445 |
#endif |
| 1446 |
|
| 1447 |
|
| 1448 |
/* |
| 1449 |
* id : BUF_LEN_TB_SET_S4_CAL_MASK |
| 1450 |
* type : <var> |
| 1451 |
* TRG queue |
| 1452 |
* location: 3 |
| 1453 |
*/ |
| 1454 |
|
| 1455 |
#ifdef PRH_DEFAULT_MODE |
| 1456 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_S4_CAL_MASK=7; |
| 1457 |
#else |
| 1458 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_S4_CAL_MASK; |
| 1459 |
#endif |
| 1460 |
|
| 1461 |
/* |
| 1462 |
* id : BUF_TB_SET_S4_CAL_MASK |
| 1463 |
* type : <array>[2] |
| 1464 |
* TRG queue |
| 1465 |
* location: 3 |
| 1466 |
*/ |
| 1467 |
|
| 1468 |
#ifdef PRH_DEFAULT_MODE |
| 1469 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_S4_CAL_MASK[2]={0x20000181,0x55FFF300}; |
| 1470 |
#else |
| 1471 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_S4_CAL_MASK[2]; |
| 1472 |
#endif |
| 1473 |
|
| 1474 |
|
| 1475 |
/* |
| 1476 |
* id : BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT |
| 1477 |
* type : <var> |
| 1478 |
* |
| 1479 |
* location: 3 |
| 1480 |
*/ |
| 1481 |
|
| 1482 |
#ifdef PRH_DEFAULT_MODE |
| 1483 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT=9; |
| 1484 |
#else |
| 1485 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT; |
| 1486 |
#endif |
| 1487 |
|
| 1488 |
/* |
| 1489 |
* id : BUF_TB_SET_BUSY_MASK_IDAQ_HOT |
| 1490 |
* type : <array>[5] |
| 1491 |
* |
| 1492 |
* location: 3 |
| 1493 |
*/ |
| 1494 |
|
| 1495 |
#ifdef PRH_DEFAULT_MODE |
| 1496 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_HOT[5]={0x20000382,0x76800000,0x0B000000}; |
| 1497 |
#else |
| 1498 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_HOT[5]; |
| 1499 |
#endif |
| 1500 |
|
| 1501 |
|
| 1502 |
/* |
| 1503 |
* id : BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD |
| 1504 |
* type : <var> |
| 1505 |
* |
| 1506 |
* location: 3 |
| 1507 |
*/ |
| 1508 |
|
| 1509 |
#ifdef PRH_DEFAULT_MODE |
| 1510 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD=9; |
| 1511 |
#else |
| 1512 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD; |
| 1513 |
#endif |
| 1514 |
|
| 1515 |
/* |
| 1516 |
* id : BUF_TB_SET_BUSY_MASK_IDAQ_COLD |
| 1517 |
* type : <array>[5] |
| 1518 |
* |
| 1519 |
* location: 3 |
| 1520 |
*/ |
| 1521 |
|
| 1522 |
#ifdef PRH_DEFAULT_MODE |
| 1523 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_COLD[5]={0x20000382,0x76400000,0x86000000}; |
| 1524 |
#else |
| 1525 |
PRH_VAR_TYPE PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_COLD[5]; |
| 1526 |
#endif |
| 1527 |
|
| 1528 |
|
| 1529 |
/* |
| 1530 |
* --------- Traker Parameters : ------------- |
| 1531 |
*/ |
| 1532 |
|
| 1533 |
|
| 1534 |
/* |
| 1535 |
* id : TRK_OK |
| 1536 |
* type : <var> |
| 1537 |
* Use ON_OFF tracker in ACQ /RO |
| 1538 |
* location: 3 |
| 1539 |
*/ |
| 1540 |
|
| 1541 |
#ifdef PRH_DEFAULT_MODE |
| 1542 |
PRH_VAR_TYPE PRH_VAR_TRK_OK=1; |
| 1543 |
#else |
| 1544 |
PRH_VAR_TYPE PRH_VAR_TRK_OK; |
| 1545 |
#endif |
| 1546 |
|
| 1547 |
/* |
| 1548 |
* id : TRK_DSP_OK |
| 1549 |
* type : <table>[2][6] |
| 1550 |
* Tracker dsp ON_OFF in ACQ /RO |
| 1551 |
*/ |
| 1552 |
|
| 1553 |
|
| 1554 |
#ifdef PRH_DEFAULT_MODE |
| 1555 |
PRH_VAR_TYPE PRH_TAB_TRK_DSP_OK[2][6]={{1,1,1,1,1,1},{1,1,1,1,1,1}}; |
| 1556 |
#else |
| 1557 |
PRH_VAR_TYPE PRH_TAB_TRK_DSP_OK[2][6]; |
| 1558 |
#endif |
| 1559 |
|
| 1560 |
|
| 1561 |
|
| 1562 |
/* |
| 1563 |
* id : TRK_CALIB_MODE |
| 1564 |
* type : <var> |
| 1565 |
* Tracker calibration mode /RO |
| 1566 |
* location: 3 |
| 1567 |
*/ |
| 1568 |
|
| 1569 |
#ifdef PRH_DEFAULT_MODE |
| 1570 |
PRH_VAR_TYPE PRH_VAR_TRK_CALIB_MODE=1; |
| 1571 |
#else |
| 1572 |
PRH_VAR_TYPE PRH_VAR_TRK_CALIB_MODE; |
| 1573 |
#endif |
| 1574 |
|
| 1575 |
/* |
| 1576 |
* id : TRK_TIME_SHORT |
| 1577 |
* type : <var> |
| 1578 |
* Tracker wait loop for 128 loop /RO |
| 1579 |
* location: 3 |
| 1580 |
*/ |
| 1581 |
|
| 1582 |
#ifdef PRH_DEFAULT_MODE |
| 1583 |
PRH_VAR_TYPE PRH_VAR_TRK_TIME_SHORT=13; |
| 1584 |
#else |
| 1585 |
PRH_VAR_TYPE PRH_VAR_TRK_TIME_SHORT; |
| 1586 |
#endif |
| 1587 |
|
| 1588 |
/* |
| 1589 |
* id : TRK_TIME_LONG |
| 1590 |
* type : <var> |
| 1591 |
* Tracker wait loop for 8 loop /RO |
| 1592 |
* location: 3 |
| 1593 |
*/ |
| 1594 |
|
| 1595 |
#ifdef PRH_DEFAULT_MODE |
| 1596 |
PRH_VAR_TYPE PRH_VAR_TRK_TIME_LONG=0; |
| 1597 |
#else |
| 1598 |
PRH_VAR_TYPE PRH_VAR_TRK_TIME_LONG; |
| 1599 |
#endif |
| 1600 |
|
| 1601 |
/* |
| 1602 |
* id : TRK_DSP_MASK |
| 1603 |
* type : <table>[2][6] |
| 1604 |
* Traker dsp mask /RO |
| 1605 |
*/ |
| 1606 |
|
| 1607 |
|
| 1608 |
#ifdef PRH_DEFAULT_MODE |
| 1609 |
PRH_VAR_TYPE PRH_TAB_TRK_DSP_MASK[2][6]={{0,0,0,0,0,0},{0,0,0,0,0,0}}; |
| 1610 |
#else |
| 1611 |
PRH_VAR_TYPE PRH_TAB_TRK_DSP_MASK[2][6]; |
| 1612 |
#endif |
| 1613 |
|
| 1614 |
|
| 1615 |
|
| 1616 |
/* |
| 1617 |
* id : TRK_LOAD_PRG |
| 1618 |
* type : <array>[2] |
| 1619 |
* The way the DSP program is loaded /RO |
| 1620 |
* location: 3 |
| 1621 |
*/ |
| 1622 |
|
| 1623 |
#ifdef PRH_DEFAULT_MODE |
| 1624 |
PRH_VAR_TYPE PRH_ARR_TRK_LOAD_PRG[2]={3,3}; |
| 1625 |
#else |
| 1626 |
PRH_VAR_TYPE PRH_ARR_TRK_LOAD_PRG[2]; |
| 1627 |
#endif |
| 1628 |
|
| 1629 |
|
| 1630 |
/* |
| 1631 |
* id : TRK_CALIB_INIT |
| 1632 |
* type : <var> |
| 1633 |
* modality of calibration /RO |
| 1634 |
* location: 3 |
| 1635 |
*/ |
| 1636 |
|
| 1637 |
#ifdef PRH_DEFAULT_MODE |
| 1638 |
PRH_VAR_TYPE PRH_VAR_TRK_CALIB_INIT=104; |
| 1639 |
#else |
| 1640 |
PRH_VAR_TYPE PRH_VAR_TRK_CALIB_INIT; |
| 1641 |
#endif |
| 1642 |
|
| 1643 |
/* |
| 1644 |
* id : TRK_NLOOP |
| 1645 |
* type : <var> |
| 1646 |
* macro loop number /RO |
| 1647 |
* location: 3 |
| 1648 |
*/ |
| 1649 |
|
| 1650 |
#ifdef PRH_DEFAULT_MODE |
| 1651 |
PRH_VAR_TYPE PRH_VAR_TRK_NLOOP=12; |
| 1652 |
#else |
| 1653 |
PRH_VAR_TYPE PRH_VAR_TRK_NLOOP; |
| 1654 |
#endif |
| 1655 |
|
| 1656 |
/* |
| 1657 |
* id : TRK_PED_MIN_0 |
| 1658 |
* type : <table>[3][6] |
| 1659 |
* Tracker 0 ped min value /RO |
| 1660 |
*/ |
| 1661 |
|
| 1662 |
|
| 1663 |
#ifdef PRH_DEFAULT_MODE |
| 1664 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MIN_0[3][6]={{100,100,100,100,100,100},{100,100,100,100,100,100},{100,100,100,100,100,100}}; |
| 1665 |
#else |
| 1666 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MIN_0[3][6]; |
| 1667 |
#endif |
| 1668 |
|
| 1669 |
|
| 1670 |
|
| 1671 |
/* |
| 1672 |
* id : TRK_PED_MIN_1 |
| 1673 |
* type : <table>[3][6] |
| 1674 |
* Tracker 1 ped min value /RO |
| 1675 |
*/ |
| 1676 |
|
| 1677 |
|
| 1678 |
#ifdef PRH_DEFAULT_MODE |
| 1679 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MIN_1[3][6]={{100,100,100,100,100,100},{100,100,100,100,100,100},{100,100,100,100,100,100}}; |
| 1680 |
#else |
| 1681 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MIN_1[3][6]; |
| 1682 |
#endif |
| 1683 |
|
| 1684 |
|
| 1685 |
|
| 1686 |
/* |
| 1687 |
* id : TRK_PED_MAX_0 |
| 1688 |
* type : <table>[3][6] |
| 1689 |
* Tracker 0 ped max value /RO |
| 1690 |
*/ |
| 1691 |
|
| 1692 |
|
| 1693 |
#ifdef PRH_DEFAULT_MODE |
| 1694 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MAX_0[3][6]={{4000,4000,4000,4000,4000,4000},{4000,4000,4000,4000,4000,4000},{4000,4000,4000,4000,4000,4000}}; |
| 1695 |
#else |
| 1696 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MAX_0[3][6]; |
| 1697 |
#endif |
| 1698 |
|
| 1699 |
|
| 1700 |
|
| 1701 |
/* |
| 1702 |
* id : TRK_PED_MAX_1 |
| 1703 |
* type : <table>[3][6] |
| 1704 |
* Tracker 1 ped max value /RO |
| 1705 |
*/ |
| 1706 |
|
| 1707 |
|
| 1708 |
#ifdef PRH_DEFAULT_MODE |
| 1709 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MAX_1[3][6]={{4000,4000,4000,4000,4000,4000},{4000,4000,4000,4000,4000,4000},{4000,4000,4000,4000,4000,4000}}; |
| 1710 |
#else |
| 1711 |
PRH_VAR_TYPE PRH_TAB_TRK_PED_MAX_1[3][6]; |
| 1712 |
#endif |
| 1713 |
|
| 1714 |
|
| 1715 |
|
| 1716 |
/* |
| 1717 |
* id : TRK_SIG_MIN_0 |
| 1718 |
* type : <table>[3][6] |
| 1719 |
* Tracker 0 sig min value /RO |
| 1720 |
*/ |
| 1721 |
|
| 1722 |
|
| 1723 |
#ifdef PRH_DEFAULT_MODE |
| 1724 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MIN_0[3][6]={{1,1,1,1,1,1},{1,1,1,1,1,1},{1,1,1,1,1,1}}; |
| 1725 |
#else |
| 1726 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MIN_0[3][6]; |
| 1727 |
#endif |
| 1728 |
|
| 1729 |
|
| 1730 |
|
| 1731 |
/* |
| 1732 |
* id : TRK_SIG_MIN_1 |
| 1733 |
* type : <table>[3][6] |
| 1734 |
* Tracker 1 sig min value /RO |
| 1735 |
*/ |
| 1736 |
|
| 1737 |
|
| 1738 |
#ifdef PRH_DEFAULT_MODE |
| 1739 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MIN_1[3][6]={{1,1,1,1,1,1},{1,1,1,1,1,1},{1,1,1,1,1,1}}; |
| 1740 |
#else |
| 1741 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MIN_1[3][6]; |
| 1742 |
#endif |
| 1743 |
|
| 1744 |
|
| 1745 |
|
| 1746 |
/* |
| 1747 |
* id : TRK_SIG_MAX_0 |
| 1748 |
* type : <table>[3][6] |
| 1749 |
* Tracker 0 sig min value /RO |
| 1750 |
*/ |
| 1751 |
|
| 1752 |
|
| 1753 |
#ifdef PRH_DEFAULT_MODE |
| 1754 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MAX_0[3][6]={{100,100,100,100,100,100},{100,100,100,100,100,100},{100,100,100,100,100,100}}; |
| 1755 |
#else |
| 1756 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MAX_0[3][6]; |
| 1757 |
#endif |
| 1758 |
|
| 1759 |
|
| 1760 |
|
| 1761 |
/* |
| 1762 |
* id : TRK_SIG_MAX_1 |
| 1763 |
* type : <table>[3][6] |
| 1764 |
* Tracker 1 sig min value /RO |
| 1765 |
*/ |
| 1766 |
|
| 1767 |
|
| 1768 |
#ifdef PRH_DEFAULT_MODE |
| 1769 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MAX_1[3][6]={{100,100,100,100,100,100},{100,100,100,100,100,100},{100,100,100,100,100,100}}; |
| 1770 |
#else |
| 1771 |
PRH_VAR_TYPE PRH_TAB_TRK_SIG_MAX_1[3][6]; |
| 1772 |
#endif |
| 1773 |
|
| 1774 |
|
| 1775 |
|
| 1776 |
/* |
| 1777 |
* id : TRK_BAD_MAX_0 |
| 1778 |
* type : <table>[3][6] |
| 1779 |
* Tracker 0 bad max value /RO |
| 1780 |
*/ |
| 1781 |
|
| 1782 |
|
| 1783 |
#ifdef PRH_DEFAULT_MODE |
| 1784 |
PRH_VAR_TYPE PRH_TAB_TRK_BAD_MAX_0[3][6]={{512,512,512,512,512,512},{512,512,512,512,512,512},{512,512,512,512,512,512}}; |
| 1785 |
#else |
| 1786 |
PRH_VAR_TYPE PRH_TAB_TRK_BAD_MAX_0[3][6]; |
| 1787 |
#endif |
| 1788 |
|
| 1789 |
|
| 1790 |
|
| 1791 |
/* |
| 1792 |
* id : TRK_BAD_MAX_1 |
| 1793 |
* type : <table>[3][6] |
| 1794 |
* Tracker 1 bad max value /RO |
| 1795 |
*/ |
| 1796 |
|
| 1797 |
|
| 1798 |
#ifdef PRH_DEFAULT_MODE |
| 1799 |
PRH_VAR_TYPE PRH_TAB_TRK_BAD_MAX_1[3][6]={{512,512,512,512,512,512},{512,512,512,512,512,512},{512,512,512,512,512,512}}; |
| 1800 |
#else |
| 1801 |
PRH_VAR_TYPE PRH_TAB_TRK_BAD_MAX_1[3][6]; |
| 1802 |
#endif |
| 1803 |
|
| 1804 |
|
| 1805 |
|
| 1806 |
/* |
| 1807 |
* id : BUF_LEN_TRK_PROGRAM |
| 1808 |
* type : <var> |
| 1809 |
* TRK DSP Program /RO |
| 1810 |
* location: 1 |
| 1811 |
*/ |
| 1812 |
|
| 1813 |
#ifdef PRH_DEFAULT_MODE |
| 1814 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_PROGRAM=10644; |
| 1815 |
#else |
| 1816 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_PROGRAM; |
| 1817 |
#endif |
| 1818 |
|
| 1819 |
/* |
| 1820 |
* id : BUF_TRK_PROGRAM |
| 1821 |
* type : <array>[3000] |
| 1822 |
* TRK DSP Program /RO |
| 1823 |
* location: 1 |
| 1824 |
*/ |
| 1825 |
|
| 1826 |
#ifdef PRH_DEFAULT_MODE |
| 1827 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_PROGRAM[3000]={0x0000010A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x186C3F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x18CF9F0A,0x001F0A00,0x1F0A001F,0x0A001F0A,0x001F0A00,0x1F0A001F,0x00000002,0x008F4000,0x0A93301A,0x02030F02,0x0C0F0400,0x403C0003,0x3C000C3C,0x00043C01,0x0141C000,0x93FFF040,0x000093FF,0xE093FFD0,0x93FFC093,0xFFB093FF,0xA093FF90,0x93FF8093,0xFF7093FF,0x5093FF30,0x93FF1093,0xFEF044C0,0xF093FF20,0x400FF093,0xFFE044C0,0xF093FF60,0x40000A93,0xFE7A4000,0x0A0D048A,0x0D049A0D,0x04AA0D04,0xBA0D088A,0x0D089A0D,0x08AA0D08,0xBA340004,0x34001534,0x00263400,0x37380004,0x38001538,0x40063800,0x370D000A,0x0D001A0D,0x004A0D00,0x5A20980F,0x0D006A0D,0x007A0D00,0x2A0D003A,0x0D00EA0D,0x00FA0D00,0x9A0D008A,0x0D0C6A40,0x004A9330,0x3A40007A,0x93304A40,0x002A9330,0x5A40005A,0x9330BA40,0x007A9330,0xEA40007A,0x9330CA40,0x001A9330,0x2A40000A,0x93306A40,0x080A9330,0x7A4FFFFA,0x9330DA40,0xC04A9330,0x8A40960A,0x93309A41,0xEA3A9330,0xFA4000AA,0x9330AA40,0x000A93FD,0xFA9333CA,0x93331A93,0x332A9333,0x3A93334A,0x9333EA93,0x340A9334,0x2A9333DA,0x9333FA93,0x341A9334,0x7A93301A,0x9339EA93,0x3B1A9339,0xCA420004,0x412FD022,0x600F22E2,0x1F22E21F,0x22E21F93,0x3A0A0000,0x001CD2CF,0x00000000,0x00000204,0x0F83301A,0x227A0F18,0x0DD09339,0xDA8339DA,0x238A1F18,0x0B701C0E,0x1F8339DA,0x238A3F23,0x82BF9330,0x1A000000,0x8339DA23,0x82DF180D,0xC03C0103,0x3C010C02,0x00CF0000,0x00000000,0x04006000,0x00000280,0x00000000,0x83332522,0x280F9333,0x2A833310,0x22580F93,0x331A0000,0x0083303A,0x93335A83,0x39DA2382,0xDF180DC0,0x8339DA40,0x00342382,0x0F180D91,0x83302183,0x332523C9,0x0F23821F,0x23A25F93,0x39FA1C6D,0x1F000000,0x00000000,0x0000180A,0x9F000000,0x0A000F00,0x00008333,0x4522280F,0x93334A83,0x33302258,0x0F93333A,0x40000A37,0x38C13C01,0x05140EDE,0x6800A500,0x00001CB4,0xBF40000A,0x933B0A40,0x0FFA93FF,0xBA8330FA,0x93FFDA40,0x000A3735,0xB13736B2,0x3737B33C,0x0105140F,0xEE6800A5,0x6800A968,0x00AD0000,0x0034000F,0x1C1C5F1C,0x1DAF1C1E,0x5F34004F,0x1C1C5F1C,0x1DAF1C1E,0x5F34005F,0x1C1C5F1C,0x1DAF1C1E,0x5F40080A,0x0D0C5A14,0x138E3C01,0x033C010C,0x0200CF00,0x00000000,0x00040060,0x00000002,0x80000000,0x00000000,0x00000083,0x39DA2382,0x9F181250,0x83332522,0x280F9333,0x2A833310,0x22580F93,0x331A4000,0x1A9339FA,0x1C6D1F00,0x00001CBC,0xDF34000F,0x373DF043,0x35BA9335,0x8A1C32DF,0x34004F37,0x3DF00900,0x014336BA,0x93358A1C,0x32DF3400,0x5F373DF0,0x09000243,0x37BA9335,0x8A1C32DF,0x00000034,0x000F1C1E,0xEF34004F,0x1C1EEF34,0x005F1C1E,0xEF34000F,0x1C37EF34,0x004F1C37,0xEF34005F,0x1C37EF34,0x000F1C4F,0x6F34004F,0x1C4F6F34,0x005F1C4F,0x6F8F30E5,0x141AAE34,0x000F1C1C,0x5F34004F,0x1C1C5F34,0x005F1C1C,0x5F40080A,0x0D0C5A14,0x197E3C01,0x033C010C,0x0200CF00,0x00000000,0x00040060,0x00000002,0x80000000,0x00000000,0x00000083,0x39DA2382,0x9F1816D0,0x83332522,0x280F9333,0x2A833310,0x22580F93,0x331A4000,0x1A9339FA,0x1C6D1F00,0x00001CBC,0xDF34000F,0x1C1E5F34,0x004F1C1E,0x5F34005F,0x1C1E5F34,0x000F373D,0xF04335BA,0x93358A1C,0x560F3400,0x4F373DF0,0x09000143,0x36BA9335,0x8A1C560F,0x34005F37,0x3DF00900,0x024337BA,0x93358A1C,0x560F3400,0x0F373DF0,0x4335BA93,0x358A1C32,0xDF34004F,0x373DF009,0x00014336,0xBA93358A,0x1C32DF34,0x005F373D,0xF0090002,0x4337BA93,0x358A1C32,0xDF000000,0x34000F1C,0x1EEF3400,0x4F1C1EEF,0x34005F1C,0x1EEF3400,0x0F1C37EF,0x34004F1C,0x37EF3400,0x5F1C37EF,0x34000F1C,0x4F6F3400,0x4F1C4F6F,0x34005F1C,0x4F6F0000,0x0034000F,0x3480011C,0xB16F4180,0x7A6800A5,0x34004F34,0x80011CB1,0x6F41808A,0x6800A534,0x005F3480,0x011CB16F,0x41809A68,0x00A51CCD,0xCF34000F,0x1C6B1F34,0x004F1C6B,0x1F34005F,0x1C6B1F1C,0xD35F1CC5,0x7F000000,0x0A000F00,0x00003480,0x0134C002,0x35000339,0x40003980,0x0139C002,0x3C400514,0x1D8E4000,0x0A6800A5,0x6800A968,0x00AD7800,0xA17800A5,0x7000A84C,0x00042382,0x0F7800A9,0x0000000A,0x000F0000,0x0040000A,0x93354A39,0xC0023C40,0x05141E3E,0x7000A823,0x9AFF7800,0xA9000000,0x0A000F00,0x000039C0,0x023C4005,0x141ECE70,0x00A8239A,0xBF7800A9,0x0000000A,0x000F0000,0x00348001,0x34C00235,0x00033940,0x00398001,0x39C00234,0x00003840,0x033C4005,0x1432BE70,0x00A82718,0x9F23920F,0x1820224F,0xFFFA7800,0xAC40000A,0x6800A018,0x322F0000,0x006000C8,0x6000B40F,0x14F10F1B,0x010F0C01,0x0D00CF0D,0x00BE4000,0x007000A8,0x27189F23,0x920F0D00,0x4A3C01F5,0x14223E0D,0x00A00F02,0x010F1C01,0x0D000F0F,0x04010F1B,0x010D00CF,0x0D00BE22,0xE00F1821,0xE523833F,0x0D00BA18,0x222F0000,0x000D000A,0x23A31F0D,0x00BA0000,0x00000000,0x239CDF18,0x22B04FFF,0xFA7800AC,0x40000A68,0x00A01832,0x2F000000,0x0F13FC0F,0x0CFC6800,0xE06000BC,0x7000C070,0x00840F14,0xF10F1801,0x0D00AF0D,0x008E0F04,0x010F1B01,0x0F1AF10D,0x00CF0D00,0xBE400000,0x7000A827,0x189F2392,0x0F0D004A,0x3C02F514,0x256E0D00,0xA00F0201,0x0F18010D,0x000F0F1C,0xF10D008E,0x0F04010F,0x1B010D00,0xCF0D00BE,0x22E00F18,0x25152383,0x3F0D00BA,0x18255F00,0x00000D00,0x0A23A31F,0x0D00BA00,0x00000000,0x00780084,0x7800C068,0x00BC60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,0x0523AA0F,0x6800A141,0x8C3A93FD,0xFA83FDF8,0x0F10F641,0x400523AE,0x0F6800A1,0x83FDFA40,0x3FF42382,0x0F23AA0F,0x6800A183,0x334A403F,0xF423820F,0x23AA0F68,0x00A14140,0x05833B04,0x22200F93,0x3B0A403F,0xF423820F,0x23AA0F68,0x00A14000,0x0A23AA0F,0x3C009514,0xBF3E6800,0xA1000000,0x40000A23,0xAA0F23B2,0x1F23B25F,0x6800A141,0xFFF56800,0x513738C0,0x36000160,0x00810F10,0x030D000E,0x6000810F,0x10060D00,0x4F23A00F,0x6800A50D,0x000E6000,0x810F1009,0x0D004F23,0xA00F6800,0xA50D000E,0x6000810F,0x100C0D00,0x4F23A00F,0x6800A50D,0x000E6000,0x810F100F,0x0D004F23,0xA00F6800,0xA50D000E,0x6000810F,0x10020D00,0x4E23A00F,0x0D000A60,0x00810F10,0x050D004F,0x23A00F68,0x00A50D00,0x0E600081,0x0F10080D,0x004F23A0,0x0F6800A5,0x0D000E60,0x00810F10,0x0B0D004F,0x23A00F68,0x00A50D00,0x0E600081,0x0F100E0D,0x004F23A0,0x0F6800A5,0x0D000E60,0x00810F10,0x010D004E,0x23A00F0D,0x000A6000,0x810F1004,0x0D004F23,0xA00F6800,0xA50D000E,0x6000810F,0x10070D00,0x4F23A00F,0x6800A50D,0x000E6000,0x810F100A,0x0D004F23,0xA00F6800,0xA50D000E,0x6000810F,0x100D0D00,0x4F23A00F,0x6800A50D,0x000E6000,0x4123A00F,0x6800A500,0x00000A00,0x0F000000,0x3738C03C,0x005514C5,0xCE090001,0x00000041,0x4005833A,0x2A23AA0F,0x6800A183,0x3A3A23AA,0x0F6800A1,0x833A4A23,0xAA0F6800,0xA1833A5A,0x23AA0F68,0x00A1833A,0x6A23AA0F,0x6800A183,0x3A6A23AA,0x0F6800A1,0x833A8A23,0xAA0F6800,0xA1833A9A,0x23AA0F68,0x00A1833A,0xAA23AA0F,0x6800A183,0x33C46000,0xA023A20F,0x23923F23,0x927F6800,0xA1090001,0x3738C036,0x00016000,0x810F1003,0x0D000E60,0x00810F10,0x060D004F,0x23A00F68,0x00A50D00,0x0E600081,0x0F10090D,0x004F23A0,0x0F6800A5,0x0D000E60,0x00810F10,0x0C0D004F,0x23A00F68,0x00A50D00,0x0E600081,0x0F100F0D,0x004F23A0,0x0F6800A5,0x0D000E60,0x00810F10,0x020D004E,0x23A00F0D,0x000A6000,0x810F1005,0x0D004F23,0xA00F6800,0xA50D000E,0x6000810F,0x10080D00,0x4F23A00F,0x6800A50D,0x000E6000,0x810F100B,0x0D004F23,0xA00F6800,0xA50D000E,0x6000810F,0x100E0D00,0x4F23A00F,0x6800A50D,0x000E6000,0x810F1001,0x0D004E23,0xA00F0D00,0x0A600081,0x0F10040D,0x004F23A0,0x0F6800A5,0x0D000E60,0x00810F10,0x070D004F,0x23A00F68,0x00A50D00,0x0E600081,0x0F100A0D,0x004F23A0,0x0F6800A5,0x0D000E60,0x00810F10,0x0D0D004F,0x23A00F68,0x00A50D00,0x0E600041,0x23A00F68,0x00A50000,0x000A000F,0x00000040,0x000A3400,0x0F348000,0x3C841514,0xCE3E6000,0x4123C20F,0x34004F34,0x80003C84,0x1514CE9E,0x60004123,0xC20F3400,0x5F348000,0x3C841514,0xCEFE6000,0x4123C20F,0x0D008A0F,0x10F80D00,0x4E400FF5,0x238A0F23,0xC20F9333,0xCA000000,0x0A000F02,0x008F0400,0x40000000,0x0D03A223,0x8A9F18D0,0x31040008,0x0D03A223,0x8A9F18CF,0xF0000000,0x0D03A223,0x829F18D0,0xB1040004,0x0D03A223,0x829F18D0,0x70000000,0x0D03A223,0x821F18D1,0x31040010,0x0D03A223,0x821F18D0,0xF0000000,0x40001A0D,0x0CFA0000,0x00833A1A,0x0D0CFA00,0x00000400,0x03000000,0x3C000304,0x00020000,0x004000DA,0x93FDFA83,0x39C023B8,0x9F9339CA,0x1C940F18,0xD26F0000,0x00833B15,0x22280F93,0x3B1A0000,0x000A001F,0x00000000,0x00000D03,0xAF000000,0x933A1A0D,0x0CFA0000,0x00000000,0x0A000F00,0x00003400,0x0F340000,0x40000A26,0x7A0F3C40,0x0514D3EE,0x60000126,0x700F225A,0x0F000000,0x0D008A22,0x100F0F12,0xF40F08F4,0x933A2E34,0x004F3400,0x0040000A,0x267A0F3C,0x400514D4,0xDE600001,0x26700F22,0x5A0F0000,0x000D008A,0x22100F0F,0x12F40F08,0xF4933A3E,0x34005F34,0x00004000,0x0A267A0F,0x3C400514,0xD5CE6000,0x0126700F,0x225A0F00,0x00000D00,0x8A22100F,0x0F12F40F,0x08F4933A,0x4E34000F,0x34400040,0x000A267A,0x0F3C4005,0x14D6BE60,0x00012670,0x0F225A0F,0x0000000D,0x008A2210,0x0F0F12F6,0x0F08F693,0x3A5E0F16,0xF6227E0F,0x18D77040,0x3FFA933A,0x5A000000,0x34004F34,0x40004000,0x0A267A0F,0x3C400514,0xD80E6000,0x0126700F,0x225A0F00,0x00000D00,0x8A22100F,0x0F12F60F,0x08F6933A,0x6E0F16F6,0x227E0F18,0xD8C0403F,0xFA933A6A,0x00000034,0x005F3440,0x0040000A,0x267A0F3C,0x400514D9,0x5E600001,0x26700F22,0x5A0F0000,0x000D008A,0x22100F0F,0x12F60F08,0xF6933A6E,0x0F16F622,0x7E0F18DA,0x10403FFA,0x933A7A00,0x00003400,0x0F35C000,0x48000440,0x000A267A,0x0F3C4005,0x14DACE60,0x00012380,0x0F0F12F1,0x26760F22,0x100F933A,0x8A0F12F6,0x227E0F18,0xDB40403F,0xFA933A8A,0x00000034,0x004F35C0,0x00480004,0x40000A26,0x7A0F3C40,0x0514DBFE,0x60000123,0x800F0F12,0xF126760F,0x22100F93,0x3A9A0F12,0xF6227E0F,0x18DC7040,0x3FFA933A,0x9A000000,0x34005F35,0xC0004800,0x0440000A,0x267A0F3C,0x400514DD,0x2E600001,0x23800F0F,0x12F12676,0x0F22100F,0x933AAA0F,0x12F6227E,0x0F18DDA0,0x403FFA93,0x3AAA0000,0x000A000F}; |
| 1828 |
#else |
| 1829 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_PROGRAM[3000]; |
| 1830 |
#endif |
| 1831 |
|
| 1832 |
|
| 1833 |
/* |
| 1834 |
* id : BUF_LEN_TRK_TRAILER_PRG_0 |
| 1835 |
* type : <var> |
| 1836 |
* TRK DSP Program Trailer for DSP 0 /RO |
| 1837 |
* location: 3 |
| 1838 |
*/ |
| 1839 |
|
| 1840 |
#ifdef PRH_DEFAULT_MODE |
| 1841 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_0=1; |
| 1842 |
#else |
| 1843 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_0; |
| 1844 |
#endif |
| 1845 |
|
| 1846 |
/* |
| 1847 |
* id : BUF_TRK_TRAILER_PRG_0 |
| 1848 |
* type : <array>[3] |
| 1849 |
* TRK DSP Program Trailer for DSP 0 /RO |
| 1850 |
* location: 3 |
| 1851 |
*/ |
| 1852 |
|
| 1853 |
#ifdef PRH_DEFAULT_MODE |
| 1854 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_0[3]={0x79000000}; |
| 1855 |
#else |
| 1856 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_0[3]; |
| 1857 |
#endif |
| 1858 |
|
| 1859 |
|
| 1860 |
/* |
| 1861 |
* id : BUF_LEN_TRK_TRAILER_PRG_1 |
| 1862 |
* type : <var> |
| 1863 |
* TRK DSP Program Trailer for DSP 1 /RO |
| 1864 |
* location: 3 |
| 1865 |
*/ |
| 1866 |
|
| 1867 |
#ifdef PRH_DEFAULT_MODE |
| 1868 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_1=1; |
| 1869 |
#else |
| 1870 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_1; |
| 1871 |
#endif |
| 1872 |
|
| 1873 |
/* |
| 1874 |
* id : BUF_TRK_TRAILER_PRG_1 |
| 1875 |
* type : <array>[3] |
| 1876 |
* TRK DSP Program Trailer for DSP 1 /RO |
| 1877 |
* location: 3 |
| 1878 |
*/ |
| 1879 |
|
| 1880 |
#ifdef PRH_DEFAULT_MODE |
| 1881 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_1[3]={0x9A000000}; |
| 1882 |
#else |
| 1883 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_1[3]; |
| 1884 |
#endif |
| 1885 |
|
| 1886 |
|
| 1887 |
/* |
| 1888 |
* id : BUF_LEN_TRK_TRAILER_PRG_2 |
| 1889 |
* type : <var> |
| 1890 |
* TRK DSP Program Trailer for DSP 2 /RO |
| 1891 |
* location: 3 |
| 1892 |
*/ |
| 1893 |
|
| 1894 |
#ifdef PRH_DEFAULT_MODE |
| 1895 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_2=1; |
| 1896 |
#else |
| 1897 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_2; |
| 1898 |
#endif |
| 1899 |
|
| 1900 |
/* |
| 1901 |
* id : BUF_TRK_TRAILER_PRG_2 |
| 1902 |
* type : <array>[3] |
| 1903 |
* TRK DSP Program Trailer for DSP 2 /RO |
| 1904 |
* location: 3 |
| 1905 |
*/ |
| 1906 |
|
| 1907 |
#ifdef PRH_DEFAULT_MODE |
| 1908 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_2[3]={0xB8000000}; |
| 1909 |
#else |
| 1910 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_2[3]; |
| 1911 |
#endif |
| 1912 |
|
| 1913 |
|
| 1914 |
/* |
| 1915 |
* id : BUF_LEN_TRK_TRAILER_PRG_3 |
| 1916 |
* type : <var> |
| 1917 |
* TRK DSP Program Trailer for DSP 3 /RO |
| 1918 |
* location: 3 |
| 1919 |
*/ |
| 1920 |
|
| 1921 |
#ifdef PRH_DEFAULT_MODE |
| 1922 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_3=1; |
| 1923 |
#else |
| 1924 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_3; |
| 1925 |
#endif |
| 1926 |
|
| 1927 |
/* |
| 1928 |
* id : BUF_TRK_TRAILER_PRG_3 |
| 1929 |
* type : <array>[3] |
| 1930 |
* TRK DSP Program Trailer for DSP 3 /RO |
| 1931 |
* location: 3 |
| 1932 |
*/ |
| 1933 |
|
| 1934 |
#ifdef PRH_DEFAULT_MODE |
| 1935 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_3[3]={0x5B000000}; |
| 1936 |
#else |
| 1937 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_3[3]; |
| 1938 |
#endif |
| 1939 |
|
| 1940 |
|
| 1941 |
/* |
| 1942 |
* id : BUF_LEN_TRK_TRAILER_PRG_4 |
| 1943 |
* type : <var> |
| 1944 |
* TRK DSP Program Trailer for DSP 4 /RO |
| 1945 |
* location: 3 |
| 1946 |
*/ |
| 1947 |
|
| 1948 |
#ifdef PRH_DEFAULT_MODE |
| 1949 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_4=1; |
| 1950 |
#else |
| 1951 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_4; |
| 1952 |
#endif |
| 1953 |
|
| 1954 |
/* |
| 1955 |
* id : BUF_TRK_TRAILER_PRG_4 |
| 1956 |
* type : <array>[3] |
| 1957 |
* TRK DSP Program Trailer for DSP 4 /RO |
| 1958 |
* location: 3 |
| 1959 |
*/ |
| 1960 |
|
| 1961 |
#ifdef PRH_DEFAULT_MODE |
| 1962 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_4[3]={0xFC000000}; |
| 1963 |
#else |
| 1964 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_4[3]; |
| 1965 |
#endif |
| 1966 |
|
| 1967 |
|
| 1968 |
/* |
| 1969 |
* id : BUF_LEN_TRK_TRAILER_PRG_5 |
| 1970 |
* type : <var> |
| 1971 |
* TRK DSP Program Trailer for DSP 5 /RO |
| 1972 |
* location: 3 |
| 1973 |
*/ |
| 1974 |
|
| 1975 |
#ifdef PRH_DEFAULT_MODE |
| 1976 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_5=1; |
| 1977 |
#else |
| 1978 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_5; |
| 1979 |
#endif |
| 1980 |
|
| 1981 |
/* |
| 1982 |
* id : BUF_TRK_TRAILER_PRG_5 |
| 1983 |
* type : <array>[3] |
| 1984 |
* TRK DSP Program Trailer for DSP 5 /RO |
| 1985 |
* location: 3 |
| 1986 |
*/ |
| 1987 |
|
| 1988 |
#ifdef PRH_DEFAULT_MODE |
| 1989 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_5[3]={0x1F000000}; |
| 1990 |
#else |
| 1991 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_TRAILER_PRG_5[3]; |
| 1992 |
#endif |
| 1993 |
|
| 1994 |
|
| 1995 |
/* |
| 1996 |
* id : BUF_LEN_TRK_NUMBER_DSP_1_0 |
| 1997 |
* type : <var> |
| 1998 |
* TRK command queue /RO |
| 1999 |
* location: 3 |
| 2000 |
*/ |
| 2001 |
|
| 2002 |
#ifdef PRH_DEFAULT_MODE |
| 2003 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_0=30; |
| 2004 |
#else |
| 2005 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_0; |
| 2006 |
#endif |
| 2007 |
|
| 2008 |
/* |
| 2009 |
* id : BUF_TRK_NUMBER_DSP_1_0 |
| 2010 |
* type : <array>[10] |
| 2011 |
* TRK command queue /RO |
| 2012 |
* location: 3 |
| 2013 |
*/ |
| 2014 |
|
| 2015 |
#ifdef PRH_DEFAULT_MODE |
| 2016 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_0[10]={0x001B01C7,0x00730200,0x0C000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07940000}; |
| 2017 |
#else |
| 2018 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_0[10]; |
| 2019 |
#endif |
| 2020 |
|
| 2021 |
|
| 2022 |
/* |
| 2023 |
* id : BUF_LEN_TRK_NUMBER_DSP_1_1 |
| 2024 |
* type : <var> |
| 2025 |
* TRK command queue /RO |
| 2026 |
* location: 3 |
| 2027 |
*/ |
| 2028 |
|
| 2029 |
#ifdef PRH_DEFAULT_MODE |
| 2030 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_1=30; |
| 2031 |
#else |
| 2032 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_1; |
| 2033 |
#endif |
| 2034 |
|
| 2035 |
/* |
| 2036 |
* id : BUF_TRK_NUMBER_DSP_1_1 |
| 2037 |
* type : <array>[10] |
| 2038 |
* TRK command queue /RO |
| 2039 |
* location: 3 |
| 2040 |
*/ |
| 2041 |
|
| 2042 |
#ifdef PRH_DEFAULT_MODE |
| 2043 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_1[10]={0x001B11B7,0x00730200,0x0A000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07210000}; |
| 2044 |
#else |
| 2045 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_1[10]; |
| 2046 |
#endif |
| 2047 |
|
| 2048 |
|
| 2049 |
/* |
| 2050 |
* id : BUF_LEN_TRK_NUMBER_DSP_1_2 |
| 2051 |
* type : <var> |
| 2052 |
* TRK command queue /RO |
| 2053 |
* location: 3 |
| 2054 |
*/ |
| 2055 |
|
| 2056 |
#ifdef PRH_DEFAULT_MODE |
| 2057 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_2=30; |
| 2058 |
#else |
| 2059 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_2; |
| 2060 |
#endif |
| 2061 |
|
| 2062 |
/* |
| 2063 |
* id : BUF_TRK_NUMBER_DSP_1_2 |
| 2064 |
* type : <array>[10] |
| 2065 |
* TRK command queue /RO |
| 2066 |
* location: 3 |
| 2067 |
*/ |
| 2068 |
|
| 2069 |
#ifdef PRH_DEFAULT_MODE |
| 2070 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_2[10]={0x001B2127,0x00730200,0x08000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07CB0000}; |
| 2071 |
#else |
| 2072 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_2[10]; |
| 2073 |
#endif |
| 2074 |
|
| 2075 |
|
| 2076 |
/* |
| 2077 |
* id : BUF_LEN_TRK_NUMBER_DSP_1_3 |
| 2078 |
* type : <var> |
| 2079 |
* TRK command queue /RO |
| 2080 |
* location: 3 |
| 2081 |
*/ |
| 2082 |
|
| 2083 |
#ifdef PRH_DEFAULT_MODE |
| 2084 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_3=30; |
| 2085 |
#else |
| 2086 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_3; |
| 2087 |
#endif |
| 2088 |
|
| 2089 |
/* |
| 2090 |
* id : BUF_TRK_NUMBER_DSP_1_3 |
| 2091 |
* type : <array>[10] |
| 2092 |
* TRK command queue /RO |
| 2093 |
* location: 3 |
| 2094 |
*/ |
| 2095 |
|
| 2096 |
#ifdef PRH_DEFAULT_MODE |
| 2097 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_3[10]={0x001B3157,0x00730200,0x04000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07C30000}; |
| 2098 |
#else |
| 2099 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_3[10]; |
| 2100 |
#endif |
| 2101 |
|
| 2102 |
|
| 2103 |
/* |
| 2104 |
* id : BUF_LEN_TRK_NUMBER_DSP_1_4 |
| 2105 |
* type : <var> |
| 2106 |
* TRK command queue /RO |
| 2107 |
* location: 3 |
| 2108 |
*/ |
| 2109 |
|
| 2110 |
#ifdef PRH_DEFAULT_MODE |
| 2111 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_4=30; |
| 2112 |
#else |
| 2113 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_4; |
| 2114 |
#endif |
| 2115 |
|
| 2116 |
/* |
| 2117 |
* id : BUF_TRK_NUMBER_DSP_1_4 |
| 2118 |
* type : <array>[10] |
| 2119 |
* TRK command queue /RO |
| 2120 |
* location: 3 |
| 2121 |
*/ |
| 2122 |
|
| 2123 |
#ifdef PRH_DEFAULT_MODE |
| 2124 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_4[10]={0x001B4100,0x00730200,0x06000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07A50000}; |
| 2125 |
#else |
| 2126 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_4[10]; |
| 2127 |
#endif |
| 2128 |
|
| 2129 |
|
| 2130 |
/* |
| 2131 |
* id : BUF_LEN_TRK_NUMBER_DSP_1_5 |
| 2132 |
* type : <var> |
| 2133 |
* TRK command queue /RO |
| 2134 |
* location: 3 |
| 2135 |
*/ |
| 2136 |
|
| 2137 |
#ifdef PRH_DEFAULT_MODE |
| 2138 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_5=30; |
| 2139 |
#else |
| 2140 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_5; |
| 2141 |
#endif |
| 2142 |
|
| 2143 |
/* |
| 2144 |
* id : BUF_TRK_NUMBER_DSP_1_5 |
| 2145 |
* type : <array>[10] |
| 2146 |
* TRK command queue /RO |
| 2147 |
* location: 3 |
| 2148 |
*/ |
| 2149 |
|
| 2150 |
#ifdef PRH_DEFAULT_MODE |
| 2151 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_5[10]={0x001B5170,0x00730200,0x02000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x079F0000}; |
| 2152 |
#else |
| 2153 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_1_5[10]; |
| 2154 |
#endif |
| 2155 |
|
| 2156 |
|
| 2157 |
/* |
| 2158 |
* id : BUF_LEN_TRK_NUMBER_DSP_2_0 |
| 2159 |
* type : <var> |
| 2160 |
* TRK command queue /RO |
| 2161 |
* location: 3 |
| 2162 |
*/ |
| 2163 |
|
| 2164 |
#ifdef PRH_DEFAULT_MODE |
| 2165 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_0=30; |
| 2166 |
#else |
| 2167 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_0; |
| 2168 |
#endif |
| 2169 |
|
| 2170 |
/* |
| 2171 |
* id : BUF_TRK_NUMBER_DSP_2_0 |
| 2172 |
* type : <array>[10] |
| 2173 |
* TRK command queue /RO |
| 2174 |
* location: 3 |
| 2175 |
*/ |
| 2176 |
|
| 2177 |
#ifdef PRH_DEFAULT_MODE |
| 2178 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_0[10]={0x001B01C7,0x00730200,0x0B000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07C60000}; |
| 2179 |
#else |
| 2180 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_0[10]; |
| 2181 |
#endif |
| 2182 |
|
| 2183 |
|
| 2184 |
/* |
| 2185 |
* id : BUF_LEN_TRK_NUMBER_DSP_2_1 |
| 2186 |
* type : <var> |
| 2187 |
* TRK command queue /RO |
| 2188 |
* location: 3 |
| 2189 |
*/ |
| 2190 |
|
| 2191 |
#ifdef PRH_DEFAULT_MODE |
| 2192 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_1=30; |
| 2193 |
#else |
| 2194 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_1; |
| 2195 |
#endif |
| 2196 |
|
| 2197 |
/* |
| 2198 |
* id : BUF_TRK_NUMBER_DSP_2_1 |
| 2199 |
* type : <array>[10] |
| 2200 |
* TRK command queue /RO |
| 2201 |
* location: 3 |
| 2202 |
*/ |
| 2203 |
|
| 2204 |
#ifdef PRH_DEFAULT_MODE |
| 2205 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_1[10]={0x001B11B7,0x00730200,0x09000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x076A0000}; |
| 2206 |
#else |
| 2207 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_1[10]; |
| 2208 |
#endif |
| 2209 |
|
| 2210 |
|
| 2211 |
/* |
| 2212 |
* id : BUF_LEN_TRK_NUMBER_DSP_2_2 |
| 2213 |
* type : <var> |
| 2214 |
* TRK command queue /RO |
| 2215 |
* location: 3 |
| 2216 |
*/ |
| 2217 |
|
| 2218 |
#ifdef PRH_DEFAULT_MODE |
| 2219 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_2=30; |
| 2220 |
#else |
| 2221 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_2; |
| 2222 |
#endif |
| 2223 |
|
| 2224 |
/* |
| 2225 |
* id : BUF_TRK_NUMBER_DSP_2_2 |
| 2226 |
* type : <array>[10] |
| 2227 |
* TRK command queue /RO |
| 2228 |
* location: 3 |
| 2229 |
*/ |
| 2230 |
|
| 2231 |
#ifdef PRH_DEFAULT_MODE |
| 2232 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_2[10]={0x001B2127,0x00730200,0x07000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07AB0000}; |
| 2233 |
#else |
| 2234 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_2[10]; |
| 2235 |
#endif |
| 2236 |
|
| 2237 |
|
| 2238 |
/* |
| 2239 |
* id : BUF_LEN_TRK_NUMBER_DSP_2_3 |
| 2240 |
* type : <var> |
| 2241 |
* TRK command queue /RO |
| 2242 |
* location: 3 |
| 2243 |
*/ |
| 2244 |
|
| 2245 |
#ifdef PRH_DEFAULT_MODE |
| 2246 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_3=30; |
| 2247 |
#else |
| 2248 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_3; |
| 2249 |
#endif |
| 2250 |
|
| 2251 |
/* |
| 2252 |
* id : BUF_TRK_NUMBER_DSP_2_3 |
| 2253 |
* type : <array>[10] |
| 2254 |
* TRK command queue /RO |
| 2255 |
* location: 3 |
| 2256 |
*/ |
| 2257 |
|
| 2258 |
#ifdef PRH_DEFAULT_MODE |
| 2259 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_3[10]={0x001B3157,0x00730200,0x03000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07910000}; |
| 2260 |
#else |
| 2261 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_3[10]; |
| 2262 |
#endif |
| 2263 |
|
| 2264 |
|
| 2265 |
/* |
| 2266 |
* id : BUF_LEN_TRK_NUMBER_DSP_2_4 |
| 2267 |
* type : <var> |
| 2268 |
* TRK command queue /RO |
| 2269 |
* location: 3 |
| 2270 |
*/ |
| 2271 |
|
| 2272 |
#ifdef PRH_DEFAULT_MODE |
| 2273 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_4=30; |
| 2274 |
#else |
| 2275 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_4; |
| 2276 |
#endif |
| 2277 |
|
| 2278 |
/* |
| 2279 |
* id : BUF_TRK_NUMBER_DSP_2_4 |
| 2280 |
* type : <array>[10] |
| 2281 |
* TRK command queue /RO |
| 2282 |
* location: 3 |
| 2283 |
*/ |
| 2284 |
|
| 2285 |
#ifdef PRH_DEFAULT_MODE |
| 2286 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_4[10]={0x001B4100,0x00730200,0x05000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07EE0000}; |
| 2287 |
#else |
| 2288 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_4[10]; |
| 2289 |
#endif |
| 2290 |
|
| 2291 |
|
| 2292 |
/* |
| 2293 |
* id : BUF_LEN_TRK_NUMBER_DSP_2_5 |
| 2294 |
* type : <var> |
| 2295 |
* TRK command queue /RO |
| 2296 |
* location: 3 |
| 2297 |
*/ |
| 2298 |
|
| 2299 |
#ifdef PRH_DEFAULT_MODE |
| 2300 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_5=30; |
| 2301 |
#else |
| 2302 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_5; |
| 2303 |
#endif |
| 2304 |
|
| 2305 |
/* |
| 2306 |
* id : BUF_TRK_NUMBER_DSP_2_5 |
| 2307 |
* type : <array>[10] |
| 2308 |
* TRK command queue /RO |
| 2309 |
* location: 3 |
| 2310 |
*/ |
| 2311 |
|
| 2312 |
#ifdef PRH_DEFAULT_MODE |
| 2313 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_5[10]={0x001B5170,0x00730200,0x01000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07D40000}; |
| 2314 |
#else |
| 2315 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_NUMBER_DSP_2_5[10]; |
| 2316 |
#endif |
| 2317 |
|
| 2318 |
|
| 2319 |
/* |
| 2320 |
* id : BUF_LEN_TRK_OPMODE_COMP_0 |
| 2321 |
* type : <var> |
| 2322 |
* TRK command queue /RO |
| 2323 |
* location: 3 |
| 2324 |
*/ |
| 2325 |
|
| 2326 |
#ifdef PRH_DEFAULT_MODE |
| 2327 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_0=10; |
| 2328 |
#else |
| 2329 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_0; |
| 2330 |
#endif |
| 2331 |
|
| 2332 |
/* |
| 2333 |
* id : BUF_TRK_OPMODE_COMP_0 |
| 2334 |
* type : <array>[3] |
| 2335 |
* TRK command queue /RO |
| 2336 |
* location: 3 |
| 2337 |
*/ |
| 2338 |
|
| 2339 |
#ifdef PRH_DEFAULT_MODE |
| 2340 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_0[3]={0x0007016C,0x00730100,0x0A6F0000}; |
| 2341 |
#else |
| 2342 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_0[3]; |
| 2343 |
#endif |
| 2344 |
|
| 2345 |
|
| 2346 |
/* |
| 2347 |
* id : BUF_LEN_TRK_OPMODE_SPEC_0 |
| 2348 |
* type : <var> |
| 2349 |
* TRK command queue /RO |
| 2350 |
* location: 3 |
| 2351 |
*/ |
| 2352 |
|
| 2353 |
#ifdef PRH_DEFAULT_MODE |
| 2354 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_0=10; |
| 2355 |
#else |
| 2356 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_0; |
| 2357 |
#endif |
| 2358 |
|
| 2359 |
/* |
| 2360 |
* id : BUF_TRK_OPMODE_SPEC_0 |
| 2361 |
* type : <array>[3] |
| 2362 |
* TRK command queue /RO |
| 2363 |
* location: 3 |
| 2364 |
*/ |
| 2365 |
|
| 2366 |
#ifdef PRH_DEFAULT_MODE |
| 2367 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_0[3]={0x0007016C,0x00730100,0x08610000}; |
| 2368 |
#else |
| 2369 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_0[3]; |
| 2370 |
#endif |
| 2371 |
|
| 2372 |
|
| 2373 |
/* |
| 2374 |
* id : BUF_LEN_TRK_OPMODE_COMP_1 |
| 2375 |
* type : <var> |
| 2376 |
* TRK command queue /RO |
| 2377 |
* location: 3 |
| 2378 |
*/ |
| 2379 |
|
| 2380 |
#ifdef PRH_DEFAULT_MODE |
| 2381 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_1=10; |
| 2382 |
#else |
| 2383 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_1; |
| 2384 |
#endif |
| 2385 |
|
| 2386 |
/* |
| 2387 |
* id : BUF_TRK_OPMODE_COMP_1 |
| 2388 |
* type : <array>[3] |
| 2389 |
* TRK command queue /RO |
| 2390 |
* location: 3 |
| 2391 |
*/ |
| 2392 |
|
| 2393 |
#ifdef PRH_DEFAULT_MODE |
| 2394 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_1[3]={0x0007111C,0x00730100,0x0AF10000}; |
| 2395 |
#else |
| 2396 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_1[3]; |
| 2397 |
#endif |
| 2398 |
|
| 2399 |
|
| 2400 |
/* |
| 2401 |
* id : BUF_LEN_TRK_OPMODE_SPEC_1 |
| 2402 |
* type : <var> |
| 2403 |
* TRK command queue /RO |
| 2404 |
* location: 3 |
| 2405 |
*/ |
| 2406 |
|
| 2407 |
#ifdef PRH_DEFAULT_MODE |
| 2408 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_1=10; |
| 2409 |
#else |
| 2410 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_1; |
| 2411 |
#endif |
| 2412 |
|
| 2413 |
/* |
| 2414 |
* id : BUF_TRK_OPMODE_SPEC_1 |
| 2415 |
* type : <array>[3] |
| 2416 |
* TRK command queue /RO |
| 2417 |
* location: 3 |
| 2418 |
*/ |
| 2419 |
|
| 2420 |
#ifdef PRH_DEFAULT_MODE |
| 2421 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_1[3]={0x0007111C,0x00730100,0x08FF0000}; |
| 2422 |
#else |
| 2423 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_1[3]; |
| 2424 |
#endif |
| 2425 |
|
| 2426 |
|
| 2427 |
/* |
| 2428 |
* id : BUF_LEN_TRK_OPMODE_COMP_2 |
| 2429 |
* type : <var> |
| 2430 |
* TRK command queue /RO |
| 2431 |
* location: 3 |
| 2432 |
*/ |
| 2433 |
|
| 2434 |
#ifdef PRH_DEFAULT_MODE |
| 2435 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_2=10; |
| 2436 |
#else |
| 2437 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_2; |
| 2438 |
#endif |
| 2439 |
|
| 2440 |
/* |
| 2441 |
* id : BUF_TRK_OPMODE_COMP_2 |
| 2442 |
* type : <array>[3] |
| 2443 |
* TRK command queue /RO |
| 2444 |
* location: 3 |
| 2445 |
*/ |
| 2446 |
|
| 2447 |
#ifdef PRH_DEFAULT_MODE |
| 2448 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_2[3]={0x0007218C,0x00730100,0x0A540000}; |
| 2449 |
#else |
| 2450 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_2[3]; |
| 2451 |
#endif |
| 2452 |
|
| 2453 |
|
| 2454 |
/* |
| 2455 |
* id : BUF_LEN_TRK_OPMODE_SPEC_2 |
| 2456 |
* type : <var> |
| 2457 |
* TRK command queue /RO |
| 2458 |
* location: 3 |
| 2459 |
*/ |
| 2460 |
|
| 2461 |
#ifdef PRH_DEFAULT_MODE |
| 2462 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_2=10; |
| 2463 |
#else |
| 2464 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_2; |
| 2465 |
#endif |
| 2466 |
|
| 2467 |
/* |
| 2468 |
* id : BUF_TRK_OPMODE_SPEC_2 |
| 2469 |
* type : <array>[3] |
| 2470 |
* TRK command queue /RO |
| 2471 |
* location: 3 |
| 2472 |
*/ |
| 2473 |
|
| 2474 |
#ifdef PRH_DEFAULT_MODE |
| 2475 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_2[3]={0x0007218C,0x00730100,0x085A0000}; |
| 2476 |
#else |
| 2477 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_2[3]; |
| 2478 |
#endif |
| 2479 |
|
| 2480 |
|
| 2481 |
/* |
| 2482 |
* id : BUF_LEN_TRK_OPMODE_COMP_3 |
| 2483 |
* type : <var> |
| 2484 |
* TRK command queue /RO |
| 2485 |
* location: 3 |
| 2486 |
*/ |
| 2487 |
|
| 2488 |
#ifdef PRH_DEFAULT_MODE |
| 2489 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_3=10; |
| 2490 |
#else |
| 2491 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_3; |
| 2492 |
#endif |
| 2493 |
|
| 2494 |
/* |
| 2495 |
* id : BUF_TRK_OPMODE_COMP_3 |
| 2496 |
* type : <array>[3] |
| 2497 |
* TRK command queue /RO |
| 2498 |
* location: 3 |
| 2499 |
*/ |
| 2500 |
|
| 2501 |
#ifdef PRH_DEFAULT_MODE |
| 2502 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_3[3]={0x000731FC,0x00730100,0x0ACA0000}; |
| 2503 |
#else |
| 2504 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_3[3]; |
| 2505 |
#endif |
| 2506 |
|
| 2507 |
|
| 2508 |
/* |
| 2509 |
* id : BUF_LEN_TRK_OPMODE_SPEC_3 |
| 2510 |
* type : <var> |
| 2511 |
* TRK command queue /RO |
| 2512 |
* location: 3 |
| 2513 |
*/ |
| 2514 |
|
| 2515 |
#ifdef PRH_DEFAULT_MODE |
| 2516 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_3=10; |
| 2517 |
#else |
| 2518 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_3; |
| 2519 |
#endif |
| 2520 |
|
| 2521 |
/* |
| 2522 |
* id : BUF_TRK_OPMODE_SPEC_3 |
| 2523 |
* type : <array>[3] |
| 2524 |
* TRK command queue /RO |
| 2525 |
* location: 3 |
| 2526 |
*/ |
| 2527 |
|
| 2528 |
#ifdef PRH_DEFAULT_MODE |
| 2529 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_3[3]={0x000731FC,0x00730100,0x08C40000}; |
| 2530 |
#else |
| 2531 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_3[3]; |
| 2532 |
#endif |
| 2533 |
|
| 2534 |
|
| 2535 |
/* |
| 2536 |
* id : BUF_LEN_TRK_OPMODE_COMP_4 |
| 2537 |
* type : <var> |
| 2538 |
* TRK command queue /RO |
| 2539 |
* location: 3 |
| 2540 |
*/ |
| 2541 |
|
| 2542 |
#ifdef PRH_DEFAULT_MODE |
| 2543 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_4=10; |
| 2544 |
#else |
| 2545 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_4; |
| 2546 |
#endif |
| 2547 |
|
| 2548 |
/* |
| 2549 |
* id : BUF_TRK_OPMODE_COMP_4 |
| 2550 |
* type : <array>[3] |
| 2551 |
* TRK command queue /RO |
| 2552 |
* location: 3 |
| 2553 |
*/ |
| 2554 |
|
| 2555 |
#ifdef PRH_DEFAULT_MODE |
| 2556 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_4[3]={0x000741AB,0x00730100,0x0A190000}; |
| 2557 |
#else |
| 2558 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_4[3]; |
| 2559 |
#endif |
| 2560 |
|
| 2561 |
|
| 2562 |
/* |
| 2563 |
* id : BUF_LEN_TRK_OPMODE_SPEC_4 |
| 2564 |
* type : <var> |
| 2565 |
* TRK command queue /RO |
| 2566 |
* location: 3 |
| 2567 |
*/ |
| 2568 |
|
| 2569 |
#ifdef PRH_DEFAULT_MODE |
| 2570 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_4=10; |
| 2571 |
#else |
| 2572 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_4; |
| 2573 |
#endif |
| 2574 |
|
| 2575 |
/* |
| 2576 |
* id : BUF_TRK_OPMODE_SPEC_4 |
| 2577 |
* type : <array>[3] |
| 2578 |
* TRK command queue /RO |
| 2579 |
* location: 3 |
| 2580 |
*/ |
| 2581 |
|
| 2582 |
#ifdef PRH_DEFAULT_MODE |
| 2583 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_4[3]={0x000741AB,0x00730100,0x08170000}; |
| 2584 |
#else |
| 2585 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_4[3]; |
| 2586 |
#endif |
| 2587 |
|
| 2588 |
|
| 2589 |
/* |
| 2590 |
* id : BUF_LEN_TRK_OPMODE_COMP_5 |
| 2591 |
* type : <var> |
| 2592 |
* TRK command queue /RO |
| 2593 |
* location: 3 |
| 2594 |
*/ |
| 2595 |
|
| 2596 |
#ifdef PRH_DEFAULT_MODE |
| 2597 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_5=10; |
| 2598 |
#else |
| 2599 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_5; |
| 2600 |
#endif |
| 2601 |
|
| 2602 |
/* |
| 2603 |
* id : BUF_TRK_OPMODE_COMP_5 |
| 2604 |
* type : <array>[3] |
| 2605 |
* TRK command queue /RO |
| 2606 |
* location: 3 |
| 2607 |
*/ |
| 2608 |
|
| 2609 |
#ifdef PRH_DEFAULT_MODE |
| 2610 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_5[3]={0x000751DB,0x00730100,0x0A870000}; |
| 2611 |
#else |
| 2612 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_COMP_5[3]; |
| 2613 |
#endif |
| 2614 |
|
| 2615 |
|
| 2616 |
/* |
| 2617 |
* id : BUF_LEN_TRK_OPMODE_SPEC_5 |
| 2618 |
* type : <var> |
| 2619 |
* TRK command queue /RO |
| 2620 |
* location: 3 |
| 2621 |
*/ |
| 2622 |
|
| 2623 |
#ifdef PRH_DEFAULT_MODE |
| 2624 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_5=10; |
| 2625 |
#else |
| 2626 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_5; |
| 2627 |
#endif |
| 2628 |
|
| 2629 |
/* |
| 2630 |
* id : BUF_TRK_OPMODE_SPEC_5 |
| 2631 |
* type : <array>[3] |
| 2632 |
* TRK command queue /RO |
| 2633 |
* location: 3 |
| 2634 |
*/ |
| 2635 |
|
| 2636 |
#ifdef PRH_DEFAULT_MODE |
| 2637 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_5[3]={0x000751DB,0x00730100,0x08890000}; |
| 2638 |
#else |
| 2639 |
PRH_VAR_TYPE PRH_ARR_BUF_TRK_OPMODE_SPEC_5[3]; |
| 2640 |
#endif |
| 2641 |
|
| 2642 |
|
| 2643 |
/* |
| 2644 |
* --------- S4 Parameters : ------------- |
| 2645 |
*/ |
| 2646 |
|
| 2647 |
|
| 2648 |
/* |
| 2649 |
* id : S4_OK |
| 2650 |
* type : <var> |
| 2651 |
* S4 enable/disable /RO |
| 2652 |
* location: 3 |
| 2653 |
*/ |
| 2654 |
|
| 2655 |
#ifdef PRH_DEFAULT_MODE |
| 2656 |
PRH_VAR_TYPE PRH_VAR_S4_OK=1; |
| 2657 |
#else |
| 2658 |
PRH_VAR_TYPE PRH_VAR_S4_OK; |
| 2659 |
#endif |
| 2660 |
|
| 2661 |
/* |
| 2662 |
* id : S4_TRH |
| 2663 |
* type : <var> |
| 2664 |
* S4 command /RO |
| 2665 |
* location: 3 |
| 2666 |
*/ |
| 2667 |
|
| 2668 |
#ifdef PRH_DEFAULT_MODE |
| 2669 |
PRH_VAR_TYPE PRH_VAR_S4_TRH=16384; |
| 2670 |
#else |
| 2671 |
PRH_VAR_TYPE PRH_VAR_S4_TRH; |
| 2672 |
#endif |
| 2673 |
|
| 2674 |
/* |
| 2675 |
* id : S4_ATTEMPT |
| 2676 |
* type : <var> |
| 2677 |
* S4 force check /RO |
| 2678 |
* location: 3 |
| 2679 |
*/ |
| 2680 |
|
| 2681 |
#ifdef PRH_DEFAULT_MODE |
| 2682 |
PRH_VAR_TYPE PRH_VAR_S4_ATTEMPT=0; |
| 2683 |
#else |
| 2684 |
PRH_VAR_TYPE PRH_VAR_S4_ATTEMPT; |
| 2685 |
#endif |
| 2686 |
|
| 2687 |
/* |
| 2688 |
* id : S4_WORKING |
| 2689 |
* type : <var> |
| 2690 |
* check if S4 is working or not /RO |
| 2691 |
* location: 2 |
| 2692 |
*/ |
| 2693 |
|
| 2694 |
#ifdef PRH_DEFAULT_MODE |
| 2695 |
PRH_VAR_TYPE PRH_VAR_S4_WORKING=1; |
| 2696 |
#else |
| 2697 |
PRH_VAR_TYPE PRH_VAR_S4_WORKING=1; |
| 2698 |
#endif |
| 2699 |
|
| 2700 |
/* |
| 2701 |
* Power Supply: |
| 2702 |
*/ |
| 2703 |
|
| 2704 |
|
| 2705 |
/* |
| 2706 |
* Acquisition: |
| 2707 |
*/ |
| 2708 |
|
| 2709 |
|
| 2710 |
/* |
| 2711 |
* --------- Calorimeter Parameters : ------------- |
| 2712 |
*/ |
| 2713 |
|
| 2714 |
|
| 2715 |
/* |
| 2716 |
* id : CAL_UPLOAD_CAL_FE_MASK |
| 2717 |
* type : <var> |
| 2718 |
* Defines the working read-out of calorimeter /RO |
| 2719 |
* location: 3 |
| 2720 |
*/ |
| 2721 |
|
| 2722 |
#ifdef PRH_DEFAULT_MODE |
| 2723 |
PRH_VAR_TYPE PRH_VAR_CAL_UPLOAD_CAL_FE_MASK=15; |
| 2724 |
#else |
| 2725 |
PRH_VAR_TYPE PRH_VAR_CAL_UPLOAD_CAL_FE_MASK; |
| 2726 |
#endif |
| 2727 |
|
| 2728 |
/* |
| 2729 |
* id : CAL_UPLOAD_CAL_DSP_MASK |
| 2730 |
* type : <var> |
| 2731 |
* Defines the workings dsps of calorimeter /RO |
| 2732 |
* location: 3 |
| 2733 |
*/ |
| 2734 |
|
| 2735 |
#ifdef PRH_DEFAULT_MODE |
| 2736 |
PRH_VAR_TYPE PRH_VAR_CAL_UPLOAD_CAL_DSP_MASK=15; |
| 2737 |
#else |
| 2738 |
PRH_VAR_TYPE PRH_VAR_CAL_UPLOAD_CAL_DSP_MASK; |
| 2739 |
#endif |
| 2740 |
|
| 2741 |
/* |
| 2742 |
* id : CAL_VCAL |
| 2743 |
* type : <var> |
| 2744 |
* Variable modified by pulse calibration /RW |
| 2745 |
* location: 3 |
| 2746 |
*/ |
| 2747 |
|
| 2748 |
#ifdef PRH_DEFAULT_MODE |
| 2749 |
PRH_VAR_TYPE PRH_VAR_CAL_VCAL=32773; |
| 2750 |
#else |
| 2751 |
PRH_VAR_TYPE PRH_VAR_CAL_VCAL; |
| 2752 |
#endif |
| 2753 |
|
| 2754 |
/* |
| 2755 |
* id : CAL_CH |
| 2756 |
* type : <var> |
| 2757 |
* Variable modified by pulse calibration /RW |
| 2758 |
* location: 3 |
| 2759 |
*/ |
| 2760 |
|
| 2761 |
#ifdef PRH_DEFAULT_MODE |
| 2762 |
PRH_VAR_TYPE PRH_VAR_CAL_CH=1; |
| 2763 |
#else |
| 2764 |
PRH_VAR_TYPE PRH_VAR_CAL_CH; |
| 2765 |
#endif |
| 2766 |
|
| 2767 |
/* |
| 2768 |
* id : CAL_TEMP |
| 2769 |
* type : <var> |
| 2770 |
* Maximum calorimeter temperature alarms /RO |
| 2771 |
* location: 3 |
| 2772 |
*/ |
| 2773 |
|
| 2774 |
#ifdef PRH_DEFAULT_MODE |
| 2775 |
PRH_VAR_TYPE PRH_VAR_CAL_TEMP=5; |
| 2776 |
#else |
| 2777 |
PRH_VAR_TYPE PRH_VAR_CAL_TEMP; |
| 2778 |
#endif |
| 2779 |
|
| 2780 |
/* |
| 2781 |
* id : CAL_COUNT |
| 2782 |
* type : <array>[4] |
| 2783 |
* defines the calorimeter read out repetitions /RO |
| 2784 |
* location: 3 |
| 2785 |
*/ |
| 2786 |
|
| 2787 |
#ifdef PRH_DEFAULT_MODE |
| 2788 |
PRH_VAR_TYPE PRH_ARR_CAL_COUNT[4]={ |
| 2789 |
0x0003, |
| 2790 |
0x0003, |
| 2791 |
0x0003, |
| 2792 |
0x0003 |
| 2793 |
}; |
| 2794 |
#else |
| 2795 |
PRH_VAR_TYPE PRH_ARR_CAL_COUNT[4]; |
| 2796 |
#endif |
| 2797 |
|
| 2798 |
|
| 2799 |
/* |
| 2800 |
* id : CAL_OK |
| 2801 |
* type : <var> |
| 2802 |
* calo ON_OFF in ACQ /RW |
| 2803 |
* location: 3 |
| 2804 |
*/ |
| 2805 |
|
| 2806 |
#ifdef PRH_DEFAULT_MODE |
| 2807 |
PRH_VAR_TYPE PRH_VAR_CAL_OK=1; |
| 2808 |
#else |
| 2809 |
PRH_VAR_TYPE PRH_VAR_CAL_OK; |
| 2810 |
#endif |
| 2811 |
|
| 2812 |
/* |
| 2813 |
* id : CAL_CHECK_FE |
| 2814 |
* type : <var> |
| 2815 |
* calo check FE /RO |
| 2816 |
* location: 3 |
| 2817 |
*/ |
| 2818 |
|
| 2819 |
#ifdef PRH_DEFAULT_MODE |
| 2820 |
PRH_VAR_TYPE PRH_VAR_CAL_CHECK_FE=0; |
| 2821 |
#else |
| 2822 |
PRH_VAR_TYPE PRH_VAR_CAL_CHECK_FE; |
| 2823 |
#endif |
| 2824 |
|
| 2825 |
/* |
| 2826 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I211 |
| 2827 |
* type : <var> |
| 2828 |
* write fpga /RO |
| 2829 |
* location: 3 |
| 2830 |
*/ |
| 2831 |
|
| 2832 |
#ifdef PRH_DEFAULT_MODE |
| 2833 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I211=8; |
| 2834 |
#else |
| 2835 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I211; |
| 2836 |
#endif |
| 2837 |
|
| 2838 |
/* |
| 2839 |
* id : BUF_CAL_WRITE_FPGA_REG_I211 |
| 2840 |
* type : <array>[2] |
| 2841 |
* write fpga /RO |
| 2842 |
* location: 3 |
| 2843 |
*/ |
| 2844 |
|
| 2845 |
#ifdef PRH_DEFAULT_MODE |
| 2846 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I211[2]={0x4D230000,0x0001D214}; |
| 2847 |
#else |
| 2848 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I211[2]; |
| 2849 |
#endif |
| 2850 |
|
| 2851 |
|
| 2852 |
/* |
| 2853 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I221 |
| 2854 |
* type : <var> |
| 2855 |
* write fpga /RO |
| 2856 |
* location: 3 |
| 2857 |
*/ |
| 2858 |
|
| 2859 |
#ifdef PRH_DEFAULT_MODE |
| 2860 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I221=8; |
| 2861 |
#else |
| 2862 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I221; |
| 2863 |
#endif |
| 2864 |
|
| 2865 |
/* |
| 2866 |
* id : BUF_CAL_WRITE_FPGA_REG_I221 |
| 2867 |
* type : <array>[2] |
| 2868 |
* write fpga /RO |
| 2869 |
* location: 3 |
| 2870 |
*/ |
| 2871 |
|
| 2872 |
#ifdef PRH_DEFAULT_MODE |
| 2873 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I221[2]={0x4D230001,0x0000F505}; |
| 2874 |
#else |
| 2875 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I221[2]; |
| 2876 |
#endif |
| 2877 |
|
| 2878 |
|
| 2879 |
/* |
| 2880 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I231 |
| 2881 |
* type : <var> |
| 2882 |
* write fpga /RO |
| 2883 |
* location: 3 |
| 2884 |
*/ |
| 2885 |
|
| 2886 |
#ifdef PRH_DEFAULT_MODE |
| 2887 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I231=8; |
| 2888 |
#else |
| 2889 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I231; |
| 2890 |
#endif |
| 2891 |
|
| 2892 |
/* |
| 2893 |
* id : BUF_CAL_WRITE_FPGA_REG_I231 |
| 2894 |
* type : <array>[2] |
| 2895 |
* write fpga /RO |
| 2896 |
* location: 3 |
| 2897 |
*/ |
| 2898 |
|
| 2899 |
#ifdef PRH_DEFAULT_MODE |
| 2900 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I231[2]={0x4D230003,0xFFFF866A}; |
| 2901 |
#else |
| 2902 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I231[2]; |
| 2903 |
#endif |
| 2904 |
|
| 2905 |
|
| 2906 |
/* |
| 2907 |
* id : BUF_LEN_CAL_WRITE_DSP_MEM_I41 |
| 2908 |
* type : <var> |
| 2909 |
* dsp prog i41 /R0 |
| 2910 |
* location: 1 |
| 2911 |
*/ |
| 2912 |
|
| 2913 |
#ifdef PRH_DEFAULT_MODE |
| 2914 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I41=4234; |
| 2915 |
#else |
| 2916 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I41; |
| 2917 |
#endif |
| 2918 |
|
| 2919 |
/* |
| 2920 |
* id : BUF_CAL_WRITE_DSP_MEM_I41 |
| 2921 |
* type : <array>[3176] |
| 2922 |
* dsp prog i41 /R0 |
| 2923 |
* location: 1 |
| 2924 |
*/ |
| 2925 |
|
| 2926 |
#ifdef PRH_DEFAULT_MODE |
| 2927 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I41[3176]={0x8E630000,0x14000840,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000000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|
| 2928 |
#else |
| 2929 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I41[3176]; |
| 2930 |
#endif |
| 2931 |
|
| 2932 |
|
| 2933 |
/* |
| 2934 |
* id : BUF_LEN_CAL_WRITE_DSP_MEM_I42 |
| 2935 |
* type : <var> |
| 2936 |
* dsp prog i42 /RO |
| 2937 |
* location: 1 |
| 2938 |
*/ |
| 2939 |
|
| 2940 |
#ifdef PRH_DEFAULT_MODE |
| 2941 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I42=3646; |
| 2942 |
#else |
| 2943 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I42; |
| 2944 |
#endif |
| 2945 |
|
| 2946 |
/* |
| 2947 |
* id : BUF_CAL_WRITE_DSP_MEM_I42 |
| 2948 |
* type : <array>[2723] |
| 2949 |
* dsp prog i42 /RO |
| 2950 |
* location: 1 |
| 2951 |
*/ |
| 2952 |
|
| 2953 |
#ifdef PRH_DEFAULT_MODE |
| 2954 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I42[2723]={0x8E638000,0x0001071A,0x0A00001F,0x0A00001F,0x0A00001F,0x1807008F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x180400EF,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x180B009F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x0A00001F,0x3C000074,0x3C290003,0x3C050001,0x40400070,0x93FF00F0,0x47FF00F0,0x93FF00E0,0x47B00000,0x93FE0060,0x04000060,0x180300CF,0x02800000,0x020000CF,0x0203000F,0x020C000F,0x3400000F,0x34000008,0x34000009,0x3400000A,0x3400000B,0x38000008,0x38000009,0x3800000A,0x3800000B,0x34000004,0x34000015,0x38000004,0x38000015,0x40000016,0x180300BF,0x0200008F,0x83FE005A,0x40000064,0x2B8200AA,0x18060010,0x35D00001,0x278200DF,0x18070040,0x2782009F,0x180500A0,0x44210000,0x180500DF,0x40000000,0x919F00A0,0x42100080,0x919F0090,0x40000000,0x919F0080,0x1807004F,0x383800B0,0x278200DF,0x500000A0,0x23180001,0x2262001F,0x580000A0,0x34000008,0x34000015,0x358C00B0,0x959F0040,0x47FF00FA,0x3C040025,0x140600EE,0x680000A1,0x41080040,0x919F0090,0x2098000F,0x340000B1,0x354A00B3,0x40000000,0x919F0030,0x39400000,0x0A00001F,0x83FE005A,0x40000064,0x2B8200AA,0x180700E0,0x1C0A009F,0x180700FF,0x1C08001F,0x0202000F,0x0A00001F,0x34060006,0x37BE0017,0x38060006,0x3BBE0017,0x34000000,0x859F0042,0x4FFF00C9,0x3C0000B5,0x140900BE,0xC0000001,0x0D030057,0x6800000E,0x2AE00085,0x10100024,0x678E0048,0x18090040,0x3C0F00F7,0x680000A6,0x1809007F,0x3C000007,0x6EE200A6,0x18090094,0x09000009,0x180900BF,0x680000A9,0x00000000,0x59000022,0x09000007,0x0900000F,0x09000013,0x819F003A,0x2262001F,0x26EA001F,0x180A0050,0x00000000,0x180A007F,0x959F0042,0x4000000A,0x919F003A,0x0A00000F,0x34060006,0x37BE0017,0x38060006,0x3BBE0017,0x83FE0050,0x34000000,0x3C0000B5,0x140B005E,0x600000A1,0x50000042,0x2780009F,0x22E20001,0x680000A6,0x09000007,0x09000013,0x0A00000F,0x819F0090,0x1C3700AF,0x919F009E,0x41080044,0x2AE600AA,0x180C0011,0x1C0E009F,0x180E007F,0x42100084,0x2AE600AA,0x180C0061,0x1C1700AF,0x180E007F,0x44210004,0x2AE600AA,0x180C00B1,0x1C3000BF,0x180E007F,0x42520094,0x2AE600AA,0x180D0001,0x1C20003F,0x180E007F,0x429400A4,0x2AE600AA,0x180D0051,0x1C27008F,0x180E007F,0x431800C4,0x2AE600AA,0x180D00A1,0x1C2B00CF,0x180E007F,0x42D600B4,0x2AE600AA,0x180D00F1,0x1C2500AF,0x180E007F,0x44630014,0x2AE600AA,0x180E0041,0x1C32008F,0x180E007F,0x35D00000,0xA0000011,0x680000E1,0x0208000F,0x0A00001F,0x39D00032,0x4CA5000A,0x780000A9,0x780000A9,0x4000000A,0x83FE0050,0x2780001F,0x237A0001,0x780000A9,0x39820000,0x40000001,0x50000041,0x52E30041,0x180F0091,0x22C4000F,0x180F00B0,0x400F00F1,0x04000040,0x2098000F,0x40000016,0x39820020,0x3C040025,0x1410001E,0x50000021,0x2160000F,0x39860040,0x40000005,0x50000041,0x52E30041,0x18100091,0x22C4000F,0x181000B0,0x4FF00005,0x04000040,0x23A9000F,0x780000A9,0x383800B0,0x500000A0,0x780000A9,0x83FE0050,0x2380001F,0x18110081,0x354A00B0,0x3C420005,0x1411007E,0x60000001,0x78000009,0x340000B0,0x354A00B1,0x398C00B0,0x39820021,0x37FF00F6,0x37FF0007,0x380000B6,0x3BFB00F7,0x40000016,0x40000000,0x919F0070,0x3C0000B5,0x1416008E,0x3C000065,0x1416007E,0x399D0033,0x40000004,0x2098000F,0x40000005,0x400000B4,0x56000005,0x70000042,0x2A600004,0x0D00001A,0x3C010005,0x1414002E,0x60000041,0x2AE00024,0x18140022,0x22E1000F,0x181300B4,0x2160000F,0x2228000F,0x0D00005A,0x1814002F,0x0D0100A0,0x22F2000F,0x22E2001F,0x400000F4,0x63820044,0x780000AD,0x7800004D,0x09000005,0x0D010000,0x22F0000F,0x0F1200FC,0x22E6001F,0x0D00001A,0x0D000005,0x266000FF,0x181500D4,0x23B100DF,0x780000A9,0x1C33007F,0x780000A9,0x419D0034,0x0D020003,0x22E0000F,0x18160070,0x399D0033,0x0D0C005A,0x1415007E,0x7000000D,0x78000009,0x0F1200FF,0x819F0075,0x226E000F,0x919F007A,0x1816007F,0x819F007A,0x226A001F,0x919F007A,0x09000007,0x23B9001F,0x780000A9,0x3C010005,0x1416006E,0x60000005,0x78000009,0x00000000,0x09000013,0x819F0070,0x383800D0,0x50000040,0x4000000A,0x2AE000AA,0x237A0005,0x35D00010,0x680000A1,0x68000001,0x0D020002,0x41D00004,0x22E0000F,0x22E2001F,0x91D0000A,0x41080040,0x919F0090,0x0A00000F,0x819F00A0,0x1C3700AF,0x919F00AE,0x819F0081,0x40000004,0x2EE6005E,0x181B0050,0x35D00000,0x358C00B1,0x359000D2,0x0D050032,0x39400000,0x39C80061,0x0D0A0021,0x4FFF00C9,0x40000016,0x3C040025,0x141B003E,0x2098000F,0x4000000A,0x3C010005,0x141900AE,0xF8000001,0x0D030087,0x10100048,0x2B8600AA,0x18190091,0x2262001F,0x3C000007,0x2160000F,0x181900AF,0x3C0F00F7,0x58000071,0x0D00000A,0x1C33007F,0x47FF00F0,0x2AE800AA,0x181B0031,0x600000B9,0x600000C9,0x667A00A9,0x2A7900AA,0x181A0081,0x4000000A,0x509800E5,0x181A009F,0x52F200E5,0x53FA00F5,0x2162000F,0x680000BD,0x6A1000CD,0x0D0000BE,0x2E7900CF,0x20980000,0x696200AD,0x580000B9,0x580000C9,0x680000A5,0x181B00AF,0x358C00B1,0x4000000A,0x3C040025,0x141B009E,0x680000A5,0x35D00000,0x340000B1,0x0D050021,0x358C00B3,0x39400000,0x39860061,0x40000016,0x3C040025,0x141E004E,0x600000ED,0x3C010005,0x141E003E,0x600000A5,0x667A0041,0x627900B5,0x26180000,0x627900C5,0x20980000,0x2326000F,0x47FF00F0,0x2AE800FA,0x181D0081,0x50000041,0x52E70045,0x181D0045,0x181D006F,0x22E7000F,0x181D0083,0x4000000F,0x2710000F,0x2230000F,0x690700A9,0x680000B9,0x680000C9,0x600000B5,0x600000C5,0x627900D5,0x20980000,0x2107001F,0x680000B9,0x680000C9,0x680000D9,0x00000000,0x819F00A0,0x1C3700AF,0x919F00AE,0x819F0084,0x2220000F,0x919F008A,0x35D00000,0xA0000031,0x680000A1,0x42100080,0x68000001,0x680000E1,0x47FF00F4,0x26E6000F,0x181F0060,0x40100005,0x181F007F,0x40400005,0x22EA000F,0x18200011,0x919F008A,0x42520090,0x400000B1,0x919F0041,0x41400001,0x919F0051,0x41860061,0x919F0061,0x919F0090,0x0A00000F,0x859F0040,0x899F0050,0x899F0061,0x3C060005,0x1423009E,0x60000001,0x600000B1,0x600000C1,0x267C000F,0x18210005,0x233B000F,0x2B5C00BA,0x0D0000CA,0x2A100060,0x1C33007F,0x2E7E0046,0x233A0004,0x500000E0,0x580000A1,0x2B0000EB,0x28E200FC,0x0D00005C,0x60000021,0x60000031,0x28E0004B,0x21E6001F,0x60000021,0x2A7D008B,0x23C2001C,0x0D0000BC,0x0D0000CA,0x2961007F,0x21EE000F,0x29EE00E8,0x2A7D008B,0x23C2001C,0x0D0000BC,0x0D0000CA,0x2160000F,0x21E7001F,0x0D0000FC,0x0D0000C8,0x2A7E00EB,0x0D0000BA,0x1C35001F,0x400F00F4,0x2B8400AA,0x18230071,0x1C3600DF,0x2262001F,0x0F1200FF,0x1823008F,0x4080000E,0x3C000007,0x580000E5,0x959F0040,0x999F0050,0x999F0061,0x819F00A0,0x1C3700AF,0x919F00AE,0x819F0084,0x2220000F,0x919F008A,0x35D00000,0xA0000031,0x680000A1,0x42520090,0x68000001,0x680000E1,0x400000B5,0x22EA000F,0x18250081,0x919F008A,0x46310084,0x2AE600AA,0x18250021,0x42D600B0,0x1825008F,0x47FF00F4,0x2AE600AA,0x18250071,0x431800C0,0x1825008F,0x429400A0,0x919F0090,0x0A00000F,0x40000066,0x48000000,0x47FF00F1,0x39400000,0x39860061,0x3C420005,0x142600AE,0x50980024,0x4000002B,0x51600040,0x0F1300FE,0x2326000F,0x22780006,0x5A6600A1,0x22790006,0x3C000007,0x580000A5,0x40000000,0x919F0080,0x819F00A0,0x1C3700AF,0x47FF00F0,0x919F00A0,0x42100080,0x919F0090,0x35D00000,0xA0000021,0xA2D600B1,0x680000E1,0x0A00000F,0x4FFF00C9,0x40000026,0x3C000025,0x142A002E,0x39860060,0x39400001,0x3C040025,0x142A001E,0x2098000F,0x4000000A,0x0D0A0020,0x0D0A0031,0x3C010005,0x142800CE,0x50000021,0x50000005,0x0D030087,0x10100048,0x2B8600AA,0x21600000,0x22620010,0x0D00000A,0x1C33007F,0x0D0000CA,0x0D0A0002,0x0D0A0013,0x3C010005,0x142A000E,0x50000041,0x56E400B4,0x18290095,0x3C0F00F7,0x182A000F,0x0D0300A7,0x1012004A,0x2B8600AA,0x182900F0,0x3C0F00F7,0x182A000F,0x3C000007,0x580000B5,0x00000000,0x00000000,0x819F00A0,0x1C3700AF,0x819F0084,0x2220000F,0x919F008A,0x35D00000,0xA0000031,0x680000A1,0x429400A0,0x68000001,0x680000E1,0x40000025,0x22EA000F,0x182B0091,0x919F008A,0x42100080,0x40000004,0x2AE600AA,0x182B0081,0x40C6003E,0x182B009F,0x4631008E,0x919F00AE,0x919F0090,0x0A00000F,0x359000D0,0x39C80060,0x0D0A0010,0x3C040025,0x142C00DE,0x40400000,0x500000B1,0x500000C1,0x1C33007F,0x3C000007,0x580000A5,0x403F00F0,0x600000B1,0x600000C1,0x09000001,0x1C33007F,0x3C000007,0x580000A5,0x39860060,0x39400001,0x39820022,0x4FFF00C9,0x40000016,0x383800C3,0x5000007C,0x3C040025,0x142E00DE,0x2098000F,0x4000000A,0x3C010005,0x142E006E,0x50000021,0x50000054,0x0D030087,0x10100048,0x2B8600AA,0x182E0051,0x2262001F,0x2160000F,0x3C000007,0x182E006F,0x3C0F00F7,0x58000055,0x0D00000A,0x1C33007F,0x20EA000F,0x226300DF,0x0F1200FC,0x3C000007,0x580000E9,0x2098000F,0x39400000,0x40000016,0x3C420005,0x142F004E,0x50000021,0x2100000F,0x39820000,0x580000B1,0x580000C1,0x2098000F,0x39820020,0x3C040025,0x142F00DE,0x50000021,0x2100000F,0x39860040,0x580000B1,0x580000C1,0x819F00A0,0x1C3700AF,0x919F00AE,0x35D00000,0xA0000021,0xA31800C1,0x680000E1,0x40000000,0x919F0090,0x0A00000F,0x35D00000,0x340000B1,0x0D050021,0x819F0084,0x40000016,0x3C420005,0x1431008E,0x600000A1,0x600000B5,0x660000C5,0x20980000,0x2162000F,0x680000B9,0x680000C9,0x819F0084,0x2220000F,0x919F008A,0x35D00000,0xA0000021,0x680000A1,0x819F0090,0x68000001,0x40080005,0x22EA000F,0x18320061,0x919F008A,0x44630010,0x919F0090,0x0A00000F,0x340000B0,0x0D050010,0x3C420005,0x1433000E,0x40080000,0x600000B1,0x600000C1,0x1C33007F,0x680000A5,0x35D00000,0xA0000011,0xA4630011,0x40000000,0x919F0090,0x0A00000F,0x0F130001,0x0F0C0001,0x2E7F004E,0x3C000000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x07100000,0x2A0000EA,0x07100000,0x0D000004,0x2780001F,0x22620012,0x0A00000F,0x40000079,0x48000000,0x2E7800AF,0x1004008E,0x101B000C,0x0D0000CF,0x100200BE,0x101800A0,0x0F1A00F7,0x40000019,0x3C020005,0x1436006E,0x2AE6000C,0x2ACF008A,0x18360015,0x2BB7008E,0x0E13000F,0x0F1A00F1,0x100C00BE,0x101000CF,0x100A0080,0x0F1800F1,0x2B7B0029,0x2B7C00BA,0x2AE600CA,0x22CF000F,0x21600015,0x0A00000F,0x4400000E,0x2A7E000B,0x0D00001C,0x4FFF00F9,0x3C0000F5,0x1437008E,0x21E2001F,0x0D00004E,0x101600B0,0x2E7C005E,0x23C20004,0x2BAA00C1,0x0A00000F,0x4FFF00B9,0x400100FA,0x2E7A0080,0x2390000F,0x1010000A,0x2396000F,0x1016004A,0x2B960014,0x2BA0005A,0x2BA8004A,0x2BA9005A,0x2382000F,0x238A000F,0x0D0000EA,0x0F1A0005,0x0F1A000A,0x0A00000F,0x00000000,0x00180000,0x00460000,0x87C90000}; |
| 2955 |
#else |
| 2956 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I42[2723]; |
| 2957 |
#endif |
| 2958 |
|
| 2959 |
|
| 2960 |
/* |
| 2961 |
* id : BUF_LEN_CAL_WRITE_DSP_MEM_I43 |
| 2962 |
* type : <var> |
| 2963 |
* dsp prog i43 /RO |
| 2964 |
* location: 3 |
| 2965 |
*/ |
| 2966 |
|
| 2967 |
#ifdef PRH_DEFAULT_MODE |
| 2968 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I43=14; |
| 2969 |
#else |
| 2970 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I43; |
| 2971 |
#endif |
| 2972 |
|
| 2973 |
/* |
| 2974 |
* id : BUF_CAL_WRITE_DSP_MEM_I43 |
| 2975 |
* type : <array>[11] |
| 2976 |
* dsp prog i43 /RO |
| 2977 |
* location: 3 |
| 2978 |
*/ |
| 2979 |
|
| 2980 |
#ifdef PRH_DEFAULT_MODE |
| 2981 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I43[11]={0x8E638000,0x00000002,0x1803000F,0xBA0E0000}; |
| 2982 |
#else |
| 2983 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I43[11]; |
| 2984 |
#endif |
| 2985 |
|
| 2986 |
|
| 2987 |
/* |
| 2988 |
* id : BUF_LEN_CAL_READ_DSP_MEM_C31 |
| 2989 |
* type : <var> |
| 2990 |
* dsp prog c31 /RO |
| 2991 |
* location: 3 |
| 2992 |
*/ |
| 2993 |
|
| 2994 |
#ifdef PRH_DEFAULT_MODE |
| 2995 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C31=10; |
| 2996 |
#else |
| 2997 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C31; |
| 2998 |
#endif |
| 2999 |
|
| 3000 |
/* |
| 3001 |
* id : BUF_CAL_READ_DSP_MEM_C31 |
| 3002 |
* type : <array>[8] |
| 3003 |
* dsp prog c31 /RO |
| 3004 |
* location: 3 |
| 3005 |
*/ |
| 3006 |
|
| 3007 |
#ifdef PRH_DEFAULT_MODE |
| 3008 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_READ_DSP_MEM_C31[8]={0xA7C80000,0x14001214,0x42BB0000}; |
| 3009 |
#else |
| 3010 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_READ_DSP_MEM_C31[8]; |
| 3011 |
#endif |
| 3012 |
|
| 3013 |
|
| 3014 |
/* |
| 3015 |
* id : BUF_LEN_CAL_READ_DSP_MEM_C32 |
| 3016 |
* type : <var> |
| 3017 |
* dsp prog c32 /RO |
| 3018 |
* location: 3 |
| 3019 |
*/ |
| 3020 |
|
| 3021 |
#ifdef PRH_DEFAULT_MODE |
| 3022 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C32=10; |
| 3023 |
#else |
| 3024 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C32; |
| 3025 |
#endif |
| 3026 |
|
| 3027 |
/* |
| 3028 |
* id : BUF_CAL_READ_DSP_MEM_C32 |
| 3029 |
* type : <array>[8] |
| 3030 |
* dsp prog c32 /RO |
| 3031 |
* location: 3 |
| 3032 |
*/ |
| 3033 |
|
| 3034 |
#ifdef PRH_DEFAULT_MODE |
| 3035 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_READ_DSP_MEM_C32[8]={0xA7C80000,0x400B0420,0xD2820000}; |
| 3036 |
#else |
| 3037 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_READ_DSP_MEM_C32[8]; |
| 3038 |
#endif |
| 3039 |
|
| 3040 |
|
| 3041 |
/* |
| 3042 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I241_1 |
| 3043 |
* type : <var> |
| 3044 |
* write fpga i241_1 /RO |
| 3045 |
* location: 3 |
| 3046 |
*/ |
| 3047 |
|
| 3048 |
#ifdef PRH_DEFAULT_MODE |
| 3049 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_1=8; |
| 3050 |
#else |
| 3051 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_1; |
| 3052 |
#endif |
| 3053 |
|
| 3054 |
/* |
| 3055 |
* id : BUF_CAL_WRITE_FPGA_REG_I241_1 |
| 3056 |
* type : <array>[2] |
| 3057 |
* write fpga i241_1 /RO |
| 3058 |
* location: 3 |
| 3059 |
*/ |
| 3060 |
|
| 3061 |
#ifdef PRH_DEFAULT_MODE |
| 3062 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_1[2]={0x4D230004,0x0FFF103B}; |
| 3063 |
#else |
| 3064 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_1[2]; |
| 3065 |
#endif |
| 3066 |
|
| 3067 |
|
| 3068 |
/* |
| 3069 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I241_2 |
| 3070 |
* type : <var> |
| 3071 |
* write fpga i241_2 /RO |
| 3072 |
* location: 3 |
| 3073 |
*/ |
| 3074 |
|
| 3075 |
#ifdef PRH_DEFAULT_MODE |
| 3076 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_2=8; |
| 3077 |
#else |
| 3078 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_2; |
| 3079 |
#endif |
| 3080 |
|
| 3081 |
/* |
| 3082 |
* id : BUF_CAL_WRITE_FPGA_REG_I241_2 |
| 3083 |
* type : <array>[2] |
| 3084 |
* write fpga i241_2 /RO |
| 3085 |
* location: 3 |
| 3086 |
*/ |
| 3087 |
|
| 3088 |
#ifdef PRH_DEFAULT_MODE |
| 3089 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_2[2]={0x4D230004,0x0FFF103B}; |
| 3090 |
#else |
| 3091 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_2[2]; |
| 3092 |
#endif |
| 3093 |
|
| 3094 |
|
| 3095 |
/* |
| 3096 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I241_3 |
| 3097 |
* type : <var> |
| 3098 |
* write fpga i241_3 /RO |
| 3099 |
* location: 3 |
| 3100 |
*/ |
| 3101 |
|
| 3102 |
#ifdef PRH_DEFAULT_MODE |
| 3103 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_3=8; |
| 3104 |
#else |
| 3105 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_3; |
| 3106 |
#endif |
| 3107 |
|
| 3108 |
/* |
| 3109 |
* id : BUF_CAL_WRITE_FPGA_REG_I241_3 |
| 3110 |
* type : <array>[2] |
| 3111 |
* write fpga i241_3 /RO |
| 3112 |
* location: 3 |
| 3113 |
*/ |
| 3114 |
|
| 3115 |
#ifdef PRH_DEFAULT_MODE |
| 3116 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_3[2]={0x4D230004,0x0FEE122B}; |
| 3117 |
#else |
| 3118 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_3[2]; |
| 3119 |
#endif |
| 3120 |
|
| 3121 |
|
| 3122 |
/* |
| 3123 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I241_4 |
| 3124 |
* type : <var> |
| 3125 |
* write fpga i241_4 /RO |
| 3126 |
* location: 3 |
| 3127 |
*/ |
| 3128 |
|
| 3129 |
#ifdef PRH_DEFAULT_MODE |
| 3130 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_4=8; |
| 3131 |
#else |
| 3132 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_4; |
| 3133 |
#endif |
| 3134 |
|
| 3135 |
/* |
| 3136 |
* id : BUF_CAL_WRITE_FPGA_REG_I241_4 |
| 3137 |
* type : <array>[2] |
| 3138 |
* write fpga i241_4 /RO |
| 3139 |
* location: 3 |
| 3140 |
*/ |
| 3141 |
|
| 3142 |
#ifdef PRH_DEFAULT_MODE |
| 3143 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_4[2]={0x4D230004,0x0BFFDCFF}; |
| 3144 |
#else |
| 3145 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_4[2]; |
| 3146 |
#endif |
| 3147 |
|
| 3148 |
|
| 3149 |
/* |
| 3150 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I251_1 |
| 3151 |
* type : <var> |
| 3152 |
* write fpga i251_1 /RO |
| 3153 |
* location: 3 |
| 3154 |
*/ |
| 3155 |
|
| 3156 |
#ifdef PRH_DEFAULT_MODE |
| 3157 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_1=8; |
| 3158 |
#else |
| 3159 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_1; |
| 3160 |
#endif |
| 3161 |
|
| 3162 |
/* |
| 3163 |
* id : BUF_CAL_WRITE_FPGA_REG_I251_1 |
| 3164 |
* type : <array>[2] |
| 3165 |
* write fpga i251_1 /RO |
| 3166 |
* location: 3 |
| 3167 |
*/ |
| 3168 |
|
| 3169 |
#ifdef PRH_DEFAULT_MODE |
| 3170 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_1[2]={0x4D230005,0x007FA6BD}; |
| 3171 |
#else |
| 3172 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_1[2]; |
| 3173 |
#endif |
| 3174 |
|
| 3175 |
|
| 3176 |
/* |
| 3177 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I251_2 |
| 3178 |
* type : <var> |
| 3179 |
* write fpga i251_2 /RO |
| 3180 |
* location: 3 |
| 3181 |
*/ |
| 3182 |
|
| 3183 |
#ifdef PRH_DEFAULT_MODE |
| 3184 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_2=8; |
| 3185 |
#else |
| 3186 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_2; |
| 3187 |
#endif |
| 3188 |
|
| 3189 |
/* |
| 3190 |
* id : BUF_CAL_WRITE_FPGA_REG_I251_2 |
| 3191 |
* type : <array>[2] |
| 3192 |
* write fpga i251_2 /RO |
| 3193 |
* location: 3 |
| 3194 |
*/ |
| 3195 |
|
| 3196 |
#ifdef PRH_DEFAULT_MODE |
| 3197 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_2[2]={0x4D230005,0x007FA6BD}; |
| 3198 |
#else |
| 3199 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_2[2]; |
| 3200 |
#endif |
| 3201 |
|
| 3202 |
|
| 3203 |
/* |
| 3204 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I251_3 |
| 3205 |
* type : <var> |
| 3206 |
* write fpga i251_3 /RO |
| 3207 |
* location: 3 |
| 3208 |
*/ |
| 3209 |
|
| 3210 |
#ifdef PRH_DEFAULT_MODE |
| 3211 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_3=8; |
| 3212 |
#else |
| 3213 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_3; |
| 3214 |
#endif |
| 3215 |
|
| 3216 |
/* |
| 3217 |
* id : BUF_CAL_WRITE_FPGA_REG_I251_3 |
| 3218 |
* type : <array>[2] |
| 3219 |
* write fpga i251_3 /RO |
| 3220 |
* location: 3 |
| 3221 |
*/ |
| 3222 |
|
| 3223 |
#ifdef PRH_DEFAULT_MODE |
| 3224 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_3[2]={0x4D230005,0x007FA6BD}; |
| 3225 |
#else |
| 3226 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_3[2]; |
| 3227 |
#endif |
| 3228 |
|
| 3229 |
|
| 3230 |
/* |
| 3231 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I251_4 |
| 3232 |
* type : <var> |
| 3233 |
* write fpga i251_4 /RO |
| 3234 |
* location: 3 |
| 3235 |
*/ |
| 3236 |
|
| 3237 |
#ifdef PRH_DEFAULT_MODE |
| 3238 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_4=8; |
| 3239 |
#else |
| 3240 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_4; |
| 3241 |
#endif |
| 3242 |
|
| 3243 |
/* |
| 3244 |
* id : BUF_CAL_WRITE_FPGA_REG_I251_4 |
| 3245 |
* type : <array>[2] |
| 3246 |
* write fpga i251_4 /RO |
| 3247 |
* location: 3 |
| 3248 |
*/ |
| 3249 |
|
| 3250 |
#ifdef PRH_DEFAULT_MODE |
| 3251 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_4[2]={0x4D230005,0x007FA6BD}; |
| 3252 |
#else |
| 3253 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_4[2]; |
| 3254 |
#endif |
| 3255 |
|
| 3256 |
|
| 3257 |
/* |
| 3258 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I261_1 |
| 3259 |
* type : <var> |
| 3260 |
* write fpga i261_1 /RO |
| 3261 |
* location: 3 |
| 3262 |
*/ |
| 3263 |
|
| 3264 |
#ifdef PRH_DEFAULT_MODE |
| 3265 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_1=8; |
| 3266 |
#else |
| 3267 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_1; |
| 3268 |
#endif |
| 3269 |
|
| 3270 |
/* |
| 3271 |
* id : BUF_CAL_WRITE_FPGA_REG_I261_1 |
| 3272 |
* type : <array>[2] |
| 3273 |
* write fpga i261_1 /RO |
| 3274 |
* location: 3 |
| 3275 |
*/ |
| 3276 |
|
| 3277 |
#ifdef PRH_DEFAULT_MODE |
| 3278 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_1[2]={0x4D230002,0x0D55D059}; |
| 3279 |
#else |
| 3280 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_1[2]; |
| 3281 |
#endif |
| 3282 |
|
| 3283 |
|
| 3284 |
/* |
| 3285 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I261_2 |
| 3286 |
* type : <var> |
| 3287 |
* write fpga i261_2 /RO |
| 3288 |
* location: 3 |
| 3289 |
*/ |
| 3290 |
|
| 3291 |
#ifdef PRH_DEFAULT_MODE |
| 3292 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_2=8; |
| 3293 |
#else |
| 3294 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_2; |
| 3295 |
#endif |
| 3296 |
|
| 3297 |
/* |
| 3298 |
* id : BUF_CAL_WRITE_FPGA_REG_I261_2 |
| 3299 |
* type : <array>[2] |
| 3300 |
* write fpga i261_2 /RO |
| 3301 |
* location: 3 |
| 3302 |
*/ |
| 3303 |
|
| 3304 |
#ifdef PRH_DEFAULT_MODE |
| 3305 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_2[2]={0x4D230002,0x0D55D059}; |
| 3306 |
#else |
| 3307 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_2[2]; |
| 3308 |
#endif |
| 3309 |
|
| 3310 |
|
| 3311 |
/* |
| 3312 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I261_3 |
| 3313 |
* type : <var> |
| 3314 |
* write fpga i261_3 /RO |
| 3315 |
* location: 3 |
| 3316 |
*/ |
| 3317 |
|
| 3318 |
#ifdef PRH_DEFAULT_MODE |
| 3319 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_3=8; |
| 3320 |
#else |
| 3321 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_3; |
| 3322 |
#endif |
| 3323 |
|
| 3324 |
/* |
| 3325 |
* id : BUF_CAL_WRITE_FPGA_REG_I261_3 |
| 3326 |
* type : <array>[2] |
| 3327 |
* write fpga i261_3 /RO |
| 3328 |
* location: 3 |
| 3329 |
*/ |
| 3330 |
|
| 3331 |
#ifdef PRH_DEFAULT_MODE |
| 3332 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_3[2]={0x4D230002,0x0D55D059}; |
| 3333 |
#else |
| 3334 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_3[2]; |
| 3335 |
#endif |
| 3336 |
|
| 3337 |
|
| 3338 |
/* |
| 3339 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I261_4 |
| 3340 |
* type : <var> |
| 3341 |
* write fpga i261_4 /RO |
| 3342 |
* location: 3 |
| 3343 |
*/ |
| 3344 |
|
| 3345 |
#ifdef PRH_DEFAULT_MODE |
| 3346 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_4=8; |
| 3347 |
#else |
| 3348 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_4; |
| 3349 |
#endif |
| 3350 |
|
| 3351 |
/* |
| 3352 |
* id : BUF_CAL_WRITE_FPGA_REG_I261_4 |
| 3353 |
* type : <array>[2] |
| 3354 |
* write fpga i261_4 /RO |
| 3355 |
* location: 3 |
| 3356 |
*/ |
| 3357 |
|
| 3358 |
#ifdef PRH_DEFAULT_MODE |
| 3359 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_4[2]={0x4D230002,0x0D55D059}; |
| 3360 |
#else |
| 3361 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_4[2]; |
| 3362 |
#endif |
| 3363 |
|
| 3364 |
|
| 3365 |
/* |
| 3366 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I260_1 |
| 3367 |
* type : <var> |
| 3368 |
* write fpga i260_1 /RO |
| 3369 |
* location: 3 |
| 3370 |
*/ |
| 3371 |
|
| 3372 |
#ifdef PRH_DEFAULT_MODE |
| 3373 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_1=8; |
| 3374 |
#else |
| 3375 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_1; |
| 3376 |
#endif |
| 3377 |
|
| 3378 |
/* |
| 3379 |
* id : BUF_CAL_WRITE_FPGA_REG_I260_1 |
| 3380 |
* type : <array>[2] |
| 3381 |
* write fpga i260_1 /RO |
| 3382 |
* location: 3 |
| 3383 |
*/ |
| 3384 |
|
| 3385 |
#ifdef PRH_DEFAULT_MODE |
| 3386 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_1[2]={0x4D230002,0x055559F0}; |
| 3387 |
#else |
| 3388 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_1[2]; |
| 3389 |
#endif |
| 3390 |
|
| 3391 |
|
| 3392 |
/* |
| 3393 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I260_2 |
| 3394 |
* type : <var> |
| 3395 |
* write fpga i260_2 /RO |
| 3396 |
* location: 3 |
| 3397 |
*/ |
| 3398 |
|
| 3399 |
#ifdef PRH_DEFAULT_MODE |
| 3400 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_2=8; |
| 3401 |
#else |
| 3402 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_2; |
| 3403 |
#endif |
| 3404 |
|
| 3405 |
/* |
| 3406 |
* id : BUF_CAL_WRITE_FPGA_REG_I260_2 |
| 3407 |
* type : <array>[2] |
| 3408 |
* write fpga i260_2 /RO |
| 3409 |
* location: 3 |
| 3410 |
*/ |
| 3411 |
|
| 3412 |
#ifdef PRH_DEFAULT_MODE |
| 3413 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_2[2]={0x4D230002,0x055559F0}; |
| 3414 |
#else |
| 3415 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_2[2]; |
| 3416 |
#endif |
| 3417 |
|
| 3418 |
|
| 3419 |
/* |
| 3420 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I260_3 |
| 3421 |
* type : <var> |
| 3422 |
* write fpga i260_3 /RO |
| 3423 |
* location: 3 |
| 3424 |
*/ |
| 3425 |
|
| 3426 |
#ifdef PRH_DEFAULT_MODE |
| 3427 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_3=8; |
| 3428 |
#else |
| 3429 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_3; |
| 3430 |
#endif |
| 3431 |
|
| 3432 |
/* |
| 3433 |
* id : BUF_CAL_WRITE_FPGA_REG_I260_3 |
| 3434 |
* type : <array>[2] |
| 3435 |
* write fpga i260_3 /RO |
| 3436 |
* location: 3 |
| 3437 |
*/ |
| 3438 |
|
| 3439 |
#ifdef PRH_DEFAULT_MODE |
| 3440 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_3[2]={0x4D230002,0x055559F0}; |
| 3441 |
#else |
| 3442 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_3[2]; |
| 3443 |
#endif |
| 3444 |
|
| 3445 |
|
| 3446 |
/* |
| 3447 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I260_4 |
| 3448 |
* type : <var> |
| 3449 |
* write fpga i260_4 /RO |
| 3450 |
* location: 3 |
| 3451 |
*/ |
| 3452 |
|
| 3453 |
#ifdef PRH_DEFAULT_MODE |
| 3454 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_4=8; |
| 3455 |
#else |
| 3456 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_4; |
| 3457 |
#endif |
| 3458 |
|
| 3459 |
/* |
| 3460 |
* id : BUF_CAL_WRITE_FPGA_REG_I260_4 |
| 3461 |
* type : <array>[2] |
| 3462 |
* write fpga i260_4 /RO |
| 3463 |
* location: 3 |
| 3464 |
*/ |
| 3465 |
|
| 3466 |
#ifdef PRH_DEFAULT_MODE |
| 3467 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_4[2]={0x4D230002,0x055559F0}; |
| 3468 |
#else |
| 3469 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_4[2]; |
| 3470 |
#endif |
| 3471 |
|
| 3472 |
|
| 3473 |
/* |
| 3474 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I311_1 |
| 3475 |
* type : <var> |
| 3476 |
* write fpga i311_1 /RO |
| 3477 |
* location: 3 |
| 3478 |
*/ |
| 3479 |
|
| 3480 |
#ifdef PRH_DEFAULT_MODE |
| 3481 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_1=8; |
| 3482 |
#else |
| 3483 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_1; |
| 3484 |
#endif |
| 3485 |
|
| 3486 |
/* |
| 3487 |
* id : BUF_CAL_WRITE_FPGA_REG_I311_1 |
| 3488 |
* type : <array>[2] |
| 3489 |
* write fpga i311_1 /RO |
| 3490 |
* location: 3 |
| 3491 |
*/ |
| 3492 |
|
| 3493 |
#ifdef PRH_DEFAULT_MODE |
| 3494 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_1[2]={0x4D230002,0x0FFFA29B}; |
| 3495 |
#else |
| 3496 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_1[2]; |
| 3497 |
#endif |
| 3498 |
|
| 3499 |
|
| 3500 |
/* |
| 3501 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I311_2 |
| 3502 |
* type : <var> |
| 3503 |
* write fpga i311_2 /RO |
| 3504 |
* location: 3 |
| 3505 |
*/ |
| 3506 |
|
| 3507 |
#ifdef PRH_DEFAULT_MODE |
| 3508 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_2=8; |
| 3509 |
#else |
| 3510 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_2; |
| 3511 |
#endif |
| 3512 |
|
| 3513 |
/* |
| 3514 |
* id : BUF_CAL_WRITE_FPGA_REG_I311_2 |
| 3515 |
* type : <array>[2] |
| 3516 |
* write fpga i311_2 /RO |
| 3517 |
* location: 3 |
| 3518 |
*/ |
| 3519 |
|
| 3520 |
#ifdef PRH_DEFAULT_MODE |
| 3521 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_2[2]={0x4D230002,0x0FFFA29B}; |
| 3522 |
#else |
| 3523 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_2[2]; |
| 3524 |
#endif |
| 3525 |
|
| 3526 |
|
| 3527 |
/* |
| 3528 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I311_3 |
| 3529 |
* type : <var> |
| 3530 |
* write fpga i311_3 /RO |
| 3531 |
* location: 3 |
| 3532 |
*/ |
| 3533 |
|
| 3534 |
#ifdef PRH_DEFAULT_MODE |
| 3535 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_3=8; |
| 3536 |
#else |
| 3537 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_3; |
| 3538 |
#endif |
| 3539 |
|
| 3540 |
/* |
| 3541 |
* id : BUF_CAL_WRITE_FPGA_REG_I311_3 |
| 3542 |
* type : <array>[2] |
| 3543 |
* write fpga i311_3 /RO |
| 3544 |
* location: 3 |
| 3545 |
*/ |
| 3546 |
|
| 3547 |
#ifdef PRH_DEFAULT_MODE |
| 3548 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_3[2]={0x4D230002,0x0FFFA29B}; |
| 3549 |
#else |
| 3550 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_3[2]; |
| 3551 |
#endif |
| 3552 |
|
| 3553 |
|
| 3554 |
/* |
| 3555 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I311_4 |
| 3556 |
* type : <var> |
| 3557 |
* write fpga i311_4 /RO |
| 3558 |
* location: 3 |
| 3559 |
*/ |
| 3560 |
|
| 3561 |
#ifdef PRH_DEFAULT_MODE |
| 3562 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_4=8; |
| 3563 |
#else |
| 3564 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_4; |
| 3565 |
#endif |
| 3566 |
|
| 3567 |
/* |
| 3568 |
* id : BUF_CAL_WRITE_FPGA_REG_I311_4 |
| 3569 |
* type : <array>[2] |
| 3570 |
* write fpga i311_4 /RO |
| 3571 |
* location: 3 |
| 3572 |
*/ |
| 3573 |
|
| 3574 |
#ifdef PRH_DEFAULT_MODE |
| 3575 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_4[2]={0x4D230002,0x0FFFA29B}; |
| 3576 |
#else |
| 3577 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_4[2]; |
| 3578 |
#endif |
| 3579 |
|
| 3580 |
|
| 3581 |
/* |
| 3582 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I310_1 |
| 3583 |
* type : <var> |
| 3584 |
* write fpga i310_1 /RO |
| 3585 |
* location: 3 |
| 3586 |
*/ |
| 3587 |
|
| 3588 |
#ifdef PRH_DEFAULT_MODE |
| 3589 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_1=8; |
| 3590 |
#else |
| 3591 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_1; |
| 3592 |
#endif |
| 3593 |
|
| 3594 |
/* |
| 3595 |
* id : BUF_CAL_WRITE_FPGA_REG_I310_1 |
| 3596 |
* type : <array>[2] |
| 3597 |
* write fpga i310_1 /RO |
| 3598 |
* location: 3 |
| 3599 |
*/ |
| 3600 |
|
| 3601 |
#ifdef PRH_DEFAULT_MODE |
| 3602 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_1[2]={0x4D230002,0x07FF2B32}; |
| 3603 |
#else |
| 3604 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_1[2]; |
| 3605 |
#endif |
| 3606 |
|
| 3607 |
|
| 3608 |
/* |
| 3609 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I310_2 |
| 3610 |
* type : <var> |
| 3611 |
* write fpga i310_2 /RO |
| 3612 |
* location: 3 |
| 3613 |
*/ |
| 3614 |
|
| 3615 |
#ifdef PRH_DEFAULT_MODE |
| 3616 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_2=8; |
| 3617 |
#else |
| 3618 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_2; |
| 3619 |
#endif |
| 3620 |
|
| 3621 |
/* |
| 3622 |
* id : BUF_CAL_WRITE_FPGA_REG_I310_2 |
| 3623 |
* type : <array>[2] |
| 3624 |
* write fpga i310_2 /RO |
| 3625 |
* location: 3 |
| 3626 |
*/ |
| 3627 |
|
| 3628 |
#ifdef PRH_DEFAULT_MODE |
| 3629 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_2[2]={0x4D230002,0x07FF2B32}; |
| 3630 |
#else |
| 3631 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_2[2]; |
| 3632 |
#endif |
| 3633 |
|
| 3634 |
|
| 3635 |
/* |
| 3636 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I310_3 |
| 3637 |
* type : <var> |
| 3638 |
* write fpga i310_3 /RO |
| 3639 |
* location: 3 |
| 3640 |
*/ |
| 3641 |
|
| 3642 |
#ifdef PRH_DEFAULT_MODE |
| 3643 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_3=8; |
| 3644 |
#else |
| 3645 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_3; |
| 3646 |
#endif |
| 3647 |
|
| 3648 |
/* |
| 3649 |
* id : BUF_CAL_WRITE_FPGA_REG_I310_3 |
| 3650 |
* type : <array>[2] |
| 3651 |
* write fpga i310_3 /RO |
| 3652 |
* location: 3 |
| 3653 |
*/ |
| 3654 |
|
| 3655 |
#ifdef PRH_DEFAULT_MODE |
| 3656 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_3[2]={0x4D230002,0x07FF2B32}; |
| 3657 |
#else |
| 3658 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_3[2]; |
| 3659 |
#endif |
| 3660 |
|
| 3661 |
|
| 3662 |
/* |
| 3663 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I310_4 |
| 3664 |
* type : <var> |
| 3665 |
* write fpga i310_4 /RO |
| 3666 |
* location: 3 |
| 3667 |
*/ |
| 3668 |
|
| 3669 |
#ifdef PRH_DEFAULT_MODE |
| 3670 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_4=8; |
| 3671 |
#else |
| 3672 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_4; |
| 3673 |
#endif |
| 3674 |
|
| 3675 |
/* |
| 3676 |
* id : BUF_CAL_WRITE_FPGA_REG_I310_4 |
| 3677 |
* type : <array>[2] |
| 3678 |
* write fpga i310_4 /RO |
| 3679 |
* location: 3 |
| 3680 |
*/ |
| 3681 |
|
| 3682 |
#ifdef PRH_DEFAULT_MODE |
| 3683 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_4[2]={0x4D230002,0x07FF2B32}; |
| 3684 |
#else |
| 3685 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_4[2]; |
| 3686 |
#endif |
| 3687 |
|
| 3688 |
|
| 3689 |
/* |
| 3690 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I321 |
| 3691 |
* type : <var> |
| 3692 |
* write fpga i321 /RO |
| 3693 |
* location: 3 |
| 3694 |
*/ |
| 3695 |
|
| 3696 |
#ifdef PRH_DEFAULT_MODE |
| 3697 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I321=8; |
| 3698 |
#else |
| 3699 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I321; |
| 3700 |
#endif |
| 3701 |
|
| 3702 |
/* |
| 3703 |
* id : BUF_CAL_WRITE_FPGA_REG_I321 |
| 3704 |
* type : <array>[2] |
| 3705 |
* write fpga i321 /RO |
| 3706 |
* location: 3 |
| 3707 |
*/ |
| 3708 |
|
| 3709 |
#ifdef PRH_DEFAULT_MODE |
| 3710 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I321[2]={0x4D230000,0x8001C98C}; |
| 3711 |
#else |
| 3712 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I321[2]; |
| 3713 |
#endif |
| 3714 |
|
| 3715 |
|
| 3716 |
/* |
| 3717 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I331_1 |
| 3718 |
* type : <var> |
| 3719 |
* write fpga i331_1 /RO |
| 3720 |
* location: 3 |
| 3721 |
*/ |
| 3722 |
|
| 3723 |
#ifdef PRH_DEFAULT_MODE |
| 3724 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_1=8; |
| 3725 |
#else |
| 3726 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_1; |
| 3727 |
#endif |
| 3728 |
|
| 3729 |
/* |
| 3730 |
* id : BUF_CAL_WRITE_FPGA_REG_I331_1 |
| 3731 |
* type : <array>[2] |
| 3732 |
* write fpga i331_1 /RO |
| 3733 |
* location: 3 |
| 3734 |
*/ |
| 3735 |
|
| 3736 |
#ifdef PRH_DEFAULT_MODE |
| 3737 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_1[2]={0x4D230006,0x07FFF7F2}; |
| 3738 |
#else |
| 3739 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_1[2]; |
| 3740 |
#endif |
| 3741 |
|
| 3742 |
|
| 3743 |
/* |
| 3744 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I331_2 |
| 3745 |
* type : <var> |
| 3746 |
* write fpga i331_2 /RO |
| 3747 |
* location: 3 |
| 3748 |
*/ |
| 3749 |
|
| 3750 |
#ifdef PRH_DEFAULT_MODE |
| 3751 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_2=8; |
| 3752 |
#else |
| 3753 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_2; |
| 3754 |
#endif |
| 3755 |
|
| 3756 |
/* |
| 3757 |
* id : BUF_CAL_WRITE_FPGA_REG_I331_2 |
| 3758 |
* type : <array>[2] |
| 3759 |
* write fpga i331_2 /RO |
| 3760 |
* location: 3 |
| 3761 |
*/ |
| 3762 |
|
| 3763 |
#ifdef PRH_DEFAULT_MODE |
| 3764 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_2[2]={0x4D230006,0x07FFF7F2}; |
| 3765 |
#else |
| 3766 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_2[2]; |
| 3767 |
#endif |
| 3768 |
|
| 3769 |
|
| 3770 |
/* |
| 3771 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I331_3 |
| 3772 |
* type : <var> |
| 3773 |
* write fpga i331_3 /RO |
| 3774 |
* location: 3 |
| 3775 |
*/ |
| 3776 |
|
| 3777 |
#ifdef PRH_DEFAULT_MODE |
| 3778 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_3=8; |
| 3779 |
#else |
| 3780 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_3; |
| 3781 |
#endif |
| 3782 |
|
| 3783 |
/* |
| 3784 |
* id : BUF_CAL_WRITE_FPGA_REG_I331_3 |
| 3785 |
* type : <array>[2] |
| 3786 |
* write fpga i331_3 /RO |
| 3787 |
* location: 3 |
| 3788 |
*/ |
| 3789 |
|
| 3790 |
#ifdef PRH_DEFAULT_MODE |
| 3791 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_3[2]={0x4D230006,0x07FFF7F2}; |
| 3792 |
#else |
| 3793 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_3[2]; |
| 3794 |
#endif |
| 3795 |
|
| 3796 |
|
| 3797 |
/* |
| 3798 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I331_4 |
| 3799 |
* type : <var> |
| 3800 |
* write fpga i331_4 /RO |
| 3801 |
* location: 3 |
| 3802 |
*/ |
| 3803 |
|
| 3804 |
#ifdef PRH_DEFAULT_MODE |
| 3805 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_4=8; |
| 3806 |
#else |
| 3807 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_4; |
| 3808 |
#endif |
| 3809 |
|
| 3810 |
/* |
| 3811 |
* id : BUF_CAL_WRITE_FPGA_REG_I331_4 |
| 3812 |
* type : <array>[2] |
| 3813 |
* write fpga i331_4 /RO |
| 3814 |
* location: 3 |
| 3815 |
*/ |
| 3816 |
|
| 3817 |
#ifdef PRH_DEFAULT_MODE |
| 3818 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_4[2]={0x4D230006,0x07FFF7F2}; |
| 3819 |
#else |
| 3820 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_4[2]; |
| 3821 |
#endif |
| 3822 |
|
| 3823 |
|
| 3824 |
/* |
| 3825 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_OFF |
| 3826 |
* type : <var> |
| 3827 |
* write fpga reg off /RO |
| 3828 |
* location: 3 |
| 3829 |
*/ |
| 3830 |
|
| 3831 |
#ifdef PRH_DEFAULT_MODE |
| 3832 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_OFF=8; |
| 3833 |
#else |
| 3834 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_OFF; |
| 3835 |
#endif |
| 3836 |
|
| 3837 |
/* |
| 3838 |
* id : BUF_CAL_WRITE_FPGA_REG_OFF |
| 3839 |
* type : <array>[2] |
| 3840 |
* write fpga reg off /RO |
| 3841 |
* location: 3 |
| 3842 |
*/ |
| 3843 |
|
| 3844 |
#ifdef PRH_DEFAULT_MODE |
| 3845 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_OFF[2]={0x4D230002,0x0000AC55}; |
| 3846 |
#else |
| 3847 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_OFF[2]; |
| 3848 |
#endif |
| 3849 |
|
| 3850 |
|
| 3851 |
/* |
| 3852 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I341_1 |
| 3853 |
* type : <var> |
| 3854 |
* write fpga i341_1 /RO |
| 3855 |
* location: 3 |
| 3856 |
*/ |
| 3857 |
|
| 3858 |
#ifdef PRH_DEFAULT_MODE |
| 3859 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_1=8; |
| 3860 |
#else |
| 3861 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_1; |
| 3862 |
#endif |
| 3863 |
|
| 3864 |
/* |
| 3865 |
* id : BUF_CAL_WRITE_FPGA_REG_I341_1 |
| 3866 |
* type : <array>[2] |
| 3867 |
* write fpga i341_1 /RO |
| 3868 |
* location: 3 |
| 3869 |
*/ |
| 3870 |
|
| 3871 |
#ifdef PRH_DEFAULT_MODE |
| 3872 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_1[2]={0x4D230004,0x0FFF103B}; |
| 3873 |
#else |
| 3874 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_1[2]; |
| 3875 |
#endif |
| 3876 |
|
| 3877 |
|
| 3878 |
/* |
| 3879 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I341_2 |
| 3880 |
* type : <var> |
| 3881 |
* write fpga i341_2 /RO |
| 3882 |
* location: 3 |
| 3883 |
*/ |
| 3884 |
|
| 3885 |
#ifdef PRH_DEFAULT_MODE |
| 3886 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_2=8; |
| 3887 |
#else |
| 3888 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_2; |
| 3889 |
#endif |
| 3890 |
|
| 3891 |
/* |
| 3892 |
* id : BUF_CAL_WRITE_FPGA_REG_I341_2 |
| 3893 |
* type : <array>[2] |
| 3894 |
* write fpga i341_2 /RO |
| 3895 |
* location: 3 |
| 3896 |
*/ |
| 3897 |
|
| 3898 |
#ifdef PRH_DEFAULT_MODE |
| 3899 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_2[2]={0x4D230004,0x0FFF103B}; |
| 3900 |
#else |
| 3901 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_2[2]; |
| 3902 |
#endif |
| 3903 |
|
| 3904 |
|
| 3905 |
/* |
| 3906 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I341_3 |
| 3907 |
* type : <var> |
| 3908 |
* write fpga i341_3 /RO |
| 3909 |
* location: 3 |
| 3910 |
*/ |
| 3911 |
|
| 3912 |
#ifdef PRH_DEFAULT_MODE |
| 3913 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_3=8; |
| 3914 |
#else |
| 3915 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_3; |
| 3916 |
#endif |
| 3917 |
|
| 3918 |
/* |
| 3919 |
* id : BUF_CAL_WRITE_FPGA_REG_I341_3 |
| 3920 |
* type : <array>[2] |
| 3921 |
* write fpga i341_3 /RO |
| 3922 |
* location: 3 |
| 3923 |
*/ |
| 3924 |
|
| 3925 |
#ifdef PRH_DEFAULT_MODE |
| 3926 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_3[2]={0x4D230004,0x0FEE122B}; |
| 3927 |
#else |
| 3928 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_3[2]; |
| 3929 |
#endif |
| 3930 |
|
| 3931 |
|
| 3932 |
/* |
| 3933 |
* id : BUF_LEN_CAL_WRITE_FPGA_REG_I341_4 |
| 3934 |
* type : <var> |
| 3935 |
* write fpga i341_4 /RO |
| 3936 |
* location: 3 |
| 3937 |
*/ |
| 3938 |
|
| 3939 |
#ifdef PRH_DEFAULT_MODE |
| 3940 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_4=8; |
| 3941 |
#else |
| 3942 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_4; |
| 3943 |
#endif |
| 3944 |
|
| 3945 |
/* |
| 3946 |
* id : BUF_CAL_WRITE_FPGA_REG_I341_4 |
| 3947 |
* type : <array>[2] |
| 3948 |
* write fpga i341_4 /RO |
| 3949 |
* location: 3 |
| 3950 |
*/ |
| 3951 |
|
| 3952 |
#ifdef PRH_DEFAULT_MODE |
| 3953 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_4[2]={0x4D230004,0x0BFFDCFF}; |
| 3954 |
#else |
| 3955 |
PRH_VAR_TYPE PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_4[2]; |
| 3956 |
#endif |
| 3957 |
|
| 3958 |
|
| 3959 |
/* |
| 3960 |
* --------- AC Anticoincidence : ------------- |
| 3961 |
*/ |
| 3962 |
|
| 3963 |
|
| 3964 |
/* |
| 3965 |
* id : AC_1_OK |
| 3966 |
* type : <var> |
| 3967 |
* AC ON_OFF in ACQ /RW |
| 3968 |
* location: 3 |
| 3969 |
*/ |
| 3970 |
|
| 3971 |
#ifdef PRH_DEFAULT_MODE |
| 3972 |
PRH_VAR_TYPE PRH_VAR_AC_1_OK=1; |
| 3973 |
#else |
| 3974 |
PRH_VAR_TYPE PRH_VAR_AC_1_OK; |
| 3975 |
#endif |
| 3976 |
|
| 3977 |
/* |
| 3978 |
* id : AC_2_OK |
| 3979 |
* type : <var> |
| 3980 |
* AC ON_OFF in ACQ /RW |
| 3981 |
* location: 3 |
| 3982 |
*/ |
| 3983 |
|
| 3984 |
#ifdef PRH_DEFAULT_MODE |
| 3985 |
PRH_VAR_TYPE PRH_VAR_AC_2_OK=1; |
| 3986 |
#else |
| 3987 |
PRH_VAR_TYPE PRH_VAR_AC_2_OK; |
| 3988 |
#endif |
| 3989 |
|
| 3990 |
/* |
| 3991 |
* id : AC_1_CHECK |
| 3992 |
* type : <var> |
| 3993 |
* AC check /RO |
| 3994 |
* location: 3 |
| 3995 |
*/ |
| 3996 |
|
| 3997 |
#ifdef PRH_DEFAULT_MODE |
| 3998 |
PRH_VAR_TYPE PRH_VAR_AC_1_CHECK=0; |
| 3999 |
#else |
| 4000 |
PRH_VAR_TYPE PRH_VAR_AC_1_CHECK; |
| 4001 |
#endif |
| 4002 |
|
| 4003 |
/* |
| 4004 |
* id : AC_2_CHECK |
| 4005 |
* type : <var> |
| 4006 |
* AC check /RO |
| 4007 |
* location: 3 |
| 4008 |
*/ |
| 4009 |
|
| 4010 |
#ifdef PRH_DEFAULT_MODE |
| 4011 |
PRH_VAR_TYPE PRH_VAR_AC_2_CHECK=0; |
| 4012 |
#else |
| 4013 |
PRH_VAR_TYPE PRH_VAR_AC_2_CHECK; |
| 4014 |
#endif |
| 4015 |
|
| 4016 |
/* |
| 4017 |
* id : AC_LOOP |
| 4018 |
* type : <var> |
| 4019 |
* AC max loop /RO |
| 4020 |
* location: 3 |
| 4021 |
*/ |
| 4022 |
|
| 4023 |
#ifdef PRH_DEFAULT_MODE |
| 4024 |
PRH_VAR_TYPE PRH_VAR_AC_LOOP=3; |
| 4025 |
#else |
| 4026 |
PRH_VAR_TYPE PRH_VAR_AC_LOOP; |
| 4027 |
#endif |
| 4028 |
|
| 4029 |
/* |
| 4030 |
* id : AC_LOOP2 |
| 4031 |
* type : <var> |
| 4032 |
* AC max loop 2 /RO |
| 4033 |
* location: 3 |
| 4034 |
*/ |
| 4035 |
|
| 4036 |
#ifdef PRH_DEFAULT_MODE |
| 4037 |
PRH_VAR_TYPE PRH_VAR_AC_LOOP2=3; |
| 4038 |
#else |
| 4039 |
PRH_VAR_TYPE PRH_VAR_AC_LOOP2; |
| 4040 |
#endif |
| 4041 |
|
| 4042 |
/* |
| 4043 |
* id : BUF_LEN_AC_1_SET_DAQ |
| 4044 |
* type : <var> |
| 4045 |
* SET DAQ command /RO |
| 4046 |
* location: 3 |
| 4047 |
*/ |
| 4048 |
|
| 4049 |
#ifdef PRH_DEFAULT_MODE |
| 4050 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_1_SET_DAQ=132; |
| 4051 |
#else |
| 4052 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_1_SET_DAQ; |
| 4053 |
#endif |
| 4054 |
|
| 4055 |
/* |
| 4056 |
* id : BUF_AC_1_SET_DAQ |
| 4057 |
* type : <array>[35] |
| 4058 |
* SET DAQ command /RO |
| 4059 |
* location: 3 |
| 4060 |
*/ |
| 4061 |
|
| 4062 |
#ifdef PRH_DEFAULT_MODE |
| 4063 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_1_SET_DAQ[35]={0x008A0000,0x000EFFFF,0xFFFF0001,0x0023FFFF,0xFFFF0002,0x0021FFFF,0xFFFF0003,0x0021FFFF,0xFFFF0004,0x0018FFFF,0xFFFF0005,0x002DFFFF,0xFFFF0006,0x0020FFFF,0xFFFF0007,0x0020FFFF,0xFFFF0008,0x0012FFFF,0xFFFF0009,0x0019FFFF,0xFFFF000A,0x001BFFFF,0xFFFF000B,0x001BFFFF,0xFFFF000C,0x0014FFFF,0xFFFF000D,0x0043FFFF,0xFFFF000E,0x0023FFFF,0xFFFF000F,0x0023FFFF,0xFFFF0D95}; |
| 4064 |
#else |
| 4065 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_1_SET_DAQ[35]; |
| 4066 |
#endif |
| 4067 |
|
| 4068 |
|
| 4069 |
/* |
| 4070 |
* id : BUF_LEN_AC_2_SET_DAQ |
| 4071 |
* type : <var> |
| 4072 |
* SET DAQ command /RO |
| 4073 |
* location: 3 |
| 4074 |
*/ |
| 4075 |
|
| 4076 |
#ifdef PRH_DEFAULT_MODE |
| 4077 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_2_SET_DAQ=132; |
| 4078 |
#else |
| 4079 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_2_SET_DAQ; |
| 4080 |
#endif |
| 4081 |
|
| 4082 |
/* |
| 4083 |
* id : BUF_AC_2_SET_DAQ |
| 4084 |
* type : <array>[35] |
| 4085 |
* SET DAQ command /RO |
| 4086 |
* location: 3 |
| 4087 |
*/ |
| 4088 |
|
| 4089 |
#ifdef PRH_DEFAULT_MODE |
| 4090 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_2_SET_DAQ[35]={0x008A0000,0x0020FFFF,0xFFFF0001,0x001BFFFF,0xFFFF0002,0x003AFFFF,0xFFFF0003,0x003AFFFF,0xFFFF0004,0x0015FFFF,0xFFFF0005,0x001CFFFF,0xFFFF0006,0x0014FFFF,0xFFFF0007,0x0014FFFF,0xFFFF0008,0x001CFFFF,0xFFFF0009,0x0039FFFF,0xFFFF000A,0x0010FFFF,0xFFFF000B,0x0010FFFF,0xFFFF000C,0x0019FFFF,0xFFFF000D,0x0012FFFF,0xFFFF000E,0x001AFFFF,0xFFFF000F,0x001AFFFF,0xFFFFAE20}; |
| 4091 |
#else |
| 4092 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_2_SET_DAQ[35]; |
| 4093 |
#endif |
| 4094 |
|
| 4095 |
|
| 4096 |
/* |
| 4097 |
* id : BUF_LEN_AC_SEND_DSP_PROG1 |
| 4098 |
* type : <var> |
| 4099 |
* DSP Program 1 /RO |
| 4100 |
* location: 1 |
| 4101 |
*/ |
| 4102 |
|
| 4103 |
#ifdef PRH_DEFAULT_MODE |
| 4104 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_SEND_DSP_PROG1=17034; |
| 4105 |
#else |
| 4106 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_SEND_DSP_PROG1; |
| 4107 |
#endif |
| 4108 |
|
| 4109 |
/* |
| 4110 |
* id : BUF_AC_SEND_DSP_PROG1 |
| 4111 |
* type : <array>[5010] |
| 4112 |
* DSP Program 1 /RO |
| 4113 |
* location: 1 |
| 4114 |
*/ |
| 4115 |
|
| 4116 |
#ifdef PRH_DEFAULT_MODE |
| 4117 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_SEND_DSP_PROG1[5010]={0x00884000,0x80002140,0x00610064,0x00690000,0x00000000,0x0000079F,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00220000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000FFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x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|
| 4118 |
#else |
| 4119 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_SEND_DSP_PROG1[5010]; |
| 4120 |
#endif |
| 4121 |
|
| 4122 |
|
| 4123 |
/* |
| 4124 |
* id : BUF_LEN_AC_1_SEND_DSP_PROG2 |
| 4125 |
* type : <var> |
| 4126 |
* /RO |
| 4127 |
* location: 1 |
| 4128 |
*/ |
| 4129 |
|
| 4130 |
#ifdef PRH_DEFAULT_MODE |
| 4131 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_1_SEND_DSP_PROG2=11156; |
| 4132 |
#else |
| 4133 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_1_SEND_DSP_PROG2; |
| 4134 |
#endif |
| 4135 |
|
| 4136 |
/* |
| 4137 |
* id : BUF_AC_1_SEND_DSP_PROG2 |
| 4138 |
* type : <array>[3800] |
| 4139 |
* /RO |
| 4140 |
* location: 1 |
| 4141 |
*/ |
| 4142 |
|
| 4143 |
#ifdef PRH_DEFAULT_MODE |
| 4144 |
PRH_VAR_TYPE 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26E9000F,0x188F00C4,0x40010015,0x26E9000F,0x188F00C2,0x400500BF,0x40000037,0x0D0000A1,0x208A000F,0x0D00004B,0x2267000F,0x0D08002A,0x70000059,0x26E9000F,0x188F00C1,0x70000009,0x2678000F,0x188F00C0,0x3BFF00E5,0x700000A9,0x40000015,0x2EEA00A1,0x188F0070,0xB000000A,0x780000A3,0x0D080020,0x0B00009F,0x38000015,0x09000011,0x09000011,0x700000A1,0x0D0400EA,0x700000A1,0x0D0400FA,0x70000031,0x70000021,0x70000001,0x70000081,0x70000091,0x700000E1,0x700000F1,0x70000061,0x70000071,0x700000C1,0x751800B1,0x700000C1,0x700000D1,0x70000041,0x70000051,0x700000A1,0x767A00A1,0x70000012,0x840400E8,0x840400F9,0x88050009,0x8805001A,0x84050020,0x84050031,0x88050042,0x84050056,0x84050067,0x88050075,0x88050086,0x880400D7,0x8C050096,0x8C0500A7,0x0A00001F,0x0D020084,0x0D0A0040,0x3BFF00B5,0x800400C1,0x40020025,0x7EE90083,0x09000011,0x0D020081,0x78000083,0x0D010084,0x78000083,0x189300D8,0x800400C1,0x0D040071,0x34000081,0x2261001F,0x900400CA,0x09000007,0x09000007,0x60000035,0x60000026,0x0D080012,0x0B00005F,0x800400C1,0x40020025,0x26E9000F,0x189200E9,0x38000012,0x09000018,0x700000AA,0x780000A3,0x1C05002F,0x0D0A0024,0x7000004B,0x0D0A0024,0x3BFF00A5,0x09000019,0x7000008B,0x0D080018,0x7000008B,0x0D040048,0x0D0A0004,0x0D080044,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000AA,0x23FA000F,0x18960020,0x0E6A000F,0x0E42000F,0x0F170002,0x0F0600F7,0x0D0000A9,0x400700F5,0x226A000F,0x400000E5,0x226A000F,0x0F0A0007,0x4FFF00FA,0x2218000B,0x0F0A000F,0x0A00000F,0x0F02007D,0x0A00000F,0x0D0A0050,0x38000042,0x09000019,0x7000005B,0x7000007B,0x700000AB,0x700000CA,0x1C9E00EF,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000C9,0x77FC00B9,0x0F140001,0x0F1600F8,0x400700F5,0x22EE000F,0x40000075,0x22EA000F,0x0D00009A,0x0F140009,0x0F1600F7,0x23AE00DF,0x0E13000F,0x0E0A000F,0x0D0000AF,0x233A000A,0x0D00001A,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000A9,0x70000059,0x0D00002A,0x0D000065,0x0D00001A,0x48000004,0x23C1000F,0x18990080,0x0D0000E5,0x23C6000F,0x18990080,0x2BC900E1,0x2BFE000A,0x0F320001,0x2A08005F,0x2BFA004E,0x0D00001A,0x1CA1009F,0x189900DF,0x2BC900E5,0x2BF9000A,0x2BFE001A,0x0D00005A,0x1CA200FF,0x2FF800A4,0x22A0000A,0x0D0000B2,0x0D0000CB,0x0D0000CD,0x2182000F,0x2A7B001B,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000A9,0x70000059,0x0D00001A,0x48000004,0x2BC100E5,0x189B0080,0x23C6000F,0x189B0080,0x2BC900E1,0x2BFE000A,0x0F320001,0x2A08005F,0x2BFA004E,0x0D00001A,0x1CA1009F,0x189B00DF,0x2BC900E5,0x2BF9000A,0x2BFE001A,0x0D00005A,0x1CA200FF,0x2FF800A4,0x22A0000A,0x0D00001A,0x0A00000F,0x40000006,0x189C004F,0x40000016,0x38000015,0x0D0A0020,0x09000019,0x70000019,0x09000019,0x72790009,0x40000005,0x26EA000F,0x189E00C4,0x40010015,0x26EA000F,0x189E00C2,0x400500BF,0x40000037,0x208A000F,0x0D00004B,0x2267000F,0x0D08002A,0x78000019,0x7000007A,0x7A790009,0x40000095,0x7EEA0069,0x189E0092,0x0D000091,0x2238000F,0x0E32000F,0x40000015,0x26E8000F,0x0D030053,0x3C000003,0x189E0060,0x23AE000F,0x189E008F,0x237E000F,0x238A000F,0x0D0C003A,0x0D0000E7,0x4000000F,0x0A00000F,0x4FFF00F1,0x0A00000F,0x40000019,0x0D00008C,0x10300087,0x40100007,0x20EE000F,0x267F000F,0x1030008A,0x0D00002B,0x2BD700BD,0x2FFA00A8,0x267C000F,0x267E0001,0x18A10070,0x296E007A,0x400700FA,0x2E7A00A7,0x2EF4007B,0x0D0000EA,0x4000009B,0x2A7300BD,0x4008000F,0x0D0000CF,0x216F000F,0x2898007C,0x2E7A00CF,0x0D00006F,0x29600065,0x28E600AC,0x0D0000BC,0x0D0000CD,0x216E000F,0x2162000F,0x0D00008B,0x0D0000BC,0x0D0000CD,0x2A1000FA,0x296F00EA,0x2E7B00AC,0x2A1000CA,0x0D0000BA,0x18A5008F,0x0F02000F,0x0A00000F,0x06090000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000A9,0x70000059,0x0D0000BA,0x0F120001,0x2A08004E,0x27FA000F,0x18A4008A,0x267F000F,0x3C000000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x2A000014,0x0A00000F,0x0D00004A,0x40000005,0x4000000C,0x1CAB007F,0x2A7E001E,0x0A00000F,0x18A5008B,0x3BFF00F5,0x2F180048,0x2200000F,0x22100000,0x0D00008A,0x237B000F,0x2B7C00BA,0x0D0000CA,0x18A500AF,0x18AA00EC,0x38000005,0x0D00004C,0x23A3000F,0x18AA0020,0x0E64000F,0x0E73000F,0x40000075,0x0D0000A9,0x2A6A007E,0x0D00009A,0x0E50000F,0x0D00000E,0x2E7A00EF,0x4000000F,0x0D020085,0x0D020045,0x2200000F,0x18AA0044,0x0E5B000F,0x0E4C000F,0x0D00002E,0x0D00006F,0x0D000059,0x0D0000A9,0x233A000F,0x0D00009A,0x0E03000F,0x0D0000B0,0x1013004E,0x23A6000F,0x0D00004A,0x48000000,0x2380000F,0x0D0000E2,0x0D0000F6,0x18A90020,0x0D000095,0x0D0000B4,0x10130012,0x0D00004E,0x2380000F,0x18AB0042,0x2261001F,0x0D0000F6,0x0D0000BE,0x0E13000F,0x227E000F,0x18A800E1,0x40000010,0x0D000046,0x2B8000E2,0x0D0000F6,0x18A90020,0x0D000012,0x2261001F,0x0D0000F6,0x0D0000EA,0x40000075,0x0D000095,0x238F00FF,0x2A1000FA,0x0D000047,0x2262000F,0x400F00F5,0x26EA000F,0x18AA00E5,0x267A000F,0x18AA0023,0x0E0A000F,0x0D0000A9,0x2218000B,0x0F0A000F,0x0A00000F,0x0F030081,0x0A00000F,0x0E5B000F,0x0E4C000F,0x2266001F,0x2A5F00EA,0x0D0000FA,0x238F00DF,0x26300000,0x2397003F,0x0D0000FA,0x18A9002F,0x40020028,0x900800E8,0x47FF00FA,0x0D0000FA,0x4FFF00FE,0x0A00000F,0x2261001F,0x0D0000F6,0x18A9001F,0x267C000F,0x23B3000F,0x18AB00C1,0x0F12009C,0x0A00000F,0x267C000F,0x18AC0045,0x0F130001,0x0F0C0001,0x0D0000BE,0x0D0000CF,0x4000001E,0x18AC009F,0x0F130001,0x0F0C0001,0x0D0000BE,0x0D0000CF,0x4000000E,0x4000000F,0x2E18001F,0x3C020005,0x4FFF0019,0x0D000005,0x14AD00FE,0x23F9000F,0x18AD004B,0x2266000F,0x2E4F008A,0x18AD006F,0x22E6000F,0x2ECF008A,0x0F130001,0x0F0C0001,0x23D0000F,0x0D00001A,0x2379000F,0x0E1A000F,0x2A1000BE,0x101400CF,0x0F180001,0x0F0A0001,0x0D0000FC,0x0D0000EB,0x0A00000F,0xC7500088,0x00008000,0x00021803,0x000FA4FD}; |
| 4145 |
#else |
| 4146 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_1_SEND_DSP_PROG2[3800]; |
| 4147 |
#endif |
| 4148 |
|
| 4149 |
|
| 4150 |
/* |
| 4151 |
* id : BUF_LEN_AC_2_SEND_DSP_PROG2 |
| 4152 |
* type : <var> |
| 4153 |
* /RO |
| 4154 |
* location: 1 |
| 4155 |
*/ |
| 4156 |
|
| 4157 |
#ifdef PRH_DEFAULT_MODE |
| 4158 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_2_SEND_DSP_PROG2=11156; |
| 4159 |
#else |
| 4160 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_2_SEND_DSP_PROG2; |
| 4161 |
#endif |
| 4162 |
|
| 4163 |
/* |
| 4164 |
* id : BUF_AC_2_SEND_DSP_PROG2 |
| 4165 |
* type : <array>[3800] |
| 4166 |
* /RO |
| 4167 |
* location: 1 |
| 4168 |
*/ |
| 4169 |
|
| 4170 |
#ifdef PRH_DEFAULT_MODE |
| 4171 |
PRH_VAR_TYPE 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26E9000F,0x188F00C4,0x40010015,0x26E9000F,0x188F00C2,0x400500BF,0x40000037,0x0D0000A1,0x208A000F,0x0D00004B,0x2267000F,0x0D08002A,0x70000059,0x26E9000F,0x188F00C1,0x70000009,0x2678000F,0x188F00C0,0x3BFF00E5,0x700000A9,0x40000015,0x2EEA00A1,0x188F0070,0xB000000A,0x780000A3,0x0D080020,0x0B00009F,0x38000015,0x09000011,0x09000011,0x700000A1,0x0D0400EA,0x700000A1,0x0D0400FA,0x70000031,0x70000021,0x70000001,0x70000081,0x70000091,0x700000E1,0x700000F1,0x70000061,0x70000071,0x700000C1,0x751800B1,0x700000C1,0x700000D1,0x70000041,0x70000051,0x700000A1,0x767A00A1,0x70000012,0x840400E8,0x840400F9,0x88050009,0x8805001A,0x84050020,0x84050031,0x88050042,0x84050056,0x84050067,0x88050075,0x88050086,0x880400D7,0x8C050096,0x8C0500A7,0x0A00001F,0x0D020084,0x0D0A0040,0x3BFF00B5,0x800400C1,0x40020025,0x7EE90083,0x09000011,0x0D020081,0x78000083,0x0D010084,0x78000083,0x189300D8,0x800400C1,0x0D040071,0x34000081,0x2261001F,0x900400CA,0x09000007,0x09000007,0x60000035,0x60000026,0x0D080012,0x0B00005F,0x800400C1,0x40020025,0x26E9000F,0x189200E9,0x38000012,0x09000018,0x700000AA,0x780000A3,0x1C05002F,0x0D0A0024,0x7000004B,0x0D0A0024,0x3BFF00A5,0x09000019,0x7000008B,0x0D080018,0x7000008B,0x0D040048,0x0D0A0004,0x0D080044,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000AA,0x23FA000F,0x18960020,0x0E6A000F,0x0E42000F,0x0F170002,0x0F0600F7,0x0D0000A9,0x400700F5,0x226A000F,0x400000E5,0x226A000F,0x0F0A0007,0x4FFF00FA,0x2218000B,0x0F0A000F,0x0A00000F,0x0F02007D,0x0A00000F,0x0D0A0050,0x38000042,0x09000019,0x7000005B,0x7000007B,0x700000AB,0x700000CA,0x1C9E00EF,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000C9,0x77FC00B9,0x0F140001,0x0F1600F8,0x400700F5,0x22EE000F,0x40000075,0x22EA000F,0x0D00009A,0x0F140009,0x0F1600F7,0x23AE00DF,0x0E13000F,0x0E0A000F,0x0D0000AF,0x233A000A,0x0D00001A,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000A9,0x70000059,0x0D00002A,0x0D000065,0x0D00001A,0x48000004,0x23C1000F,0x18990080,0x0D0000E5,0x23C6000F,0x18990080,0x2BC900E1,0x2BFE000A,0x0F320001,0x2A08005F,0x2BFA004E,0x0D00001A,0x1CA1009F,0x189900DF,0x2BC900E5,0x2BF9000A,0x2BFE001A,0x0D00005A,0x1CA200FF,0x2FF800A4,0x22A0000A,0x0D0000B2,0x0D0000CB,0x0D0000CD,0x2182000F,0x2A7B001B,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000A9,0x70000059,0x0D00001A,0x48000004,0x2BC100E5,0x189B0080,0x23C6000F,0x189B0080,0x2BC900E1,0x2BFE000A,0x0F320001,0x2A08005F,0x2BFA004E,0x0D00001A,0x1CA1009F,0x189B00DF,0x2BC900E5,0x2BF9000A,0x2BFE001A,0x0D00005A,0x1CA200FF,0x2FF800A4,0x22A0000A,0x0D00001A,0x0A00000F,0x40000006,0x189C004F,0x40000016,0x38000015,0x0D0A0020,0x09000019,0x70000019,0x09000019,0x72790009,0x40000005,0x26EA000F,0x189E00C4,0x40010015,0x26EA000F,0x189E00C2,0x400500BF,0x40000037,0x208A000F,0x0D00004B,0x2267000F,0x0D08002A,0x78000019,0x7000007A,0x7A790009,0x40000095,0x7EEA0069,0x189E0092,0x0D000091,0x2238000F,0x0E32000F,0x40000015,0x26E8000F,0x0D030053,0x3C000003,0x189E0060,0x23AE000F,0x189E008F,0x237E000F,0x238A000F,0x0D0C003A,0x0D0000E7,0x4000000F,0x0A00000F,0x4FFF00F1,0x0A00000F,0x40000019,0x0D00008C,0x10300087,0x40100007,0x20EE000F,0x267F000F,0x1030008A,0x0D00002B,0x2BD700BD,0x2FFA00A8,0x267C000F,0x267E0001,0x18A10070,0x296E007A,0x400700FA,0x2E7A00A7,0x2EF4007B,0x0D0000EA,0x4000009B,0x2A7300BD,0x4008000F,0x0D0000CF,0x216F000F,0x2898007C,0x2E7A00CF,0x0D00006F,0x29600065,0x28E600AC,0x0D0000BC,0x0D0000CD,0x216E000F,0x2162000F,0x0D00008B,0x0D0000BC,0x0D0000CD,0x2A1000FA,0x296F00EA,0x2E7B00AC,0x2A1000CA,0x0D0000BA,0x18A5008F,0x0F02000F,0x0A00000F,0x06090000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x07110000,0x0A00000F,0x38000015,0x0D0A0020,0x09000019,0x700000A9,0x70000059,0x0D0000BA,0x0F120001,0x2A08004E,0x27FA000F,0x18A4008A,0x267F000F,0x3C000000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x07120000,0x2A000014,0x0A00000F,0x0D00004A,0x40000005,0x4000000C,0x1CAB007F,0x2A7E001E,0x0A00000F,0x18A5008B,0x3BFF00F5,0x2F180048,0x2200000F,0x22100000,0x0D00008A,0x237B000F,0x2B7C00BA,0x0D0000CA,0x18A500AF,0x18AA00EC,0x38000005,0x0D00004C,0x23A3000F,0x18AA0020,0x0E64000F,0x0E73000F,0x40000075,0x0D0000A9,0x2A6A007E,0x0D00009A,0x0E50000F,0x0D00000E,0x2E7A00EF,0x4000000F,0x0D020085,0x0D020045,0x2200000F,0x18AA0044,0x0E5B000F,0x0E4C000F,0x0D00002E,0x0D00006F,0x0D000059,0x0D0000A9,0x233A000F,0x0D00009A,0x0E03000F,0x0D0000B0,0x1013004E,0x23A6000F,0x0D00004A,0x48000000,0x2380000F,0x0D0000E2,0x0D0000F6,0x18A90020,0x0D000095,0x0D0000B4,0x10130012,0x0D00004E,0x2380000F,0x18AB0042,0x2261001F,0x0D0000F6,0x0D0000BE,0x0E13000F,0x227E000F,0x18A800E1,0x40000010,0x0D000046,0x2B8000E2,0x0D0000F6,0x18A90020,0x0D000012,0x2261001F,0x0D0000F6,0x0D0000EA,0x40000075,0x0D000095,0x238F00FF,0x2A1000FA,0x0D000047,0x2262000F,0x400F00F5,0x26EA000F,0x18AA00E5,0x267A000F,0x18AA0023,0x0E0A000F,0x0D0000A9,0x2218000B,0x0F0A000F,0x0A00000F,0x0F030081,0x0A00000F,0x0E5B000F,0x0E4C000F,0x2266001F,0x2A5F00EA,0x0D0000FA,0x238F00DF,0x26300000,0x2397003F,0x0D0000FA,0x18A9002F,0x40020028,0x900800E8,0x47FF00FA,0x0D0000FA,0x4FFF00FE,0x0A00000F,0x2261001F,0x0D0000F6,0x18A9001F,0x267C000F,0x23B3000F,0x18AB00C1,0x0F12009C,0x0A00000F,0x267C000F,0x18AC0045,0x0F130001,0x0F0C0001,0x0D0000BE,0x0D0000CF,0x4000001E,0x18AC009F,0x0F130001,0x0F0C0001,0x0D0000BE,0x0D0000CF,0x4000000E,0x4000000F,0x2E18001F,0x3C020005,0x4FFF0019,0x0D000005,0x14AD00FE,0x23F9000F,0x18AD004B,0x2266000F,0x2E4F008A,0x18AD006F,0x22E6000F,0x2ECF008A,0x0F130001,0x0F0C0001,0x23D0000F,0x0D00001A,0x2379000F,0x0E1A000F,0x2A1000BE,0x101400CF,0x0F180001,0x0F0A0001,0x0D0000FC,0x0D0000EB,0x0A00000F,0xF2780088,0x00008000,0x00021803,0x000FA4FD}; |
| 4172 |
#else |
| 4173 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_2_SEND_DSP_PROG2[3800]; |
| 4174 |
#endif |
| 4175 |
|
| 4176 |
|
| 4177 |
/* |
| 4178 |
* id : BUF_LEN_AC_2_WRITE_REG |
| 4179 |
* type : <var> |
| 4180 |
* /RO |
| 4181 |
* location: 3 |
| 4182 |
*/ |
| 4183 |
|
| 4184 |
#ifdef PRH_DEFAULT_MODE |
| 4185 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_2_WRITE_REG=54; |
| 4186 |
#else |
| 4187 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_2_WRITE_REG; |
| 4188 |
#endif |
| 4189 |
|
| 4190 |
/* |
| 4191 |
* id : BUF_AC_2_WRITE_REG |
| 4192 |
* type : <array>[15] |
| 4193 |
* /RO |
| 4194 |
* location: 3 |
| 4195 |
*/ |
| 4196 |
|
| 4197 |
#ifdef PRH_DEFAULT_MODE |
| 4198 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_2_WRITE_REG[15]={0x00890008,0xFFFF0040,0xACACFFFF,0x0041AC22,0xFFFF0044,0xFE00FFFF,0x00450000,0xFFFF0046,0xFFFFFFFF,0x00470040,0xFFFF0048,0xFFFFFFFF,0x0049FFFF,0x442B0000}; |
| 4199 |
#else |
| 4200 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_2_WRITE_REG[15]; |
| 4201 |
#endif |
| 4202 |
|
| 4203 |
|
| 4204 |
/* |
| 4205 |
* id : BUF_LEN_AC_1_WRITE_REG |
| 4206 |
* type : <var> |
| 4207 |
* /RO |
| 4208 |
* location: 3 |
| 4209 |
*/ |
| 4210 |
|
| 4211 |
#ifdef PRH_DEFAULT_MODE |
| 4212 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_1_WRITE_REG=54; |
| 4213 |
#else |
| 4214 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_1_WRITE_REG; |
| 4215 |
#endif |
| 4216 |
|
| 4217 |
/* |
| 4218 |
* id : BUF_AC_1_WRITE_REG |
| 4219 |
* type : <array>[15] |
| 4220 |
* /RO |
| 4221 |
* location: 3 |
| 4222 |
*/ |
| 4223 |
|
| 4224 |
#ifdef PRH_DEFAULT_MODE |
| 4225 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_1_WRITE_REG[15]={0x00890008,0xFFFF0040,0xACACFFFF,0x0041AC11,0xFFFF0044,0xFE00FFFF,0x0045000F,0xFFFF0046,0xFFFFFFFF,0x00470040,0xFFFF0048,0xFFFFFFFF,0x0049FFFF,0x42D80000}; |
| 4226 |
#else |
| 4227 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_1_WRITE_REG[15]; |
| 4228 |
#endif |
| 4229 |
|
| 4230 |
|
| 4231 |
/* |
| 4232 |
* id : BUF_LEN_AC_READ_DSP_MEM |
| 4233 |
* type : <var> |
| 4234 |
* /RO |
| 4235 |
* location: 3 |
| 4236 |
*/ |
| 4237 |
|
| 4238 |
#ifdef PRH_DEFAULT_MODE |
| 4239 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_READ_DSP_MEM=10; |
| 4240 |
#else |
| 4241 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_AC_READ_DSP_MEM; |
| 4242 |
#endif |
| 4243 |
|
| 4244 |
/* |
| 4245 |
* id : BUF_AC_READ_DSP_MEM |
| 4246 |
* type : <array>[3] |
| 4247 |
* /RO |
| 4248 |
* location: 3 |
| 4249 |
*/ |
| 4250 |
|
| 4251 |
#ifdef PRH_DEFAULT_MODE |
| 4252 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_READ_DSP_MEM[3]={0x00804100,0x80002040,0x17530000}; |
| 4253 |
#else |
| 4254 |
PRH_VAR_TYPE PRH_ARR_BUF_AC_READ_DSP_MEM[3]; |
| 4255 |
#endif |
| 4256 |
|
| 4257 |
|
| 4258 |
/* |
| 4259 |
* --------- TOF Time of Fligth : ------------- |
| 4260 |
*/ |
| 4261 |
|
| 4262 |
|
| 4263 |
/* |
| 4264 |
* id : BUF_LEN_TOF_WRITE_PMT_THR_1 |
| 4265 |
* type : <var> |
| 4266 |
* TOF set THR front end 1 /RO |
| 4267 |
* location: 3 |
| 4268 |
*/ |
| 4269 |
|
| 4270 |
#ifdef PRH_DEFAULT_MODE |
| 4271 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_1=7; |
| 4272 |
#else |
| 4273 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_1; |
| 4274 |
#endif |
| 4275 |
|
| 4276 |
/* |
| 4277 |
* id : BUF_TOF_WRITE_PMT_THR_1 |
| 4278 |
* type : <array>[2] |
| 4279 |
* TOF set THR front end 1 /RO |
| 4280 |
* location: 3 |
| 4281 |
*/ |
| 4282 |
|
| 4283 |
#ifdef PRH_DEFAULT_MODE |
| 4284 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_1[2]={0xB0C40A0A,0x0707FC00}; |
| 4285 |
#else |
| 4286 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_1[2]; |
| 4287 |
#endif |
| 4288 |
|
| 4289 |
|
| 4290 |
/* |
| 4291 |
* id : BUF_LEN_TOF_WRITE_PMT_THR_2 |
| 4292 |
* type : <var> |
| 4293 |
* TOF set THR front end 2 /RO |
| 4294 |
* location: 3 |
| 4295 |
*/ |
| 4296 |
|
| 4297 |
#ifdef PRH_DEFAULT_MODE |
| 4298 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_2=7; |
| 4299 |
#else |
| 4300 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_2; |
| 4301 |
#endif |
| 4302 |
|
| 4303 |
/* |
| 4304 |
* id : BUF_TOF_WRITE_PMT_THR_2 |
| 4305 |
* type : <array>[2] |
| 4306 |
* TOF set THR front end 2 /RO |
| 4307 |
* location: 3 |
| 4308 |
*/ |
| 4309 |
|
| 4310 |
#ifdef PRH_DEFAULT_MODE |
| 4311 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_2[2]={0xB1C40707,0x0707BA00}; |
| 4312 |
#else |
| 4313 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_2[2]; |
| 4314 |
#endif |
| 4315 |
|
| 4316 |
|
| 4317 |
/* |
| 4318 |
* id : BUF_LEN_TOF_WRITE_PMT_THR_3 |
| 4319 |
* type : <var> |
| 4320 |
* TOF set THR front end 3 /RO |
| 4321 |
* location: 3 |
| 4322 |
*/ |
| 4323 |
|
| 4324 |
#ifdef PRH_DEFAULT_MODE |
| 4325 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_3=7; |
| 4326 |
#else |
| 4327 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_3; |
| 4328 |
#endif |
| 4329 |
|
| 4330 |
/* |
| 4331 |
* id : BUF_TOF_WRITE_PMT_THR_3 |
| 4332 |
* type : <array>[2] |
| 4333 |
* TOF set THR front end 3 /RO |
| 4334 |
* location: 3 |
| 4335 |
*/ |
| 4336 |
|
| 4337 |
#ifdef PRH_DEFAULT_MODE |
| 4338 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_3[2]={0xB2C40707,0x0707C100}; |
| 4339 |
#else |
| 4340 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_3[2]; |
| 4341 |
#endif |
| 4342 |
|
| 4343 |
|
| 4344 |
/* |
| 4345 |
* id : BUF_LEN_TOF_WRITE_PMT_THR_4 |
| 4346 |
* type : <var> |
| 4347 |
* TOF set THR front end 4 /RO |
| 4348 |
* location: 3 |
| 4349 |
*/ |
| 4350 |
|
| 4351 |
#ifdef PRH_DEFAULT_MODE |
| 4352 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_4=7; |
| 4353 |
#else |
| 4354 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_4; |
| 4355 |
#endif |
| 4356 |
|
| 4357 |
/* |
| 4358 |
* id : BUF_TOF_WRITE_PMT_THR_4 |
| 4359 |
* type : <array>[2] |
| 4360 |
* TOF set THR front end 4 /RO |
| 4361 |
* location: 3 |
| 4362 |
*/ |
| 4363 |
|
| 4364 |
#ifdef PRH_DEFAULT_MODE |
| 4365 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_4[2]={0xB3C40707,0x0707E800}; |
| 4366 |
#else |
| 4367 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_4[2]; |
| 4368 |
#endif |
| 4369 |
|
| 4370 |
|
| 4371 |
/* |
| 4372 |
* id : BUF_LEN_TOF_WRITE_PMT_THR_5 |
| 4373 |
* type : <var> |
| 4374 |
* TOF set THR front end 5 /RO |
| 4375 |
* location: 3 |
| 4376 |
*/ |
| 4377 |
|
| 4378 |
#ifdef PRH_DEFAULT_MODE |
| 4379 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_5=7; |
| 4380 |
#else |
| 4381 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_5; |
| 4382 |
#endif |
| 4383 |
|
| 4384 |
/* |
| 4385 |
* id : BUF_TOF_WRITE_PMT_THR_5 |
| 4386 |
* type : <array>[2] |
| 4387 |
* TOF set THR front end 5 /RO |
| 4388 |
* location: 3 |
| 4389 |
*/ |
| 4390 |
|
| 4391 |
#ifdef PRH_DEFAULT_MODE |
| 4392 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_5[2]={0xB4C40707,0x07073700}; |
| 4393 |
#else |
| 4394 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_5[2]; |
| 4395 |
#endif |
| 4396 |
|
| 4397 |
|
| 4398 |
/* |
| 4399 |
* id : BUF_LEN_TOF_WRITE_PMT_THR_6 |
| 4400 |
* type : <var> |
| 4401 |
* TOF set THR front end 5 /RO |
| 4402 |
* location: 3 |
| 4403 |
*/ |
| 4404 |
|
| 4405 |
#ifdef PRH_DEFAULT_MODE |
| 4406 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_6=7; |
| 4407 |
#else |
| 4408 |
PRH_VAR_TYPE PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_6; |
| 4409 |
#endif |
| 4410 |
|
| 4411 |
/* |
| 4412 |
* id : BUF_TOF_WRITE_PMT_THR_6 |
| 4413 |
* type : <array>[2] |
| 4414 |
* TOF set THR front end 5 /RO |
| 4415 |
* location: 3 |
| 4416 |
*/ |
| 4417 |
|
| 4418 |
#ifdef PRH_DEFAULT_MODE |
| 4419 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_6[2]={0xB5C40707,0x07071E00}; |
| 4420 |
#else |
| 4421 |
PRH_VAR_TYPE PRH_ARR_BUF_TOF_WRITE_PMT_THR_6[2]; |
| 4422 |
#endif |
| 4423 |
|
| 4424 |
|
| 4425 |
/* |
| 4426 |
* id : TOF_OK |
| 4427 |
* type : <var> |
| 4428 |
* TOF ON_OFF in ACQ /RW |
| 4429 |
* location: 3 |
| 4430 |
*/ |
| 4431 |
|
| 4432 |
#ifdef PRH_DEFAULT_MODE |
| 4433 |
PRH_VAR_TYPE PRH_VAR_TOF_OK=1; |
| 4434 |
#else |
| 4435 |
PRH_VAR_TYPE PRH_VAR_TOF_OK; |
| 4436 |
#endif |
| 4437 |
|
| 4438 |
/* |
| 4439 |
* id : TOF_PLAN |
| 4440 |
* type : <array>[6] |
| 4441 |
* TOF Plans selectors /RO |
| 4442 |
* location: 3 |
| 4443 |
*/ |
| 4444 |
|
| 4445 |
#ifdef PRH_DEFAULT_MODE |
| 4446 |
PRH_VAR_TYPE PRH_ARR_TOF_PLAN[6]={1,1,1,1,1,1}; |
| 4447 |
#else |
| 4448 |
PRH_VAR_TYPE PRH_ARR_TOF_PLAN[6]; |
| 4449 |
#endif |
| 4450 |
|
| 4451 |
|
| 4452 |
/* |
| 4453 |
* --------- ND Neutron Detector : ------------- |
| 4454 |
*/ |
| 4455 |
|
| 4456 |
|
| 4457 |
/* |
| 4458 |
* id : ND_OK |
| 4459 |
* type : <var> |
| 4460 |
* ND ON_OFF in ACQ /RW |
| 4461 |
* location: 3 |
| 4462 |
*/ |
| 4463 |
|
| 4464 |
#ifdef PRH_DEFAULT_MODE |
| 4465 |
PRH_VAR_TYPE PRH_VAR_ND_OK=1; |
| 4466 |
#else |
| 4467 |
PRH_VAR_TYPE PRH_VAR_ND_OK; |
| 4468 |
#endif |
| 4469 |
|
| 4470 |
/* |
| 4471 |
* id : ND_ATTEMPT |
| 4472 |
* type : <var> |
| 4473 |
* Force ND in ACQ (1), unless ND_OK is FALSE /RO |
| 4474 |
* location: 3 |
| 4475 |
*/ |
| 4476 |
|
| 4477 |
#ifdef PRH_DEFAULT_MODE |
| 4478 |
PRH_VAR_TYPE PRH_VAR_ND_ATTEMPT=0; |
| 4479 |
#else |
| 4480 |
PRH_VAR_TYPE PRH_VAR_ND_ATTEMPT; |
| 4481 |
#endif |
| 4482 |
|
| 4483 |
/* |
| 4484 |
* id : ND_CMDS |
| 4485 |
* type : <var> |
| 4486 |
* Force ND in ACQ, unless ND_OK is FALSE /RO |
| 4487 |
* location: 3 |
| 4488 |
*/ |
| 4489 |
|
| 4490 |
#ifdef PRH_DEFAULT_MODE |
| 4491 |
PRH_VAR_TYPE PRH_VAR_ND_CMDS=3; |
| 4492 |
#else |
| 4493 |
PRH_VAR_TYPE PRH_VAR_ND_CMDS; |
| 4494 |
#endif |
| 4495 |
|
| 4496 |
/* |
| 4497 |
* --------- SM SRAM Page Manager Test : ------------- |
| 4498 |
*/ |
| 4499 |
|
| 4500 |
|
| 4501 |
/* |
| 4502 |
* --------- SCM Task : ------------- |
| 4503 |
*/ |
| 4504 |
|
| 4505 |
|
| 4506 |
/* |
| 4507 |
* id : PM_PERIODIC_DELAY |
| 4508 |
* type : <array>[4] |
| 4509 |
* Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations, /RO |
| 4510 |
* location: 3 |
| 4511 |
*/ |
| 4512 |
|
| 4513 |
#ifdef PRH_DEFAULT_MODE |
| 4514 |
PRH_VAR_TYPE PRH_ARR_PM_PERIODIC_DELAY[4]= |
| 4515 |
{ |
| 4516 |
1000, |
| 4517 |
10000, |
| 4518 |
10000, |
| 4519 |
1000*24*60*60 |
| 4520 |
}; |
| 4521 |
#else |
| 4522 |
PRH_VAR_TYPE PRH_ARR_PM_PERIODIC_DELAY[4]; |
| 4523 |
#endif |
| 4524 |
|
| 4525 |
|
| 4526 |
/* |
| 4527 |
* id : SCM_TM_DO_CHECK_VALUES_FREQ |
| 4528 |
* type : <var> |
| 4529 |
* Do a Check on TM values every XXX Number of cyc acq done /RO |
| 4530 |
* location: 3 |
| 4531 |
*/ |
| 4532 |
|
| 4533 |
#ifdef PRH_DEFAULT_MODE |
| 4534 |
PRH_VAR_TYPE PRH_VAR_SCM_TM_DO_CHECK_VALUES_FREQ=1; |
| 4535 |
#else |
| 4536 |
PRH_VAR_TYPE PRH_VAR_SCM_TM_DO_CHECK_VALUES_FREQ; |
| 4537 |
#endif |
| 4538 |
|
| 4539 |
/* |
| 4540 |
* --------- PWR :------------- |
| 4541 |
*/ |
| 4542 |
|
| 4543 |
|
| 4544 |
/* |
| 4545 |
* HL Setting ------------- |
| 4546 |
*/ |
| 4547 |
|
| 4548 |
|
| 4549 |
/* |
| 4550 |
* id : POWER_KHB |
| 4551 |
* type : <var> |
| 4552 |
* Select KHB board 0==>HOT else COLD |
| 4553 |
* location: 3 |
| 4554 |
*/ |
| 4555 |
|
| 4556 |
#ifdef PRH_DEFAULT_MODE |
| 4557 |
PRH_VAR_TYPE PRH_VAR_POWER_KHB=0; |
| 4558 |
#else |
| 4559 |
PRH_VAR_TYPE PRH_VAR_POWER_KHB; |
| 4560 |
#endif |
| 4561 |
|
| 4562 |
/* |
| 4563 |
* PSB Setting ------------- |
| 4564 |
*/ |
| 4565 |
|
| 4566 |
|
| 4567 |
/* |
| 4568 |
* id : PSB_TRB_S9004_ALL_ON_DELAY |
| 4569 |
* type : <var> |
| 4570 |
* milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on) /RO |
| 4571 |
* location: 3 |
| 4572 |
*/ |
| 4573 |
|
| 4574 |
#ifdef PRH_DEFAULT_MODE |
| 4575 |
PRH_VAR_TYPE PRH_VAR_PSB_TRB_S9004_ALL_ON_DELAY=1000; |
| 4576 |
#else |
| 4577 |
PRH_VAR_TYPE PRH_VAR_PSB_TRB_S9004_ALL_ON_DELAY; |
| 4578 |
#endif |
| 4579 |
|
| 4580 |
/* |
| 4581 |
* id : PSB_TRB_BIAS_WAIT |
| 4582 |
* type : <var> |
| 4583 |
* wait between bias TRB switch on/off /RO |
| 4584 |
* location: 3 |
| 4585 |
*/ |
| 4586 |
|
| 4587 |
#ifdef PRH_DEFAULT_MODE |
| 4588 |
PRH_VAR_TYPE PRH_VAR_PSB_TRB_BIAS_WAIT=3000; |
| 4589 |
#else |
| 4590 |
PRH_VAR_TYPE PRH_VAR_PSB_TRB_BIAS_WAIT; |
| 4591 |
#endif |
| 4592 |
|
| 4593 |
/* |
| 4594 |
* id : PSB_COMMANDS |
| 4595 |
* type : <array>[29] |
| 4596 |
* Command for PSB /RO |
| 4597 |
* location: 3 |
| 4598 |
*/ |
| 4599 |
|
| 4600 |
#ifdef PRH_DEFAULT_MODE |
| 4601 |
PRH_VAR_TYPE PRH_ARR_PSB_COMMANDS[29]={ |
| 4602 |
0x00C5, |
| 4603 |
0x01B6, |
| 4604 |
0x02D0, |
| 4605 |
0x05C5, |
| 4606 |
0x05A5, |
| 4607 |
0x0500, |
| 4608 |
0x0500, |
| 4609 |
0x06C3, |
| 4610 |
0x07D0, |
| 4611 |
0x08EC, |
| 4612 |
0x09FF, |
| 4613 |
0x0AF9, |
| 4614 |
0x0B8A, |
| 4615 |
0x0C9F, |
| 4616 |
0x0E8A, |
| 4617 |
0x0F99, |
| 4618 |
0x10AE, |
| 4619 |
0x121E, |
| 4620 |
0x12DB, |
| 4621 |
0x121E, |
| 4622 |
0x14DD, |
| 4623 |
0x15CE, |
| 4624 |
0x17DB, |
| 4625 |
0x18E7, |
| 4626 |
0x19F4, |
| 4627 |
0x03c3, |
| 4628 |
0x04d6, |
| 4629 |
0x0dec, |
| 4630 |
0x0F3C |
| 4631 |
}; |
| 4632 |
#else |
| 4633 |
PRH_VAR_TYPE PRH_ARR_PSB_COMMANDS[29]; |
| 4634 |
#endif |
| 4635 |
|
| 4636 |
|
| 4637 |
/* |
| 4638 |
* id : PSB_CALO_FE_ON |
| 4639 |
* type : <array>[4] |
| 4640 |
* Command for PSB /RO |
| 4641 |
* location: 3 |
| 4642 |
*/ |
| 4643 |
|
| 4644 |
#ifdef PRH_DEFAULT_MODE |
| 4645 |
PRH_VAR_TYPE PRH_ARR_PSB_CALO_FE_ON[4]={ |
| 4646 |
0x1AF2, |
| 4647 |
0x1BE1, |
| 4648 |
0x1CF4, |
| 4649 |
0x1DE7 |
| 4650 |
}; |
| 4651 |
#else |
| 4652 |
PRH_VAR_TYPE PRH_ARR_PSB_CALO_FE_ON[4]; |
| 4653 |
#endif |
| 4654 |
|
| 4655 |
|
| 4656 |
/* |
| 4657 |
* id : PSB_CALO_FE_OFF |
| 4658 |
* type : <array>[4] |
| 4659 |
* Command for PSB /RO |
| 4660 |
* location: 3 |
| 4661 |
*/ |
| 4662 |
|
| 4663 |
#ifdef PRH_DEFAULT_MODE |
| 4664 |
PRH_VAR_TYPE PRH_ARR_PSB_CALO_FE_OFF[4]={ |
| 4665 |
0x1A37, |
| 4666 |
0x1B24, |
| 4667 |
0x1C31, |
| 4668 |
0x1D22 |
| 4669 |
}; |
| 4670 |
#else |
| 4671 |
PRH_VAR_TYPE PRH_ARR_PSB_CALO_FE_OFF[4]; |
| 4672 |
#endif |
| 4673 |
|
| 4674 |
|
| 4675 |
/* |
| 4676 |
* id : PSB_CALO_FE |
| 4677 |
* type : <array>[4] |
| 4678 |
* Command for PSB /RO |
| 4679 |
* location: 3 |
| 4680 |
*/ |
| 4681 |
|
| 4682 |
#ifdef PRH_DEFAULT_MODE |
| 4683 |
PRH_VAR_TYPE PRH_ARR_PSB_CALO_FE[4]={ |
| 4684 |
0x1AF2, |
| 4685 |
0x1BE1, |
| 4686 |
0x1CF4, |
| 4687 |
0x1DE7 |
| 4688 |
}; |
| 4689 |
#else |
| 4690 |
PRH_VAR_TYPE PRH_ARR_PSB_CALO_FE[4]; |
| 4691 |
#endif |
| 4692 |
|
| 4693 |
|
| 4694 |
/* |
| 4695 |
* id : PSB_CALOFE_DELAY |
| 4696 |
* type : <var> |
| 4697 |
* Delay before power on CALO 5.7 /RO |
| 4698 |
* location: 3 |
| 4699 |
*/ |
| 4700 |
|
| 4701 |
#ifdef PRH_DEFAULT_MODE |
| 4702 |
PRH_VAR_TYPE PRH_VAR_PSB_CALOFE_DELAY=1000; |
| 4703 |
#else |
| 4704 |
PRH_VAR_TYPE PRH_VAR_PSB_CALOFE_DELAY; |
| 4705 |
#endif |
| 4706 |
|
| 4707 |
/* |
| 4708 |
* id : HV_OK |
| 4709 |
* type : <var> |
| 4710 |
* call HV settings after TRB setting at start-up /RO |
| 4711 |
* location: 3 |
| 4712 |
*/ |
| 4713 |
|
| 4714 |
#ifdef PRH_DEFAULT_MODE |
| 4715 |
PRH_VAR_TYPE PRH_VAR_HV_OK=1; |
| 4716 |
#else |
| 4717 |
PRH_VAR_TYPE PRH_VAR_HV_OK; |
| 4718 |
#endif |
| 4719 |
|
| 4720 |
/* |
| 4721 |
* id : HVB_COMMANDS |
| 4722 |
* type : <array>[12] |
| 4723 |
* Command for HVB /RO |
| 4724 |
* location: 3 |
| 4725 |
*/ |
| 4726 |
|
| 4727 |
#ifdef PRH_DEFAULT_MODE |
| 4728 |
PRH_VAR_TYPE PRH_ARR_HVB_COMMANDS[12]={ |
| 4729 |
0xC387, |
| 4730 |
0xC78F, |
| 4731 |
0xCB16, |
| 4732 |
0xCF9F, |
| 4733 |
0xD2A5, |
| 4734 |
0xD7AF, |
| 4735 |
0xDBB7, |
| 4736 |
0xDFBF, |
| 4737 |
0xE3C7, |
| 4738 |
0xE6CD, |
| 4739 |
0xEBD7, |
| 4740 |
0xEEDD |
| 4741 |
}; |
| 4742 |
#else |
| 4743 |
PRH_VAR_TYPE PRH_ARR_HVB_COMMANDS[12]; |
| 4744 |
#endif |
| 4745 |
|
| 4746 |
|
| 4747 |
/* |
| 4748 |
* TRB Setting ------------- |
| 4749 |
*/ |
| 4750 |
|
| 4751 |
|
| 4752 |
/* |
| 4753 |
* TRB Setting:expected value ------------- |
| 4754 |
*/ |
| 4755 |
|
| 4756 |
|
| 4757 |
/* |
| 4758 |
* TSB Setting:expected value ------------- |
| 4759 |
*/ |
| 4760 |
|
| 4761 |
|
| 4762 |
/* |
| 4763 |
* id : TSB_BOARD_OK |
| 4764 |
* type : <array>[2] |
| 4765 |
* User TSB Board no 0/1 flags /RO |
| 4766 |
* location: 3 |
| 4767 |
*/ |
| 4768 |
|
| 4769 |
#ifdef PRH_DEFAULT_MODE |
| 4770 |
PRH_VAR_TYPE PRH_ARR_TSB_BOARD_OK[2]={1,0}; |
| 4771 |
#else |
| 4772 |
PRH_VAR_TYPE PRH_ARR_TSB_BOARD_OK[2]; |
| 4773 |
#endif |
| 4774 |
|
| 4775 |
|
| 4776 |
/* |
| 4777 |
* id : TSB_T_OK |
| 4778 |
* type : <var> |
| 4779 |
* Do TSB Temperature check /RO |
| 4780 |
* location: 3 |
| 4781 |
*/ |
| 4782 |
|
| 4783 |
#ifdef PRH_DEFAULT_MODE |
| 4784 |
PRH_VAR_TYPE PRH_VAR_TSB_T_OK=1; |
| 4785 |
#else |
| 4786 |
PRH_VAR_TYPE PRH_VAR_TSB_T_OK; |
| 4787 |
#endif |
| 4788 |
|
| 4789 |
/* |
| 4790 |
* id : TSB_B_OK |
| 4791 |
* type : <var> |
| 4792 |
* Do B-field TSB check /RO |
| 4793 |
* location: 3 |
| 4794 |
*/ |
| 4795 |
|
| 4796 |
#ifdef PRH_DEFAULT_MODE |
| 4797 |
PRH_VAR_TYPE PRH_VAR_TSB_B_OK=1; |
| 4798 |
#else |
| 4799 |
PRH_VAR_TYPE PRH_VAR_TSB_B_OK; |
| 4800 |
#endif |
| 4801 |
|
| 4802 |
/* |
| 4803 |
* id : ALLPAGEAVAIL_ATTEMPT |
| 4804 |
* type : <var> |
| 4805 |
* ATTEMP TO ALLPAGE AVAILABLE |
| 4806 |
* location: 3 |
| 4807 |
*/ |
| 4808 |
|
| 4809 |
#ifdef PRH_DEFAULT_MODE |
| 4810 |
PRH_VAR_TYPE PRH_VAR_ALLPAGEAVAIL_ATTEMPT=50; |
| 4811 |
#else |
| 4812 |
PRH_VAR_TYPE PRH_VAR_ALLPAGEAVAIL_ATTEMPT; |
| 4813 |
#endif |
| 4814 |
|
| 4815 |
/* |
| 4816 |
* ********************************** end of declarations ************************************ |
| 4817 |
*/ |
| 4818 |
|
| 4819 |
|
| 4820 |
|
| 4821 |
|
| 4822 |
|
| 4823 |
static UINT32 PRH_VAR_EEPROM_ADDR[206]; |
| 4824 |
|
| 4825 |
#ifdef I386 |
| 4826 |
static char *PRH_VAR_NAME[206] |
| 4827 |
#endif // ifdef I386 |
| 4828 |
|
| 4829 |
|
| 4830 |
|
| 4831 |
static UINT32 PRH_ARR_EEPROM_ADDR[116]; |
| 4832 |
|
| 4833 |
#ifdef I386 |
| 4834 |
static char *PRH_ARR_NAME[116] |
| 4835 |
#endif // ifdef I386 |
| 4836 |
|
| 4837 |
|
| 4838 |
|
| 4839 |
|
| 4840 |
|
| 4841 |
static UINT32 PRH_TAB_EEPROM_ADDR[14]; |
| 4842 |
|
| 4843 |
#ifdef I386 |
| 4844 |
static char *PRH_TAB_NAME[116] |
| 4845 |
#endif // ifdef I386 |
| 4846 |
|
| 4847 |
static BYTE PRH_VAR_MM_FLAG[206] = {1 /* LU_WRITE_ON_UART */ |
| 4848 |
,1 /* VERBOSE_DEBUG */ |
| 4849 |
,1 /* DOWNLOAD_HEADER */ |
| 4850 |
,1 /* KHB_ALARM_REG_LOW_LEVEL_MASK */ |
| 4851 |
,1 /* KHB_STATUS_REG_LOW_LEVEL_MASK */ |
| 4852 |
,1 /* PULSER_ACTION */ |
| 4853 |
,1 /* N_BOOT */ |
| 4854 |
,1 /* THERMISTORS_CHECK */ |
| 4855 |
,1 /* THERM_MASK */ |
| 4856 |
,1 /* IPM_VOLTAGES_CHECK */ |
| 4857 |
,1 /* KHB_IDAQ_CHECK */ |
| 4858 |
,1 /* NTRIG */ |
| 4859 |
,1 /* TRIG */ |
| 4860 |
,1 /* CONF_SEL */ |
| 4861 |
,1 /* CONFOK */ |
| 4862 |
,1 /* OFF */ |
| 4863 |
,1 /* NOFF */ |
| 4864 |
,1 /* NRES */ |
| 4865 |
,1 /* RES */ |
| 4866 |
,1 /* WATCHDOG_RESET_DISABLE */ |
| 4867 |
,1 /* NFAILED_POWER_ON */ |
| 4868 |
,1 /* AUTO_RM_MODE */ |
| 4869 |
,1 /* AUTO_SCM_MODE */ |
| 4870 |
,1 /* MASK_ACQ_ALARM */ |
| 4871 |
,1 /* GOM_DURING_ALARM */ |
| 4872 |
,1 /* PM_FORCE_RUNNING_TIMEOUT */ |
| 4873 |
,1 /* PAMELA_ON */ |
| 4874 |
,1 /* N_CALIB */ |
| 4875 |
,1 /* AC_1_ON */ |
| 4876 |
,1 /* AC_2_ON */ |
| 4877 |
,1 /* POWER_MODE */ |
| 4878 |
,1 /* TRIG_II */ |
| 4879 |
,0 /* BUF_LEN_TRIG_II_INIT */ |
| 4880 |
,0 /* BUF_LEN_TRIG_II_ACQ */ |
| 4881 |
,1 /* EXP64_MODE */ |
| 4882 |
,1 /* EXP64_MODE_DELAY */ |
| 4883 |
,1 /* MH_END_OF_DOWNLOAD_TIMEOUT */ |
| 4884 |
,1 /* PM_STOP_RUNMANAGER_TIMEOUT */ |
| 4885 |
,1 /* PM_STOP_RUNMANAGER_TIMES_RETRY */ |
| 4886 |
,1 /* PM_N_ORBIT_CALIB */ |
| 4887 |
,1 /* WS_TIME_ORBIT */ |
| 4888 |
,1 /* WS_FAVOURITE_WS */ |
| 4889 |
,1 /* RM_N_TRIES_PREPARE_PAGE */ |
| 4890 |
,1 /* RM_TRIES_PREPARE_PAGE_SLEEP */ |
| 4891 |
,1 /* RM_WS3_TIMER_FIRE_AFTER */ |
| 4892 |
,1 /* RM_TIME_MAX_RUN */ |
| 4893 |
,1 /* RM_TIME_SPECIAL_RUN */ |
| 4894 |
,1 /* RM_ACQCHECK_PERIOD */ |
| 4895 |
,1 /* RM_FLUSH_TIMEOUT */ |
| 4896 |
,1 /* RM_NO_FLUSH_PARAM_DUMP */ |
| 4897 |
,1 /* RM_DUMP_ALL_PARAMS */ |
| 4898 |
,1 /* RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ */ |
| 4899 |
,1 /* PWR_WAIT_BEFORE_SENDTC */ |
| 4900 |
,1 /* PWR_CMD2PSB_DELAY */ |
| 4901 |
,1 /* PWR_TRB_READ_ATTEMPTS */ |
| 4902 |
,1 /* PWR_KHB_INITBOARD_TWICE_DELAY */ |
| 4903 |
,1 /* PWR_IPM_WAIT_OK_N_ATTEMPT */ |
| 4904 |
,1 /* PWR_IPM_WAIT_OK_DELAY_ATTEMPT */ |
| 4905 |
,1 /* PWR_VOLTAGE_N_ATTEMPT */ |
| 4906 |
,1 /* PWR_VOLTAGE_DELAY_ATTEMPT */ |
| 4907 |
,1 /* PWR_TRB1_SET */ |
| 4908 |
,1 /* PWR_TRB2_SET */ |
| 4909 |
,1 /* PWR_TRB_SET_DELAY */ |
| 4910 |
,1 /* PWR_TRB_READ_DELAY */ |
| 4911 |
,1 /* HB_N_ATTEMPT_WRITE2PIF */ |
| 4912 |
,1 /* HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF */ |
| 4913 |
,1 /* HB_WRITE2PIF_TIMEOUT */ |
| 4914 |
,1 /* HB_ALMOST_FULL */ |
| 4915 |
,1 /* TM_VRL_SUSPEND_HCL */ |
| 4916 |
,1 /* TM_VRL_SUSPEND_BEFORE_START */ |
| 4917 |
,1 /* DAQ_EVENT_RECEIVE_TIMEOUT */ |
| 4918 |
,1 /* DAQ_WAITFREECMDIF_N */ |
| 4919 |
,1 /* TRB_OK */ |
| 4920 |
,1 /* TRIGGER_MODE_A */ |
| 4921 |
,1 /* TRIGGER_MODE_B */ |
| 4922 |
,1 /* TRIGGER_BUSY_CONTROL */ |
| 4923 |
,1 /* TB_LINK */ |
| 4924 |
,1 /* TB_LINK_CUSTOM */ |
| 4925 |
,1 /* BUF_LEN_TB_SET_ALARM_MASK */ |
| 4926 |
,1 /* BUF_LEN_TB_SET_PMT_MASK */ |
| 4927 |
,1 /* BUF_LEN_TB_SET_S4_CAL_MASK */ |
| 4928 |
,1 /* BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT */ |
| 4929 |
,1 /* BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD */ |
| 4930 |
,1 /* TRK_OK */ |
| 4931 |
,1 /* TRK_CALIB_MODE */ |
| 4932 |
,1 /* TRK_TIME_SHORT */ |
| 4933 |
,1 /* TRK_TIME_LONG */ |
| 4934 |
,1 /* TRK_CALIB_INIT */ |
| 4935 |
,1 /* TRK_NLOOP */ |
| 4936 |
,0 /* BUF_LEN_TRK_PROGRAM */ |
| 4937 |
,1 /* BUF_LEN_TRK_TRAILER_PRG_0 */ |
| 4938 |
,1 /* BUF_LEN_TRK_TRAILER_PRG_1 */ |
| 4939 |
,1 /* BUF_LEN_TRK_TRAILER_PRG_2 */ |
| 4940 |
,1 /* BUF_LEN_TRK_TRAILER_PRG_3 */ |
| 4941 |
,1 /* BUF_LEN_TRK_TRAILER_PRG_4 */ |
| 4942 |
,1 /* BUF_LEN_TRK_TRAILER_PRG_5 */ |
| 4943 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_1_0 */ |
| 4944 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_1_1 */ |
| 4945 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_1_2 */ |
| 4946 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_1_3 */ |
| 4947 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_1_4 */ |
| 4948 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_1_5 */ |
| 4949 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_2_0 */ |
| 4950 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_2_1 */ |
| 4951 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_2_2 */ |
| 4952 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_2_3 */ |
| 4953 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_2_4 */ |
| 4954 |
,1 /* BUF_LEN_TRK_NUMBER_DSP_2_5 */ |
| 4955 |
,1 /* BUF_LEN_TRK_OPMODE_COMP_0 */ |
| 4956 |
,1 /* BUF_LEN_TRK_OPMODE_SPEC_0 */ |
| 4957 |
,1 /* BUF_LEN_TRK_OPMODE_COMP_1 */ |
| 4958 |
,1 /* BUF_LEN_TRK_OPMODE_SPEC_1 */ |
| 4959 |
,1 /* BUF_LEN_TRK_OPMODE_COMP_2 */ |
| 4960 |
,1 /* BUF_LEN_TRK_OPMODE_SPEC_2 */ |
| 4961 |
,1 /* BUF_LEN_TRK_OPMODE_COMP_3 */ |
| 4962 |
,1 /* BUF_LEN_TRK_OPMODE_SPEC_3 */ |
| 4963 |
,1 /* BUF_LEN_TRK_OPMODE_COMP_4 */ |
| 4964 |
,1 /* BUF_LEN_TRK_OPMODE_SPEC_4 */ |
| 4965 |
,1 /* BUF_LEN_TRK_OPMODE_COMP_5 */ |
| 4966 |
,1 /* BUF_LEN_TRK_OPMODE_SPEC_5 */ |
| 4967 |
,1 /* S4_OK */ |
| 4968 |
,1 /* S4_TRH */ |
| 4969 |
,1 /* S4_ATTEMPT */ |
| 4970 |
,1 /* S4_WORKING */ |
| 4971 |
,1 /* CAL_UPLOAD_CAL_FE_MASK */ |
| 4972 |
,1 /* CAL_UPLOAD_CAL_DSP_MASK */ |
| 4973 |
,1 /* CAL_VCAL */ |
| 4974 |
,1 /* CAL_CH */ |
| 4975 |
,1 /* CAL_TEMP */ |
| 4976 |
,1 /* CAL_OK */ |
| 4977 |
,1 /* CAL_CHECK_FE */ |
| 4978 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I211 */ |
| 4979 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I221 */ |
| 4980 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I231 */ |
| 4981 |
,0 /* BUF_LEN_CAL_WRITE_DSP_MEM_I41 */ |
| 4982 |
,0 /* BUF_LEN_CAL_WRITE_DSP_MEM_I42 */ |
| 4983 |
,1 /* BUF_LEN_CAL_WRITE_DSP_MEM_I43 */ |
| 4984 |
,1 /* BUF_LEN_CAL_READ_DSP_MEM_C31 */ |
| 4985 |
,1 /* BUF_LEN_CAL_READ_DSP_MEM_C32 */ |
| 4986 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I241_1 */ |
| 4987 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I241_2 */ |
| 4988 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I241_3 */ |
| 4989 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I241_4 */ |
| 4990 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I251_1 */ |
| 4991 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I251_2 */ |
| 4992 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I251_3 */ |
| 4993 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I251_4 */ |
| 4994 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I261_1 */ |
| 4995 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I261_2 */ |
| 4996 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I261_3 */ |
| 4997 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I261_4 */ |
| 4998 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I260_1 */ |
| 4999 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I260_2 */ |
| 5000 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I260_3 */ |
| 5001 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I260_4 */ |
| 5002 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I311_1 */ |
| 5003 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I311_2 */ |
| 5004 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I311_3 */ |
| 5005 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I311_4 */ |
| 5006 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I310_1 */ |
| 5007 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I310_2 */ |
| 5008 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I310_3 */ |
| 5009 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I310_4 */ |
| 5010 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I321 */ |
| 5011 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I331_1 */ |
| 5012 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I331_2 */ |
| 5013 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I331_3 */ |
| 5014 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I331_4 */ |
| 5015 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_OFF */ |
| 5016 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I341_1 */ |
| 5017 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I341_2 */ |
| 5018 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I341_3 */ |
| 5019 |
,1 /* BUF_LEN_CAL_WRITE_FPGA_REG_I341_4 */ |
| 5020 |
,1 /* AC_1_OK */ |
| 5021 |
,1 /* AC_2_OK */ |
| 5022 |
,1 /* AC_1_CHECK */ |
| 5023 |
,1 /* AC_2_CHECK */ |
| 5024 |
,1 /* AC_LOOP */ |
| 5025 |
,1 /* AC_LOOP2 */ |
| 5026 |
,1 /* BUF_LEN_AC_1_SET_DAQ */ |
| 5027 |
,1 /* BUF_LEN_AC_2_SET_DAQ */ |
| 5028 |
,0 /* BUF_LEN_AC_SEND_DSP_PROG1 */ |
| 5029 |
,0 /* BUF_LEN_AC_1_SEND_DSP_PROG2 */ |
| 5030 |
,0 /* BUF_LEN_AC_2_SEND_DSP_PROG2 */ |
| 5031 |
,1 /* BUF_LEN_AC_2_WRITE_REG */ |
| 5032 |
,1 /* BUF_LEN_AC_1_WRITE_REG */ |
| 5033 |
,1 /* BUF_LEN_AC_READ_DSP_MEM */ |
| 5034 |
,1 /* BUF_LEN_TOF_WRITE_PMT_THR_1 */ |
| 5035 |
,1 /* BUF_LEN_TOF_WRITE_PMT_THR_2 */ |
| 5036 |
,1 /* BUF_LEN_TOF_WRITE_PMT_THR_3 */ |
| 5037 |
,1 /* BUF_LEN_TOF_WRITE_PMT_THR_4 */ |
| 5038 |
,1 /* BUF_LEN_TOF_WRITE_PMT_THR_5 */ |
| 5039 |
,1 /* BUF_LEN_TOF_WRITE_PMT_THR_6 */ |
| 5040 |
,1 /* TOF_OK */ |
| 5041 |
,1 /* ND_OK */ |
| 5042 |
,1 /* ND_ATTEMPT */ |
| 5043 |
,1 /* ND_CMDS */ |
| 5044 |
,1 /* SCM_TM_DO_CHECK_VALUES_FREQ */ |
| 5045 |
,1 /* POWER_KHB */ |
| 5046 |
,1 /* PSB_TRB_S9004_ALL_ON_DELAY */ |
| 5047 |
,1 /* PSB_TRB_BIAS_WAIT */ |
| 5048 |
,1 /* PSB_CALOFE_DELAY */ |
| 5049 |
,1 /* HV_OK */ |
| 5050 |
,1 /* TSB_T_OK */ |
| 5051 |
,1 /* TSB_B_OK */ |
| 5052 |
,1 /* ALLPAGEAVAIL_ATTEMPT */ }; |
| 5053 |
|
| 5054 |
static BYTE PRH_ARR_MM_FLAG[116] = {1 /* LOG_MASK */ |
| 5055 |
,1 /* THERM_LOW */ |
| 5056 |
,1 /* THERM_HIGH */ |
| 5057 |
,0 /* BUF_TRIG_II_INIT */ |
| 5058 |
,0 /* BUF_TRIG_II_ACQ */ |
| 5059 |
,1 /* WS_1_SETTING */ |
| 5060 |
,1 /* RM_RATE_METER_S1_TRH */ |
| 5061 |
,1 /* PWR_IPM_CONF */ |
| 5062 |
,1 /* PWR_VOLTAGE_IPM_RANGE_ON_MAX */ |
| 5063 |
,1 /* PWR_VOLTAGE_IPM_RANGE_ON_MIN */ |
| 5064 |
,1 /* PWR_VOLTAGE_IPM_RANGE_OFF_MAX */ |
| 5065 |
,1 /* PWR_VOLTAGE_IPM_RANGE_OFF_MIN */ |
| 5066 |
,1 /* TM_FILTER_OPERATION */ |
| 5067 |
,1 /* TM_FILTER_VALUE */ |
| 5068 |
,1 /* BUF_TB_SET_ALARM_MASK */ |
| 5069 |
,1 /* BUF_TB_SET_PMT_MASK */ |
| 5070 |
,1 /* BUF_TB_SET_S4_CAL_MASK */ |
| 5071 |
,1 /* BUF_TB_SET_BUSY_MASK_IDAQ_HOT */ |
| 5072 |
,1 /* BUF_TB_SET_BUSY_MASK_IDAQ_COLD */ |
| 5073 |
,1 /* TRK_LOAD_PRG */ |
| 5074 |
,0 /* BUF_TRK_PROGRAM */ |
| 5075 |
,1 /* BUF_TRK_TRAILER_PRG_0 */ |
| 5076 |
,1 /* BUF_TRK_TRAILER_PRG_1 */ |
| 5077 |
,1 /* BUF_TRK_TRAILER_PRG_2 */ |
| 5078 |
,1 /* BUF_TRK_TRAILER_PRG_3 */ |
| 5079 |
,1 /* BUF_TRK_TRAILER_PRG_4 */ |
| 5080 |
,1 /* BUF_TRK_TRAILER_PRG_5 */ |
| 5081 |
,1 /* BUF_TRK_NUMBER_DSP_1_0 */ |
| 5082 |
,1 /* BUF_TRK_NUMBER_DSP_1_1 */ |
| 5083 |
,1 /* BUF_TRK_NUMBER_DSP_1_2 */ |
| 5084 |
,1 /* BUF_TRK_NUMBER_DSP_1_3 */ |
| 5085 |
,1 /* BUF_TRK_NUMBER_DSP_1_4 */ |
| 5086 |
,1 /* BUF_TRK_NUMBER_DSP_1_5 */ |
| 5087 |
,1 /* BUF_TRK_NUMBER_DSP_2_0 */ |
| 5088 |
,1 /* BUF_TRK_NUMBER_DSP_2_1 */ |
| 5089 |
,1 /* BUF_TRK_NUMBER_DSP_2_2 */ |
| 5090 |
,1 /* BUF_TRK_NUMBER_DSP_2_3 */ |
| 5091 |
,1 /* BUF_TRK_NUMBER_DSP_2_4 */ |
| 5092 |
,1 /* BUF_TRK_NUMBER_DSP_2_5 */ |
| 5093 |
,1 /* BUF_TRK_OPMODE_COMP_0 */ |
| 5094 |
,1 /* BUF_TRK_OPMODE_SPEC_0 */ |
| 5095 |
,1 /* BUF_TRK_OPMODE_COMP_1 */ |
| 5096 |
,1 /* BUF_TRK_OPMODE_SPEC_1 */ |
| 5097 |
,1 /* BUF_TRK_OPMODE_COMP_2 */ |
| 5098 |
,1 /* BUF_TRK_OPMODE_SPEC_2 */ |
| 5099 |
,1 /* BUF_TRK_OPMODE_COMP_3 */ |
| 5100 |
,1 /* BUF_TRK_OPMODE_SPEC_3 */ |
| 5101 |
,1 /* BUF_TRK_OPMODE_COMP_4 */ |
| 5102 |
,1 /* BUF_TRK_OPMODE_SPEC_4 */ |
| 5103 |
,1 /* BUF_TRK_OPMODE_COMP_5 */ |
| 5104 |
,1 /* BUF_TRK_OPMODE_SPEC_5 */ |
| 5105 |
,1 /* CAL_COUNT */ |
| 5106 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I211 */ |
| 5107 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I221 */ |
| 5108 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I231 */ |
| 5109 |
,0 /* BUF_CAL_WRITE_DSP_MEM_I41 */ |
| 5110 |
,0 /* BUF_CAL_WRITE_DSP_MEM_I42 */ |
| 5111 |
,1 /* BUF_CAL_WRITE_DSP_MEM_I43 */ |
| 5112 |
,1 /* BUF_CAL_READ_DSP_MEM_C31 */ |
| 5113 |
,1 /* BUF_CAL_READ_DSP_MEM_C32 */ |
| 5114 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I241_1 */ |
| 5115 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I241_2 */ |
| 5116 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I241_3 */ |
| 5117 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I241_4 */ |
| 5118 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I251_1 */ |
| 5119 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I251_2 */ |
| 5120 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I251_3 */ |
| 5121 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I251_4 */ |
| 5122 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I261_1 */ |
| 5123 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I261_2 */ |
| 5124 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I261_3 */ |
| 5125 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I261_4 */ |
| 5126 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I260_1 */ |
| 5127 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I260_2 */ |
| 5128 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I260_3 */ |
| 5129 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I260_4 */ |
| 5130 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I311_1 */ |
| 5131 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I311_2 */ |
| 5132 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I311_3 */ |
| 5133 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I311_4 */ |
| 5134 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I310_1 */ |
| 5135 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I310_2 */ |
| 5136 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I310_3 */ |
| 5137 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I310_4 */ |
| 5138 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I321 */ |
| 5139 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I331_1 */ |
| 5140 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I331_2 */ |
| 5141 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I331_3 */ |
| 5142 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I331_4 */ |
| 5143 |
,1 /* BUF_CAL_WRITE_FPGA_REG_OFF */ |
| 5144 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I341_1 */ |
| 5145 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I341_2 */ |
| 5146 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I341_3 */ |
| 5147 |
,1 /* BUF_CAL_WRITE_FPGA_REG_I341_4 */ |
| 5148 |
,1 /* BUF_AC_1_SET_DAQ */ |
| 5149 |
,1 /* BUF_AC_2_SET_DAQ */ |
| 5150 |
,0 /* BUF_AC_SEND_DSP_PROG1 */ |
| 5151 |
,0 /* BUF_AC_1_SEND_DSP_PROG2 */ |
| 5152 |
,0 /* BUF_AC_2_SEND_DSP_PROG2 */ |
| 5153 |
,1 /* BUF_AC_2_WRITE_REG */ |
| 5154 |
,1 /* BUF_AC_1_WRITE_REG */ |
| 5155 |
,1 /* BUF_AC_READ_DSP_MEM */ |
| 5156 |
,1 /* BUF_TOF_WRITE_PMT_THR_1 */ |
| 5157 |
,1 /* BUF_TOF_WRITE_PMT_THR_2 */ |
| 5158 |
,1 /* BUF_TOF_WRITE_PMT_THR_3 */ |
| 5159 |
,1 /* BUF_TOF_WRITE_PMT_THR_4 */ |
| 5160 |
,1 /* BUF_TOF_WRITE_PMT_THR_5 */ |
| 5161 |
,1 /* BUF_TOF_WRITE_PMT_THR_6 */ |
| 5162 |
,1 /* TOF_PLAN */ |
| 5163 |
,1 /* PM_PERIODIC_DELAY */ |
| 5164 |
,1 /* PSB_COMMANDS */ |
| 5165 |
,1 /* PSB_CALO_FE_ON */ |
| 5166 |
,1 /* PSB_CALO_FE_OFF */ |
| 5167 |
,1 /* PSB_CALO_FE */ |
| 5168 |
,1 /* HVB_COMMANDS */ |
| 5169 |
,1 /* TSB_BOARD_OK */ }; |
| 5170 |
|
| 5171 |
|
| 5172 |
static BYTE PRH_TAB_MM_FLAG[14] = {1 /* CONF */ |
| 5173 |
,1 /* PWR_IPM_ACTION */ |
| 5174 |
,1 /* TRK_DSP_OK */ |
| 5175 |
,1 /* TRK_DSP_MASK */ |
| 5176 |
,1 /* TRK_PED_MIN_0 */ |
| 5177 |
,1 /* TRK_PED_MIN_1 */ |
| 5178 |
,1 /* TRK_PED_MAX_0 */ |
| 5179 |
,1 /* TRK_PED_MAX_1 */ |
| 5180 |
,1 /* TRK_SIG_MIN_0 */ |
| 5181 |
,1 /* TRK_SIG_MIN_1 */ |
| 5182 |
,1 /* TRK_SIG_MAX_0 */ |
| 5183 |
,1 /* TRK_SIG_MAX_1 */ |
| 5184 |
,1 /* TRK_BAD_MAX_0 */ |
| 5185 |
,1 /* TRK_BAD_MAX_1 */ }; |
| 5186 |
|
| 5187 |
|
| 5188 |
UINT32 PRH_var_dump_len; |
| 5189 |
static PRH_VAR_TYPE* PRH_VAR_PTR[206] = {&PRH_VAR_LU_WRITE_ON_UART |
| 5190 |
,&PRH_VAR_VERBOSE_DEBUG |
| 5191 |
,&PRH_VAR_DOWNLOAD_HEADER |
| 5192 |
,&PRH_VAR_KHB_ALARM_REG_LOW_LEVEL_MASK |
| 5193 |
,&PRH_VAR_KHB_STATUS_REG_LOW_LEVEL_MASK |
| 5194 |
,&PRH_VAR_PULSER_ACTION |
| 5195 |
,&PRH_VAR_N_BOOT |
| 5196 |
,&PRH_VAR_THERMISTORS_CHECK |
| 5197 |
,&PRH_VAR_THERM_MASK |
| 5198 |
,&PRH_VAR_IPM_VOLTAGES_CHECK |
| 5199 |
,&PRH_VAR_KHB_IDAQ_CHECK |
| 5200 |
,&PRH_VAR_NTRIG |
| 5201 |
,&PRH_VAR_TRIG |
| 5202 |
,&PRH_VAR_CONF_SEL |
| 5203 |
,&PRH_VAR_CONFOK |
| 5204 |
,&PRH_VAR_OFF |
| 5205 |
,&PRH_VAR_NOFF |
| 5206 |
,&PRH_VAR_NRES |
| 5207 |
,&PRH_VAR_RES |
| 5208 |
,&PRH_VAR_WATCHDOG_RESET_DISABLE |
| 5209 |
,&PRH_VAR_NFAILED_POWER_ON |
| 5210 |
,&PRH_VAR_AUTO_RM_MODE |
| 5211 |
,&PRH_VAR_AUTO_SCM_MODE |
| 5212 |
,&PRH_VAR_MASK_ACQ_ALARM |
| 5213 |
,&PRH_VAR_GOM_DURING_ALARM |
| 5214 |
,&PRH_VAR_PM_FORCE_RUNNING_TIMEOUT |
| 5215 |
,&PRH_VAR_PAMELA_ON |
| 5216 |
,&PRH_VAR_N_CALIB |
| 5217 |
,&PRH_VAR_AC_1_ON |
| 5218 |
,&PRH_VAR_AC_2_ON |
| 5219 |
,&PRH_VAR_POWER_MODE |
| 5220 |
,&PRH_VAR_TRIG_II |
| 5221 |
,&PRH_VAR_BUF_LEN_TRIG_II_INIT |
| 5222 |
,&PRH_VAR_BUF_LEN_TRIG_II_ACQ |
| 5223 |
,&PRH_VAR_EXP64_MODE |
| 5224 |
,&PRH_VAR_EXP64_MODE_DELAY |
| 5225 |
,&PRH_VAR_MH_END_OF_DOWNLOAD_TIMEOUT |
| 5226 |
,&PRH_VAR_PM_STOP_RUNMANAGER_TIMEOUT |
| 5227 |
,&PRH_VAR_PM_STOP_RUNMANAGER_TIMES_RETRY |
| 5228 |
,&PRH_VAR_PM_N_ORBIT_CALIB |
| 5229 |
,&PRH_VAR_WS_TIME_ORBIT |
| 5230 |
,&PRH_VAR_WS_FAVOURITE_WS |
| 5231 |
,&PRH_VAR_RM_N_TRIES_PREPARE_PAGE |
| 5232 |
,&PRH_VAR_RM_TRIES_PREPARE_PAGE_SLEEP |
| 5233 |
,&PRH_VAR_RM_WS3_TIMER_FIRE_AFTER |
| 5234 |
,&PRH_VAR_RM_TIME_MAX_RUN |
| 5235 |
,&PRH_VAR_RM_TIME_SPECIAL_RUN |
| 5236 |
,&PRH_VAR_RM_ACQCHECK_PERIOD |
| 5237 |
,&PRH_VAR_RM_FLUSH_TIMEOUT |
| 5238 |
,&PRH_VAR_RM_NO_FLUSH_PARAM_DUMP |
| 5239 |
,&PRH_VAR_RM_DUMP_ALL_PARAMS |
| 5240 |
,&PRH_VAR_RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ |
| 5241 |
,&PRH_VAR_PWR_WAIT_BEFORE_SENDTC |
| 5242 |
,&PRH_VAR_PWR_CMD2PSB_DELAY |
| 5243 |
,&PRH_VAR_PWR_TRB_READ_ATTEMPTS |
| 5244 |
,&PRH_VAR_PWR_KHB_INITBOARD_TWICE_DELAY |
| 5245 |
,&PRH_VAR_PWR_IPM_WAIT_OK_N_ATTEMPT |
| 5246 |
,&PRH_VAR_PWR_IPM_WAIT_OK_DELAY_ATTEMPT |
| 5247 |
,&PRH_VAR_PWR_VOLTAGE_N_ATTEMPT |
| 5248 |
,&PRH_VAR_PWR_VOLTAGE_DELAY_ATTEMPT |
| 5249 |
,&PRH_VAR_PWR_TRB1_SET |
| 5250 |
,&PRH_VAR_PWR_TRB2_SET |
| 5251 |
,&PRH_VAR_PWR_TRB_SET_DELAY |
| 5252 |
,&PRH_VAR_PWR_TRB_READ_DELAY |
| 5253 |
,&PRH_VAR_HB_N_ATTEMPT_WRITE2PIF |
| 5254 |
,&PRH_VAR_HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF |
| 5255 |
,&PRH_VAR_HB_WRITE2PIF_TIMEOUT |
| 5256 |
,&PRH_VAR_HB_ALMOST_FULL |
| 5257 |
,&PRH_VAR_TM_VRL_SUSPEND_HCL |
| 5258 |
,&PRH_VAR_TM_VRL_SUSPEND_BEFORE_START |
| 5259 |
,&PRH_VAR_DAQ_EVENT_RECEIVE_TIMEOUT |
| 5260 |
,&PRH_VAR_DAQ_WAITFREECMDIF_N |
| 5261 |
,&PRH_VAR_TRB_OK |
| 5262 |
,&PRH_VAR_TRIGGER_MODE_A |
| 5263 |
,&PRH_VAR_TRIGGER_MODE_B |
| 5264 |
,&PRH_VAR_TRIGGER_BUSY_CONTROL |
| 5265 |
,&PRH_VAR_TB_LINK |
| 5266 |
,&PRH_VAR_TB_LINK_CUSTOM |
| 5267 |
,&PRH_VAR_BUF_LEN_TB_SET_ALARM_MASK |
| 5268 |
,&PRH_VAR_BUF_LEN_TB_SET_PMT_MASK |
| 5269 |
,&PRH_VAR_BUF_LEN_TB_SET_S4_CAL_MASK |
| 5270 |
,&PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT |
| 5271 |
,&PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD |
| 5272 |
,&PRH_VAR_TRK_OK |
| 5273 |
,&PRH_VAR_TRK_CALIB_MODE |
| 5274 |
,&PRH_VAR_TRK_TIME_SHORT |
| 5275 |
,&PRH_VAR_TRK_TIME_LONG |
| 5276 |
,&PRH_VAR_TRK_CALIB_INIT |
| 5277 |
,&PRH_VAR_TRK_NLOOP |
| 5278 |
,&PRH_VAR_BUF_LEN_TRK_PROGRAM |
| 5279 |
,&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_0 |
| 5280 |
,&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_1 |
| 5281 |
,&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_2 |
| 5282 |
,&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_3 |
| 5283 |
,&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_4 |
| 5284 |
,&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_5 |
| 5285 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_0 |
| 5286 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_1 |
| 5287 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_2 |
| 5288 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_3 |
| 5289 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_4 |
| 5290 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_5 |
| 5291 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_0 |
| 5292 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_1 |
| 5293 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_2 |
| 5294 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_3 |
| 5295 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_4 |
| 5296 |
,&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_5 |
| 5297 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_0 |
| 5298 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_0 |
| 5299 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_1 |
| 5300 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_1 |
| 5301 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_2 |
| 5302 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_2 |
| 5303 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_3 |
| 5304 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_3 |
| 5305 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_4 |
| 5306 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_4 |
| 5307 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_5 |
| 5308 |
,&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_5 |
| 5309 |
,&PRH_VAR_S4_OK |
| 5310 |
,&PRH_VAR_S4_TRH |
| 5311 |
,&PRH_VAR_S4_ATTEMPT |
| 5312 |
,&PRH_VAR_S4_WORKING |
| 5313 |
,&PRH_VAR_CAL_UPLOAD_CAL_FE_MASK |
| 5314 |
,&PRH_VAR_CAL_UPLOAD_CAL_DSP_MASK |
| 5315 |
,&PRH_VAR_CAL_VCAL |
| 5316 |
,&PRH_VAR_CAL_CH |
| 5317 |
,&PRH_VAR_CAL_TEMP |
| 5318 |
,&PRH_VAR_CAL_OK |
| 5319 |
,&PRH_VAR_CAL_CHECK_FE |
| 5320 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I211 |
| 5321 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I221 |
| 5322 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I231 |
| 5323 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I41 |
| 5324 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I42 |
| 5325 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I43 |
| 5326 |
,&PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C31 |
| 5327 |
,&PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C32 |
| 5328 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_1 |
| 5329 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_2 |
| 5330 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_3 |
| 5331 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_4 |
| 5332 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_1 |
| 5333 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_2 |
| 5334 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_3 |
| 5335 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_4 |
| 5336 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_1 |
| 5337 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_2 |
| 5338 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_3 |
| 5339 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_4 |
| 5340 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_1 |
| 5341 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_2 |
| 5342 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_3 |
| 5343 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_4 |
| 5344 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_1 |
| 5345 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_2 |
| 5346 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_3 |
| 5347 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_4 |
| 5348 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_1 |
| 5349 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_2 |
| 5350 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_3 |
| 5351 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_4 |
| 5352 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I321 |
| 5353 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_1 |
| 5354 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_2 |
| 5355 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_3 |
| 5356 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_4 |
| 5357 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_OFF |
| 5358 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_1 |
| 5359 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_2 |
| 5360 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_3 |
| 5361 |
,&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_4 |
| 5362 |
,&PRH_VAR_AC_1_OK |
| 5363 |
,&PRH_VAR_AC_2_OK |
| 5364 |
,&PRH_VAR_AC_1_CHECK |
| 5365 |
,&PRH_VAR_AC_2_CHECK |
| 5366 |
,&PRH_VAR_AC_LOOP |
| 5367 |
,&PRH_VAR_AC_LOOP2 |
| 5368 |
,&PRH_VAR_BUF_LEN_AC_1_SET_DAQ |
| 5369 |
,&PRH_VAR_BUF_LEN_AC_2_SET_DAQ |
| 5370 |
,&PRH_VAR_BUF_LEN_AC_SEND_DSP_PROG1 |
| 5371 |
,&PRH_VAR_BUF_LEN_AC_1_SEND_DSP_PROG2 |
| 5372 |
,&PRH_VAR_BUF_LEN_AC_2_SEND_DSP_PROG2 |
| 5373 |
,&PRH_VAR_BUF_LEN_AC_2_WRITE_REG |
| 5374 |
,&PRH_VAR_BUF_LEN_AC_1_WRITE_REG |
| 5375 |
,&PRH_VAR_BUF_LEN_AC_READ_DSP_MEM |
| 5376 |
,&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_1 |
| 5377 |
,&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_2 |
| 5378 |
,&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_3 |
| 5379 |
,&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_4 |
| 5380 |
,&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_5 |
| 5381 |
,&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_6 |
| 5382 |
,&PRH_VAR_TOF_OK |
| 5383 |
,&PRH_VAR_ND_OK |
| 5384 |
,&PRH_VAR_ND_ATTEMPT |
| 5385 |
,&PRH_VAR_ND_CMDS |
| 5386 |
,&PRH_VAR_SCM_TM_DO_CHECK_VALUES_FREQ |
| 5387 |
,&PRH_VAR_POWER_KHB |
| 5388 |
,&PRH_VAR_PSB_TRB_S9004_ALL_ON_DELAY |
| 5389 |
,&PRH_VAR_PSB_TRB_BIAS_WAIT |
| 5390 |
,&PRH_VAR_PSB_CALOFE_DELAY |
| 5391 |
,&PRH_VAR_HV_OK |
| 5392 |
,&PRH_VAR_TSB_T_OK |
| 5393 |
,&PRH_VAR_TSB_B_OK |
| 5394 |
,&PRH_VAR_ALLPAGEAVAIL_ATTEMPT}; |
| 5395 |
|
| 5396 |
|
| 5397 |
static PRH_VAR_TYPE* PRH_ARR_PTR[116] = {PRH_ARR_LOG_MASK |
| 5398 |
,PRH_ARR_THERM_LOW |
| 5399 |
,PRH_ARR_THERM_HIGH |
| 5400 |
,PRH_ARR_BUF_TRIG_II_INIT |
| 5401 |
,PRH_ARR_BUF_TRIG_II_ACQ |
| 5402 |
,PRH_ARR_WS_1_SETTING |
| 5403 |
,PRH_ARR_RM_RATE_METER_S1_TRH |
| 5404 |
,PRH_ARR_PWR_IPM_CONF |
| 5405 |
,PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MAX |
| 5406 |
,PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MIN |
| 5407 |
,PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MAX |
| 5408 |
,PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MIN |
| 5409 |
,PRH_ARR_TM_FILTER_OPERATION |
| 5410 |
,PRH_ARR_TM_FILTER_VALUE |
| 5411 |
,PRH_ARR_BUF_TB_SET_ALARM_MASK |
| 5412 |
,PRH_ARR_BUF_TB_SET_PMT_MASK |
| 5413 |
,PRH_ARR_BUF_TB_SET_S4_CAL_MASK |
| 5414 |
,PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_HOT |
| 5415 |
,PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_COLD |
| 5416 |
,PRH_ARR_TRK_LOAD_PRG |
| 5417 |
,PRH_ARR_BUF_TRK_PROGRAM |
| 5418 |
,PRH_ARR_BUF_TRK_TRAILER_PRG_0 |
| 5419 |
,PRH_ARR_BUF_TRK_TRAILER_PRG_1 |
| 5420 |
,PRH_ARR_BUF_TRK_TRAILER_PRG_2 |
| 5421 |
,PRH_ARR_BUF_TRK_TRAILER_PRG_3 |
| 5422 |
,PRH_ARR_BUF_TRK_TRAILER_PRG_4 |
| 5423 |
,PRH_ARR_BUF_TRK_TRAILER_PRG_5 |
| 5424 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_1_0 |
| 5425 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_1_1 |
| 5426 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_1_2 |
| 5427 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_1_3 |
| 5428 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_1_4 |
| 5429 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_1_5 |
| 5430 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_2_0 |
| 5431 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_2_1 |
| 5432 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_2_2 |
| 5433 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_2_3 |
| 5434 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_2_4 |
| 5435 |
,PRH_ARR_BUF_TRK_NUMBER_DSP_2_5 |
| 5436 |
,PRH_ARR_BUF_TRK_OPMODE_COMP_0 |
| 5437 |
,PRH_ARR_BUF_TRK_OPMODE_SPEC_0 |
| 5438 |
,PRH_ARR_BUF_TRK_OPMODE_COMP_1 |
| 5439 |
,PRH_ARR_BUF_TRK_OPMODE_SPEC_1 |
| 5440 |
,PRH_ARR_BUF_TRK_OPMODE_COMP_2 |
| 5441 |
,PRH_ARR_BUF_TRK_OPMODE_SPEC_2 |
| 5442 |
,PRH_ARR_BUF_TRK_OPMODE_COMP_3 |
| 5443 |
,PRH_ARR_BUF_TRK_OPMODE_SPEC_3 |
| 5444 |
,PRH_ARR_BUF_TRK_OPMODE_COMP_4 |
| 5445 |
,PRH_ARR_BUF_TRK_OPMODE_SPEC_4 |
| 5446 |
,PRH_ARR_BUF_TRK_OPMODE_COMP_5 |
| 5447 |
,PRH_ARR_BUF_TRK_OPMODE_SPEC_5 |
| 5448 |
,PRH_ARR_CAL_COUNT |
| 5449 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I211 |
| 5450 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I221 |
| 5451 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I231 |
| 5452 |
,PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I41 |
| 5453 |
,PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I42 |
| 5454 |
,PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I43 |
| 5455 |
,PRH_ARR_BUF_CAL_READ_DSP_MEM_C31 |
| 5456 |
,PRH_ARR_BUF_CAL_READ_DSP_MEM_C32 |
| 5457 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_1 |
| 5458 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_2 |
| 5459 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_3 |
| 5460 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_4 |
| 5461 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_1 |
| 5462 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_2 |
| 5463 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_3 |
| 5464 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_4 |
| 5465 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_1 |
| 5466 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_2 |
| 5467 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_3 |
| 5468 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_4 |
| 5469 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_1 |
| 5470 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_2 |
| 5471 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_3 |
| 5472 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_4 |
| 5473 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_1 |
| 5474 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_2 |
| 5475 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_3 |
| 5476 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_4 |
| 5477 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_1 |
| 5478 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_2 |
| 5479 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_3 |
| 5480 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_4 |
| 5481 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I321 |
| 5482 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_1 |
| 5483 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_2 |
| 5484 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_3 |
| 5485 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_4 |
| 5486 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_OFF |
| 5487 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_1 |
| 5488 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_2 |
| 5489 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_3 |
| 5490 |
,PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_4 |
| 5491 |
,PRH_ARR_BUF_AC_1_SET_DAQ |
| 5492 |
,PRH_ARR_BUF_AC_2_SET_DAQ |
| 5493 |
,PRH_ARR_BUF_AC_SEND_DSP_PROG1 |
| 5494 |
,PRH_ARR_BUF_AC_1_SEND_DSP_PROG2 |
| 5495 |
,PRH_ARR_BUF_AC_2_SEND_DSP_PROG2 |
| 5496 |
,PRH_ARR_BUF_AC_2_WRITE_REG |
| 5497 |
,PRH_ARR_BUF_AC_1_WRITE_REG |
| 5498 |
,PRH_ARR_BUF_AC_READ_DSP_MEM |
| 5499 |
,PRH_ARR_BUF_TOF_WRITE_PMT_THR_1 |
| 5500 |
,PRH_ARR_BUF_TOF_WRITE_PMT_THR_2 |
| 5501 |
,PRH_ARR_BUF_TOF_WRITE_PMT_THR_3 |
| 5502 |
,PRH_ARR_BUF_TOF_WRITE_PMT_THR_4 |
| 5503 |
,PRH_ARR_BUF_TOF_WRITE_PMT_THR_5 |
| 5504 |
,PRH_ARR_BUF_TOF_WRITE_PMT_THR_6 |
| 5505 |
,PRH_ARR_TOF_PLAN |
| 5506 |
,PRH_ARR_PM_PERIODIC_DELAY |
| 5507 |
,PRH_ARR_PSB_COMMANDS |
| 5508 |
,PRH_ARR_PSB_CALO_FE_ON |
| 5509 |
,PRH_ARR_PSB_CALO_FE_OFF |
| 5510 |
,PRH_ARR_PSB_CALO_FE |
| 5511 |
,PRH_ARR_HVB_COMMANDS |
| 5512 |
,PRH_ARR_TSB_BOARD_OK}; |
| 5513 |
|
| 5514 |
|
| 5515 |
UINT32 PRH_arr_dump_len; |
| 5516 |
static unsigned int PRH_ARR_N[116] = {PRH_ARR_N_LOG_MASK |
| 5517 |
,PRH_ARR_N_THERM_LOW |
| 5518 |
,PRH_ARR_N_THERM_HIGH |
| 5519 |
,PRH_ARR_N_BUF_TRIG_II_INIT |
| 5520 |
,PRH_ARR_N_BUF_TRIG_II_ACQ |
| 5521 |
,PRH_ARR_N_WS_1_SETTING |
| 5522 |
,PRH_ARR_N_RM_RATE_METER_S1_TRH |
| 5523 |
,PRH_ARR_N_PWR_IPM_CONF |
| 5524 |
,PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_ON_MAX |
| 5525 |
,PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_ON_MIN |
| 5526 |
,PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_OFF_MAX |
| 5527 |
,PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_OFF_MIN |
| 5528 |
,PRH_ARR_N_TM_FILTER_OPERATION |
| 5529 |
,PRH_ARR_N_TM_FILTER_VALUE |
| 5530 |
,PRH_ARR_N_BUF_TB_SET_ALARM_MASK |
| 5531 |
,PRH_ARR_N_BUF_TB_SET_PMT_MASK |
| 5532 |
,PRH_ARR_N_BUF_TB_SET_S4_CAL_MASK |
| 5533 |
,PRH_ARR_N_BUF_TB_SET_BUSY_MASK_IDAQ_HOT |
| 5534 |
,PRH_ARR_N_BUF_TB_SET_BUSY_MASK_IDAQ_COLD |
| 5535 |
,PRH_ARR_N_TRK_LOAD_PRG |
| 5536 |
,PRH_ARR_N_BUF_TRK_PROGRAM |
| 5537 |
,PRH_ARR_N_BUF_TRK_TRAILER_PRG_0 |
| 5538 |
,PRH_ARR_N_BUF_TRK_TRAILER_PRG_1 |
| 5539 |
,PRH_ARR_N_BUF_TRK_TRAILER_PRG_2 |
| 5540 |
,PRH_ARR_N_BUF_TRK_TRAILER_PRG_3 |
| 5541 |
,PRH_ARR_N_BUF_TRK_TRAILER_PRG_4 |
| 5542 |
,PRH_ARR_N_BUF_TRK_TRAILER_PRG_5 |
| 5543 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_0 |
| 5544 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_1 |
| 5545 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_2 |
| 5546 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_3 |
| 5547 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_4 |
| 5548 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_5 |
| 5549 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_0 |
| 5550 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_1 |
| 5551 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_2 |
| 5552 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_3 |
| 5553 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_4 |
| 5554 |
,PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_5 |
| 5555 |
,PRH_ARR_N_BUF_TRK_OPMODE_COMP_0 |
| 5556 |
,PRH_ARR_N_BUF_TRK_OPMODE_SPEC_0 |
| 5557 |
,PRH_ARR_N_BUF_TRK_OPMODE_COMP_1 |
| 5558 |
,PRH_ARR_N_BUF_TRK_OPMODE_SPEC_1 |
| 5559 |
,PRH_ARR_N_BUF_TRK_OPMODE_COMP_2 |
| 5560 |
,PRH_ARR_N_BUF_TRK_OPMODE_SPEC_2 |
| 5561 |
,PRH_ARR_N_BUF_TRK_OPMODE_COMP_3 |
| 5562 |
,PRH_ARR_N_BUF_TRK_OPMODE_SPEC_3 |
| 5563 |
,PRH_ARR_N_BUF_TRK_OPMODE_COMP_4 |
| 5564 |
,PRH_ARR_N_BUF_TRK_OPMODE_SPEC_4 |
| 5565 |
,PRH_ARR_N_BUF_TRK_OPMODE_COMP_5 |
| 5566 |
,PRH_ARR_N_BUF_TRK_OPMODE_SPEC_5 |
| 5567 |
,PRH_ARR_N_CAL_COUNT |
| 5568 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I211 |
| 5569 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I221 |
| 5570 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I231 |
| 5571 |
,PRH_ARR_N_BUF_CAL_WRITE_DSP_MEM_I41 |
| 5572 |
,PRH_ARR_N_BUF_CAL_WRITE_DSP_MEM_I42 |
| 5573 |
,PRH_ARR_N_BUF_CAL_WRITE_DSP_MEM_I43 |
| 5574 |
,PRH_ARR_N_BUF_CAL_READ_DSP_MEM_C31 |
| 5575 |
,PRH_ARR_N_BUF_CAL_READ_DSP_MEM_C32 |
| 5576 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_1 |
| 5577 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_2 |
| 5578 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_3 |
| 5579 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_4 |
| 5580 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_1 |
| 5581 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_2 |
| 5582 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_3 |
| 5583 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_4 |
| 5584 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_1 |
| 5585 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_2 |
| 5586 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_3 |
| 5587 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_4 |
| 5588 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_1 |
| 5589 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_2 |
| 5590 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_3 |
| 5591 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_4 |
| 5592 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_1 |
| 5593 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_2 |
| 5594 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_3 |
| 5595 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_4 |
| 5596 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_1 |
| 5597 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_2 |
| 5598 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_3 |
| 5599 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_4 |
| 5600 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I321 |
| 5601 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_1 |
| 5602 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_2 |
| 5603 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_3 |
| 5604 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_4 |
| 5605 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_OFF |
| 5606 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_1 |
| 5607 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_2 |
| 5608 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_3 |
| 5609 |
,PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_4 |
| 5610 |
,PRH_ARR_N_BUF_AC_1_SET_DAQ |
| 5611 |
,PRH_ARR_N_BUF_AC_2_SET_DAQ |
| 5612 |
,PRH_ARR_N_BUF_AC_SEND_DSP_PROG1 |
| 5613 |
,PRH_ARR_N_BUF_AC_1_SEND_DSP_PROG2 |
| 5614 |
,PRH_ARR_N_BUF_AC_2_SEND_DSP_PROG2 |
| 5615 |
,PRH_ARR_N_BUF_AC_2_WRITE_REG |
| 5616 |
,PRH_ARR_N_BUF_AC_1_WRITE_REG |
| 5617 |
,PRH_ARR_N_BUF_AC_READ_DSP_MEM |
| 5618 |
,PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_1 |
| 5619 |
,PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_2 |
| 5620 |
,PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_3 |
| 5621 |
,PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_4 |
| 5622 |
,PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_5 |
| 5623 |
,PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_6 |
| 5624 |
,PRH_ARR_N_TOF_PLAN |
| 5625 |
,PRH_ARR_N_PM_PERIODIC_DELAY |
| 5626 |
,PRH_ARR_N_PSB_COMMANDS |
| 5627 |
,PRH_ARR_N_PSB_CALO_FE_ON |
| 5628 |
,PRH_ARR_N_PSB_CALO_FE_OFF |
| 5629 |
,PRH_ARR_N_PSB_CALO_FE |
| 5630 |
,PRH_ARR_N_HVB_COMMANDS |
| 5631 |
,PRH_ARR_N_TSB_BOARD_OK}; |
| 5632 |
|
| 5633 |
|
| 5634 |
static PRH_VAR_TYPE* PRH_TAB_PTR[14] = {(PRH_VAR_TYPE *)PRH_TAB_CONF |
| 5635 |
,(PRH_VAR_TYPE *)PRH_TAB_PWR_IPM_ACTION |
| 5636 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_DSP_OK |
| 5637 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_DSP_MASK |
| 5638 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MIN_0 |
| 5639 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MIN_1 |
| 5640 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MAX_0 |
| 5641 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MAX_1 |
| 5642 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MIN_0 |
| 5643 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MIN_1 |
| 5644 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MAX_0 |
| 5645 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MAX_1 |
| 5646 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_BAD_MAX_0 |
| 5647 |
,(PRH_VAR_TYPE *)PRH_TAB_TRK_BAD_MAX_1}; |
| 5648 |
|
| 5649 |
|
| 5650 |
UINT32 PRH_tab_dump_len; |
| 5651 |
static unsigned int PRH_TAB_NCOL[14] = {PRH_TAB_NCOL_CONF |
| 5652 |
,PRH_TAB_NCOL_PWR_IPM_ACTION |
| 5653 |
,PRH_TAB_NCOL_TRK_DSP_OK |
| 5654 |
,PRH_TAB_NCOL_TRK_DSP_MASK |
| 5655 |
,PRH_TAB_NCOL_TRK_PED_MIN_0 |
| 5656 |
,PRH_TAB_NCOL_TRK_PED_MIN_1 |
| 5657 |
,PRH_TAB_NCOL_TRK_PED_MAX_0 |
| 5658 |
,PRH_TAB_NCOL_TRK_PED_MAX_1 |
| 5659 |
,PRH_TAB_NCOL_TRK_SIG_MIN_0 |
| 5660 |
,PRH_TAB_NCOL_TRK_SIG_MIN_1 |
| 5661 |
,PRH_TAB_NCOL_TRK_SIG_MAX_0 |
| 5662 |
,PRH_TAB_NCOL_TRK_SIG_MAX_1 |
| 5663 |
,PRH_TAB_NCOL_TRK_BAD_MAX_0 |
| 5664 |
,PRH_TAB_NCOL_TRK_BAD_MAX_1}; |
| 5665 |
|
| 5666 |
|
| 5667 |
static unsigned int PRH_TAB_NROW[14] = {PRH_TAB_NROW_CONF |
| 5668 |
,PRH_TAB_NROW_PWR_IPM_ACTION |
| 5669 |
,PRH_TAB_NROW_TRK_DSP_OK |
| 5670 |
,PRH_TAB_NROW_TRK_DSP_MASK |
| 5671 |
,PRH_TAB_NROW_TRK_PED_MIN_0 |
| 5672 |
,PRH_TAB_NROW_TRK_PED_MIN_1 |
| 5673 |
,PRH_TAB_NROW_TRK_PED_MAX_0 |
| 5674 |
,PRH_TAB_NROW_TRK_PED_MAX_1 |
| 5675 |
,PRH_TAB_NROW_TRK_SIG_MIN_0 |
| 5676 |
,PRH_TAB_NROW_TRK_SIG_MIN_1 |
| 5677 |
,PRH_TAB_NROW_TRK_SIG_MAX_0 |
| 5678 |
,PRH_TAB_NROW_TRK_SIG_MAX_1 |
| 5679 |
,PRH_TAB_NROW_TRK_BAD_MAX_0 |
| 5680 |
,PRH_TAB_NROW_TRK_BAD_MAX_1}; |
| 5681 |
|
| 5682 |
|
| 5683 |
|
| 5684 |
/* |
| 5685 |
* this function must be invoked before the pamela software starts and before set_all_to_default |
| 5686 |
*/ |
| 5687 |
status_code PRH_int_init_internal_structure() { |
| 5688 |
|
| 5689 |
// unsigned int prec_flash = PRH_FLASH_BASE_ADDR; |
| 5690 |
UINT32 prec_eeprom = 0; |
| 5691 |
|
| 5692 |
// init DEFAULT_VAR: |
| 5693 |
|
| 5694 |
int i; |
| 5695 |
BOOL mm; |
| 5696 |
UINT32 size; |
| 5697 |
|
| 5698 |
|
| 5699 |
// PRH_VAR_PTR[0]=&PRH_VAR_LU_WRITE_ON_UART; |
| 5700 |
PRH_VAR_EEPROM_ADDR[0]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_LU_WRITE_ON_UART); |
| 5701 |
#ifdef I386 |
| 5702 |
PRH_VAR_NAME[0]="LU_WRITE_ON_UART" |
| 5703 |
#endif // ifdef I386 |
| 5704 |
// PRH_VAR_PTR[1]=&PRH_VAR_VERBOSE_DEBUG; |
| 5705 |
PRH_VAR_EEPROM_ADDR[1]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_VERBOSE_DEBUG); |
| 5706 |
#ifdef I386 |
| 5707 |
PRH_VAR_NAME[1]="VERBOSE_DEBUG" |
| 5708 |
#endif // ifdef I386 |
| 5709 |
// PRH_VAR_PTR[2]=&PRH_VAR_DOWNLOAD_HEADER; |
| 5710 |
PRH_VAR_EEPROM_ADDR[2]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_DOWNLOAD_HEADER); |
| 5711 |
#ifdef I386 |
| 5712 |
PRH_VAR_NAME[2]="DOWNLOAD_HEADER" |
| 5713 |
#endif // ifdef I386 |
| 5714 |
// PRH_VAR_PTR[3]=&PRH_VAR_KHB_ALARM_REG_LOW_LEVEL_MASK; |
| 5715 |
PRH_VAR_EEPROM_ADDR[3]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_KHB_ALARM_REG_LOW_LEVEL_MASK); |
| 5716 |
#ifdef I386 |
| 5717 |
PRH_VAR_NAME[3]="KHB_ALARM_REG_LOW_LEVEL_MASK" |
| 5718 |
#endif // ifdef I386 |
| 5719 |
// PRH_VAR_PTR[4]=&PRH_VAR_KHB_STATUS_REG_LOW_LEVEL_MASK; |
| 5720 |
PRH_VAR_EEPROM_ADDR[4]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_KHB_STATUS_REG_LOW_LEVEL_MASK); |
| 5721 |
#ifdef I386 |
| 5722 |
PRH_VAR_NAME[4]="KHB_STATUS_REG_LOW_LEVEL_MASK" |
| 5723 |
#endif // ifdef I386 |
| 5724 |
// PRH_VAR_PTR[5]=&PRH_VAR_PULSER_ACTION; |
| 5725 |
PRH_VAR_EEPROM_ADDR[5]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PULSER_ACTION); |
| 5726 |
#ifdef I386 |
| 5727 |
PRH_VAR_NAME[5]="PULSER_ACTION" |
| 5728 |
#endif // ifdef I386 |
| 5729 |
// PRH_VAR_PTR[6]=&PRH_VAR_N_BOOT; |
| 5730 |
PRH_VAR_EEPROM_ADDR[6]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_N_BOOT); |
| 5731 |
#ifdef I386 |
| 5732 |
PRH_VAR_NAME[6]="N_BOOT" |
| 5733 |
#endif // ifdef I386 |
| 5734 |
// PRH_VAR_PTR[7]=&PRH_VAR_THERMISTORS_CHECK; |
| 5735 |
PRH_VAR_EEPROM_ADDR[7]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_THERMISTORS_CHECK); |
| 5736 |
#ifdef I386 |
| 5737 |
PRH_VAR_NAME[7]="THERMISTORS_CHECK" |
| 5738 |
#endif // ifdef I386 |
| 5739 |
// PRH_VAR_PTR[8]=&PRH_VAR_THERM_MASK; |
| 5740 |
PRH_VAR_EEPROM_ADDR[8]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_THERM_MASK); |
| 5741 |
#ifdef I386 |
| 5742 |
PRH_VAR_NAME[8]="THERM_MASK" |
| 5743 |
#endif // ifdef I386 |
| 5744 |
// PRH_VAR_PTR[9]=&PRH_VAR_IPM_VOLTAGES_CHECK; |
| 5745 |
PRH_VAR_EEPROM_ADDR[9]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_IPM_VOLTAGES_CHECK); |
| 5746 |
#ifdef I386 |
| 5747 |
PRH_VAR_NAME[9]="IPM_VOLTAGES_CHECK" |
| 5748 |
#endif // ifdef I386 |
| 5749 |
// PRH_VAR_PTR[10]=&PRH_VAR_KHB_IDAQ_CHECK; |
| 5750 |
PRH_VAR_EEPROM_ADDR[10]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_KHB_IDAQ_CHECK); |
| 5751 |
#ifdef I386 |
| 5752 |
PRH_VAR_NAME[10]="KHB_IDAQ_CHECK" |
| 5753 |
#endif // ifdef I386 |
| 5754 |
// PRH_VAR_PTR[11]=&PRH_VAR_NTRIG; |
| 5755 |
PRH_VAR_EEPROM_ADDR[11]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_NTRIG); |
| 5756 |
#ifdef I386 |
| 5757 |
PRH_VAR_NAME[11]="NTRIG" |
| 5758 |
#endif // ifdef I386 |
| 5759 |
// PRH_VAR_PTR[12]=&PRH_VAR_TRIG; |
| 5760 |
PRH_VAR_EEPROM_ADDR[12]=PRH_EEPROM_NO_STORED; |
| 5761 |
#ifdef I386 |
| 5762 |
PRH_VAR_NAME[12]="TRIG" |
| 5763 |
#endif // ifdef I386 |
| 5764 |
// PRH_VAR_PTR[13]=&PRH_VAR_CONF_SEL; |
| 5765 |
PRH_VAR_EEPROM_ADDR[13]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CONF_SEL); |
| 5766 |
#ifdef I386 |
| 5767 |
PRH_VAR_NAME[13]="CONF_SEL" |
| 5768 |
#endif // ifdef I386 |
| 5769 |
// PRH_VAR_PTR[14]=&PRH_VAR_CONFOK; |
| 5770 |
PRH_VAR_EEPROM_ADDR[14]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CONFOK); |
| 5771 |
#ifdef I386 |
| 5772 |
PRH_VAR_NAME[14]="CONFOK" |
| 5773 |
#endif // ifdef I386 |
| 5774 |
// PRH_VAR_PTR[15]=&PRH_VAR_OFF; |
| 5775 |
PRH_VAR_EEPROM_ADDR[15]=PRH_EEPROM_NO_STORED; |
| 5776 |
#ifdef I386 |
| 5777 |
PRH_VAR_NAME[15]="OFF" |
| 5778 |
#endif // ifdef I386 |
| 5779 |
// PRH_VAR_PTR[16]=&PRH_VAR_NOFF; |
| 5780 |
PRH_VAR_EEPROM_ADDR[16]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_NOFF); |
| 5781 |
#ifdef I386 |
| 5782 |
PRH_VAR_NAME[16]="NOFF" |
| 5783 |
#endif // ifdef I386 |
| 5784 |
// PRH_VAR_PTR[17]=&PRH_VAR_NRES; |
| 5785 |
PRH_VAR_EEPROM_ADDR[17]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_NRES); |
| 5786 |
#ifdef I386 |
| 5787 |
PRH_VAR_NAME[17]="NRES" |
| 5788 |
#endif // ifdef I386 |
| 5789 |
// PRH_VAR_PTR[18]=&PRH_VAR_RES; |
| 5790 |
PRH_VAR_EEPROM_ADDR[18]=PRH_EEPROM_NO_STORED; |
| 5791 |
#ifdef I386 |
| 5792 |
PRH_VAR_NAME[18]="RES" |
| 5793 |
#endif // ifdef I386 |
| 5794 |
// PRH_VAR_PTR[19]=&PRH_VAR_WATCHDOG_RESET_DISABLE; |
| 5795 |
PRH_VAR_EEPROM_ADDR[19]=PRH_EEPROM_NO_STORED; |
| 5796 |
#ifdef I386 |
| 5797 |
PRH_VAR_NAME[19]="WATCHDOG_RESET_DISABLE" |
| 5798 |
#endif // ifdef I386 |
| 5799 |
// PRH_VAR_PTR[20]=&PRH_VAR_NFAILED_POWER_ON; |
| 5800 |
PRH_VAR_EEPROM_ADDR[20]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_NFAILED_POWER_ON); |
| 5801 |
#ifdef I386 |
| 5802 |
PRH_VAR_NAME[20]="NFAILED_POWER_ON" |
| 5803 |
#endif // ifdef I386 |
| 5804 |
// PRH_VAR_PTR[21]=&PRH_VAR_AUTO_RM_MODE; |
| 5805 |
PRH_VAR_EEPROM_ADDR[21]=PRH_EEPROM_NO_STORED; |
| 5806 |
#ifdef I386 |
| 5807 |
PRH_VAR_NAME[21]="AUTO_RM_MODE" |
| 5808 |
#endif // ifdef I386 |
| 5809 |
// PRH_VAR_PTR[22]=&PRH_VAR_AUTO_SCM_MODE; |
| 5810 |
PRH_VAR_EEPROM_ADDR[22]=PRH_EEPROM_NO_STORED; |
| 5811 |
#ifdef I386 |
| 5812 |
PRH_VAR_NAME[22]="AUTO_SCM_MODE" |
| 5813 |
#endif // ifdef I386 |
| 5814 |
// PRH_VAR_PTR[23]=&PRH_VAR_MASK_ACQ_ALARM; |
| 5815 |
PRH_VAR_EEPROM_ADDR[23]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_MASK_ACQ_ALARM); |
| 5816 |
#ifdef I386 |
| 5817 |
PRH_VAR_NAME[23]="MASK_ACQ_ALARM" |
| 5818 |
#endif // ifdef I386 |
| 5819 |
// PRH_VAR_PTR[24]=&PRH_VAR_GOM_DURING_ALARM; |
| 5820 |
PRH_VAR_EEPROM_ADDR[24]=PRH_EEPROM_NO_STORED; |
| 5821 |
#ifdef I386 |
| 5822 |
PRH_VAR_NAME[24]="GOM_DURING_ALARM" |
| 5823 |
#endif // ifdef I386 |
| 5824 |
// PRH_VAR_PTR[25]=&PRH_VAR_PM_FORCE_RUNNING_TIMEOUT; |
| 5825 |
PRH_VAR_EEPROM_ADDR[25]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PM_FORCE_RUNNING_TIMEOUT); |
| 5826 |
#ifdef I386 |
| 5827 |
PRH_VAR_NAME[25]="PM_FORCE_RUNNING_TIMEOUT" |
| 5828 |
#endif // ifdef I386 |
| 5829 |
// PRH_VAR_PTR[26]=&PRH_VAR_PAMELA_ON; |
| 5830 |
PRH_VAR_EEPROM_ADDR[26]=PRH_EEPROM_NO_STORED; |
| 5831 |
#ifdef I386 |
| 5832 |
PRH_VAR_NAME[26]="PAMELA_ON" |
| 5833 |
#endif // ifdef I386 |
| 5834 |
// PRH_VAR_PTR[27]=&PRH_VAR_N_CALIB; |
| 5835 |
PRH_VAR_EEPROM_ADDR[27]=PRH_EEPROM_NO_STORED; |
| 5836 |
#ifdef I386 |
| 5837 |
PRH_VAR_NAME[27]="N_CALIB" |
| 5838 |
#endif // ifdef I386 |
| 5839 |
// PRH_VAR_PTR[28]=&PRH_VAR_AC_1_ON; |
| 5840 |
PRH_VAR_EEPROM_ADDR[28]=PRH_EEPROM_NO_STORED; |
| 5841 |
#ifdef I386 |
| 5842 |
PRH_VAR_NAME[28]="AC_1_ON" |
| 5843 |
#endif // ifdef I386 |
| 5844 |
// PRH_VAR_PTR[29]=&PRH_VAR_AC_2_ON; |
| 5845 |
PRH_VAR_EEPROM_ADDR[29]=PRH_EEPROM_NO_STORED; |
| 5846 |
#ifdef I386 |
| 5847 |
PRH_VAR_NAME[29]="AC_2_ON" |
| 5848 |
#endif // ifdef I386 |
| 5849 |
// PRH_VAR_PTR[30]=&PRH_VAR_POWER_MODE; |
| 5850 |
PRH_VAR_EEPROM_ADDR[30]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_POWER_MODE); |
| 5851 |
#ifdef I386 |
| 5852 |
PRH_VAR_NAME[30]="POWER_MODE" |
| 5853 |
#endif // ifdef I386 |
| 5854 |
// PRH_VAR_PTR[31]=&PRH_VAR_TRIG_II; |
| 5855 |
PRH_VAR_EEPROM_ADDR[31]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRIG_II); |
| 5856 |
#ifdef I386 |
| 5857 |
PRH_VAR_NAME[31]="TRIG_II" |
| 5858 |
#endif // ifdef I386 |
| 5859 |
// PRH_VAR_PTR[32]=&PRH_VAR_BUF_LEN_TRIG_II_INIT; |
| 5860 |
PRH_VAR_EEPROM_ADDR[32]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRIG_II_INIT); |
| 5861 |
#ifdef I386 |
| 5862 |
PRH_VAR_NAME[32]="BUF_LEN_TRIG_II_INIT" |
| 5863 |
#endif // ifdef I386 |
| 5864 |
// PRH_VAR_PTR[33]=&PRH_VAR_BUF_LEN_TRIG_II_ACQ; |
| 5865 |
PRH_VAR_EEPROM_ADDR[33]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRIG_II_ACQ); |
| 5866 |
#ifdef I386 |
| 5867 |
PRH_VAR_NAME[33]="BUF_LEN_TRIG_II_ACQ" |
| 5868 |
#endif // ifdef I386 |
| 5869 |
// PRH_VAR_PTR[34]=&PRH_VAR_EXP64_MODE; |
| 5870 |
PRH_VAR_EEPROM_ADDR[34]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_EXP64_MODE); |
| 5871 |
#ifdef I386 |
| 5872 |
PRH_VAR_NAME[34]="EXP64_MODE" |
| 5873 |
#endif // ifdef I386 |
| 5874 |
// PRH_VAR_PTR[35]=&PRH_VAR_EXP64_MODE_DELAY; |
| 5875 |
PRH_VAR_EEPROM_ADDR[35]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_EXP64_MODE_DELAY); |
| 5876 |
#ifdef I386 |
| 5877 |
PRH_VAR_NAME[35]="EXP64_MODE_DELAY" |
| 5878 |
#endif // ifdef I386 |
| 5879 |
// PRH_VAR_PTR[36]=&PRH_VAR_MH_END_OF_DOWNLOAD_TIMEOUT; |
| 5880 |
PRH_VAR_EEPROM_ADDR[36]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_MH_END_OF_DOWNLOAD_TIMEOUT); |
| 5881 |
#ifdef I386 |
| 5882 |
PRH_VAR_NAME[36]="MH_END_OF_DOWNLOAD_TIMEOUT" |
| 5883 |
#endif // ifdef I386 |
| 5884 |
// PRH_VAR_PTR[37]=&PRH_VAR_PM_STOP_RUNMANAGER_TIMEOUT; |
| 5885 |
PRH_VAR_EEPROM_ADDR[37]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PM_STOP_RUNMANAGER_TIMEOUT); |
| 5886 |
#ifdef I386 |
| 5887 |
PRH_VAR_NAME[37]="PM_STOP_RUNMANAGER_TIMEOUT" |
| 5888 |
#endif // ifdef I386 |
| 5889 |
// PRH_VAR_PTR[38]=&PRH_VAR_PM_STOP_RUNMANAGER_TIMES_RETRY; |
| 5890 |
PRH_VAR_EEPROM_ADDR[38]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PM_STOP_RUNMANAGER_TIMES_RETRY); |
| 5891 |
#ifdef I386 |
| 5892 |
PRH_VAR_NAME[38]="PM_STOP_RUNMANAGER_TIMES_RETRY" |
| 5893 |
#endif // ifdef I386 |
| 5894 |
// PRH_VAR_PTR[39]=&PRH_VAR_PM_N_ORBIT_CALIB; |
| 5895 |
PRH_VAR_EEPROM_ADDR[39]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PM_N_ORBIT_CALIB); |
| 5896 |
#ifdef I386 |
| 5897 |
PRH_VAR_NAME[39]="PM_N_ORBIT_CALIB" |
| 5898 |
#endif // ifdef I386 |
| 5899 |
// PRH_VAR_PTR[40]=&PRH_VAR_WS_TIME_ORBIT; |
| 5900 |
PRH_VAR_EEPROM_ADDR[40]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_WS_TIME_ORBIT); |
| 5901 |
#ifdef I386 |
| 5902 |
PRH_VAR_NAME[40]="WS_TIME_ORBIT" |
| 5903 |
#endif // ifdef I386 |
| 5904 |
// PRH_VAR_PTR[41]=&PRH_VAR_WS_FAVOURITE_WS; |
| 5905 |
PRH_VAR_EEPROM_ADDR[41]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_WS_FAVOURITE_WS); |
| 5906 |
#ifdef I386 |
| 5907 |
PRH_VAR_NAME[41]="WS_FAVOURITE_WS" |
| 5908 |
#endif // ifdef I386 |
| 5909 |
// PRH_VAR_PTR[42]=&PRH_VAR_RM_N_TRIES_PREPARE_PAGE; |
| 5910 |
PRH_VAR_EEPROM_ADDR[42]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_N_TRIES_PREPARE_PAGE); |
| 5911 |
#ifdef I386 |
| 5912 |
PRH_VAR_NAME[42]="RM_N_TRIES_PREPARE_PAGE" |
| 5913 |
#endif // ifdef I386 |
| 5914 |
// PRH_VAR_PTR[43]=&PRH_VAR_RM_TRIES_PREPARE_PAGE_SLEEP; |
| 5915 |
PRH_VAR_EEPROM_ADDR[43]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_TRIES_PREPARE_PAGE_SLEEP); |
| 5916 |
#ifdef I386 |
| 5917 |
PRH_VAR_NAME[43]="RM_TRIES_PREPARE_PAGE_SLEEP" |
| 5918 |
#endif // ifdef I386 |
| 5919 |
// PRH_VAR_PTR[44]=&PRH_VAR_RM_WS3_TIMER_FIRE_AFTER; |
| 5920 |
PRH_VAR_EEPROM_ADDR[44]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_WS3_TIMER_FIRE_AFTER); |
| 5921 |
#ifdef I386 |
| 5922 |
PRH_VAR_NAME[44]="RM_WS3_TIMER_FIRE_AFTER" |
| 5923 |
#endif // ifdef I386 |
| 5924 |
// PRH_VAR_PTR[45]=&PRH_VAR_RM_TIME_MAX_RUN; |
| 5925 |
PRH_VAR_EEPROM_ADDR[45]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_TIME_MAX_RUN); |
| 5926 |
#ifdef I386 |
| 5927 |
PRH_VAR_NAME[45]="RM_TIME_MAX_RUN" |
| 5928 |
#endif // ifdef I386 |
| 5929 |
// PRH_VAR_PTR[46]=&PRH_VAR_RM_TIME_SPECIAL_RUN; |
| 5930 |
PRH_VAR_EEPROM_ADDR[46]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_TIME_SPECIAL_RUN); |
| 5931 |
#ifdef I386 |
| 5932 |
PRH_VAR_NAME[46]="RM_TIME_SPECIAL_RUN" |
| 5933 |
#endif // ifdef I386 |
| 5934 |
// PRH_VAR_PTR[47]=&PRH_VAR_RM_ACQCHECK_PERIOD; |
| 5935 |
PRH_VAR_EEPROM_ADDR[47]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_ACQCHECK_PERIOD); |
| 5936 |
#ifdef I386 |
| 5937 |
PRH_VAR_NAME[47]="RM_ACQCHECK_PERIOD" |
| 5938 |
#endif // ifdef I386 |
| 5939 |
// PRH_VAR_PTR[48]=&PRH_VAR_RM_FLUSH_TIMEOUT; |
| 5940 |
PRH_VAR_EEPROM_ADDR[48]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_FLUSH_TIMEOUT); |
| 5941 |
#ifdef I386 |
| 5942 |
PRH_VAR_NAME[48]="RM_FLUSH_TIMEOUT" |
| 5943 |
#endif // ifdef I386 |
| 5944 |
// PRH_VAR_PTR[49]=&PRH_VAR_RM_NO_FLUSH_PARAM_DUMP; |
| 5945 |
PRH_VAR_EEPROM_ADDR[49]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_NO_FLUSH_PARAM_DUMP); |
| 5946 |
#ifdef I386 |
| 5947 |
PRH_VAR_NAME[49]="RM_NO_FLUSH_PARAM_DUMP" |
| 5948 |
#endif // ifdef I386 |
| 5949 |
// PRH_VAR_PTR[50]=&PRH_VAR_RM_DUMP_ALL_PARAMS; |
| 5950 |
PRH_VAR_EEPROM_ADDR[50]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_DUMP_ALL_PARAMS); |
| 5951 |
#ifdef I386 |
| 5952 |
PRH_VAR_NAME[50]="RM_DUMP_ALL_PARAMS" |
| 5953 |
#endif // ifdef I386 |
| 5954 |
// PRH_VAR_PTR[51]=&PRH_VAR_RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ; |
| 5955 |
PRH_VAR_EEPROM_ADDR[51]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ); |
| 5956 |
#ifdef I386 |
| 5957 |
PRH_VAR_NAME[51]="RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ" |
| 5958 |
#endif // ifdef I386 |
| 5959 |
// PRH_VAR_PTR[52]=&PRH_VAR_PWR_WAIT_BEFORE_SENDTC; |
| 5960 |
PRH_VAR_EEPROM_ADDR[52]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_WAIT_BEFORE_SENDTC); |
| 5961 |
#ifdef I386 |
| 5962 |
PRH_VAR_NAME[52]="PWR_WAIT_BEFORE_SENDTC" |
| 5963 |
#endif // ifdef I386 |
| 5964 |
// PRH_VAR_PTR[53]=&PRH_VAR_PWR_CMD2PSB_DELAY; |
| 5965 |
PRH_VAR_EEPROM_ADDR[53]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_CMD2PSB_DELAY); |
| 5966 |
#ifdef I386 |
| 5967 |
PRH_VAR_NAME[53]="PWR_CMD2PSB_DELAY" |
| 5968 |
#endif // ifdef I386 |
| 5969 |
// PRH_VAR_PTR[54]=&PRH_VAR_PWR_TRB_READ_ATTEMPTS; |
| 5970 |
PRH_VAR_EEPROM_ADDR[54]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_TRB_READ_ATTEMPTS); |
| 5971 |
#ifdef I386 |
| 5972 |
PRH_VAR_NAME[54]="PWR_TRB_READ_ATTEMPTS" |
| 5973 |
#endif // ifdef I386 |
| 5974 |
// PRH_VAR_PTR[55]=&PRH_VAR_PWR_KHB_INITBOARD_TWICE_DELAY; |
| 5975 |
PRH_VAR_EEPROM_ADDR[55]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_KHB_INITBOARD_TWICE_DELAY); |
| 5976 |
#ifdef I386 |
| 5977 |
PRH_VAR_NAME[55]="PWR_KHB_INITBOARD_TWICE_DELAY" |
| 5978 |
#endif // ifdef I386 |
| 5979 |
// PRH_VAR_PTR[56]=&PRH_VAR_PWR_IPM_WAIT_OK_N_ATTEMPT; |
| 5980 |
PRH_VAR_EEPROM_ADDR[56]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_IPM_WAIT_OK_N_ATTEMPT); |
| 5981 |
#ifdef I386 |
| 5982 |
PRH_VAR_NAME[56]="PWR_IPM_WAIT_OK_N_ATTEMPT" |
| 5983 |
#endif // ifdef I386 |
| 5984 |
// PRH_VAR_PTR[57]=&PRH_VAR_PWR_IPM_WAIT_OK_DELAY_ATTEMPT; |
| 5985 |
PRH_VAR_EEPROM_ADDR[57]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_IPM_WAIT_OK_DELAY_ATTEMPT); |
| 5986 |
#ifdef I386 |
| 5987 |
PRH_VAR_NAME[57]="PWR_IPM_WAIT_OK_DELAY_ATTEMPT" |
| 5988 |
#endif // ifdef I386 |
| 5989 |
// PRH_VAR_PTR[58]=&PRH_VAR_PWR_VOLTAGE_N_ATTEMPT; |
| 5990 |
PRH_VAR_EEPROM_ADDR[58]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_VOLTAGE_N_ATTEMPT); |
| 5991 |
#ifdef I386 |
| 5992 |
PRH_VAR_NAME[58]="PWR_VOLTAGE_N_ATTEMPT" |
| 5993 |
#endif // ifdef I386 |
| 5994 |
// PRH_VAR_PTR[59]=&PRH_VAR_PWR_VOLTAGE_DELAY_ATTEMPT; |
| 5995 |
PRH_VAR_EEPROM_ADDR[59]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_VOLTAGE_DELAY_ATTEMPT); |
| 5996 |
#ifdef I386 |
| 5997 |
PRH_VAR_NAME[59]="PWR_VOLTAGE_DELAY_ATTEMPT" |
| 5998 |
#endif // ifdef I386 |
| 5999 |
// PRH_VAR_PTR[60]=&PRH_VAR_PWR_TRB1_SET; |
| 6000 |
PRH_VAR_EEPROM_ADDR[60]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_TRB1_SET); |
| 6001 |
#ifdef I386 |
| 6002 |
PRH_VAR_NAME[60]="PWR_TRB1_SET" |
| 6003 |
#endif // ifdef I386 |
| 6004 |
// PRH_VAR_PTR[61]=&PRH_VAR_PWR_TRB2_SET; |
| 6005 |
PRH_VAR_EEPROM_ADDR[61]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_TRB2_SET); |
| 6006 |
#ifdef I386 |
| 6007 |
PRH_VAR_NAME[61]="PWR_TRB2_SET" |
| 6008 |
#endif // ifdef I386 |
| 6009 |
// PRH_VAR_PTR[62]=&PRH_VAR_PWR_TRB_SET_DELAY; |
| 6010 |
PRH_VAR_EEPROM_ADDR[62]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_TRB_SET_DELAY); |
| 6011 |
#ifdef I386 |
| 6012 |
PRH_VAR_NAME[62]="PWR_TRB_SET_DELAY" |
| 6013 |
#endif // ifdef I386 |
| 6014 |
// PRH_VAR_PTR[63]=&PRH_VAR_PWR_TRB_READ_DELAY; |
| 6015 |
PRH_VAR_EEPROM_ADDR[63]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PWR_TRB_READ_DELAY); |
| 6016 |
#ifdef I386 |
| 6017 |
PRH_VAR_NAME[63]="PWR_TRB_READ_DELAY" |
| 6018 |
#endif // ifdef I386 |
| 6019 |
// PRH_VAR_PTR[64]=&PRH_VAR_HB_N_ATTEMPT_WRITE2PIF; |
| 6020 |
PRH_VAR_EEPROM_ADDR[64]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_HB_N_ATTEMPT_WRITE2PIF); |
| 6021 |
#ifdef I386 |
| 6022 |
PRH_VAR_NAME[64]="HB_N_ATTEMPT_WRITE2PIF" |
| 6023 |
#endif // ifdef I386 |
| 6024 |
// PRH_VAR_PTR[65]=&PRH_VAR_HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF; |
| 6025 |
PRH_VAR_EEPROM_ADDR[65]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF); |
| 6026 |
#ifdef I386 |
| 6027 |
PRH_VAR_NAME[65]="HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF" |
| 6028 |
#endif // ifdef I386 |
| 6029 |
// PRH_VAR_PTR[66]=&PRH_VAR_HB_WRITE2PIF_TIMEOUT; |
| 6030 |
PRH_VAR_EEPROM_ADDR[66]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_HB_WRITE2PIF_TIMEOUT); |
| 6031 |
#ifdef I386 |
| 6032 |
PRH_VAR_NAME[66]="HB_WRITE2PIF_TIMEOUT" |
| 6033 |
#endif // ifdef I386 |
| 6034 |
// PRH_VAR_PTR[67]=&PRH_VAR_HB_ALMOST_FULL; |
| 6035 |
PRH_VAR_EEPROM_ADDR[67]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_HB_ALMOST_FULL); |
| 6036 |
#ifdef I386 |
| 6037 |
PRH_VAR_NAME[67]="HB_ALMOST_FULL" |
| 6038 |
#endif // ifdef I386 |
| 6039 |
// PRH_VAR_PTR[68]=&PRH_VAR_TM_VRL_SUSPEND_HCL; |
| 6040 |
PRH_VAR_EEPROM_ADDR[68]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TM_VRL_SUSPEND_HCL); |
| 6041 |
#ifdef I386 |
| 6042 |
PRH_VAR_NAME[68]="TM_VRL_SUSPEND_HCL" |
| 6043 |
#endif // ifdef I386 |
| 6044 |
// PRH_VAR_PTR[69]=&PRH_VAR_TM_VRL_SUSPEND_BEFORE_START; |
| 6045 |
PRH_VAR_EEPROM_ADDR[69]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TM_VRL_SUSPEND_BEFORE_START); |
| 6046 |
#ifdef I386 |
| 6047 |
PRH_VAR_NAME[69]="TM_VRL_SUSPEND_BEFORE_START" |
| 6048 |
#endif // ifdef I386 |
| 6049 |
// PRH_VAR_PTR[70]=&PRH_VAR_DAQ_EVENT_RECEIVE_TIMEOUT; |
| 6050 |
PRH_VAR_EEPROM_ADDR[70]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_DAQ_EVENT_RECEIVE_TIMEOUT); |
| 6051 |
#ifdef I386 |
| 6052 |
PRH_VAR_NAME[70]="DAQ_EVENT_RECEIVE_TIMEOUT" |
| 6053 |
#endif // ifdef I386 |
| 6054 |
// PRH_VAR_PTR[71]=&PRH_VAR_DAQ_WAITFREECMDIF_N; |
| 6055 |
PRH_VAR_EEPROM_ADDR[71]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_DAQ_WAITFREECMDIF_N); |
| 6056 |
#ifdef I386 |
| 6057 |
PRH_VAR_NAME[71]="DAQ_WAITFREECMDIF_N" |
| 6058 |
#endif // ifdef I386 |
| 6059 |
// PRH_VAR_PTR[72]=&PRH_VAR_TRB_OK; |
| 6060 |
PRH_VAR_EEPROM_ADDR[72]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRB_OK); |
| 6061 |
#ifdef I386 |
| 6062 |
PRH_VAR_NAME[72]="TRB_OK" |
| 6063 |
#endif // ifdef I386 |
| 6064 |
// PRH_VAR_PTR[73]=&PRH_VAR_TRIGGER_MODE_A; |
| 6065 |
PRH_VAR_EEPROM_ADDR[73]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRIGGER_MODE_A); |
| 6066 |
#ifdef I386 |
| 6067 |
PRH_VAR_NAME[73]="TRIGGER_MODE_A" |
| 6068 |
#endif // ifdef I386 |
| 6069 |
// PRH_VAR_PTR[74]=&PRH_VAR_TRIGGER_MODE_B; |
| 6070 |
PRH_VAR_EEPROM_ADDR[74]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRIGGER_MODE_B); |
| 6071 |
#ifdef I386 |
| 6072 |
PRH_VAR_NAME[74]="TRIGGER_MODE_B" |
| 6073 |
#endif // ifdef I386 |
| 6074 |
// PRH_VAR_PTR[75]=&PRH_VAR_TRIGGER_BUSY_CONTROL; |
| 6075 |
PRH_VAR_EEPROM_ADDR[75]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRIGGER_BUSY_CONTROL); |
| 6076 |
#ifdef I386 |
| 6077 |
PRH_VAR_NAME[75]="TRIGGER_BUSY_CONTROL" |
| 6078 |
#endif // ifdef I386 |
| 6079 |
// PRH_VAR_PTR[76]=&PRH_VAR_TB_LINK; |
| 6080 |
PRH_VAR_EEPROM_ADDR[76]=PRH_EEPROM_NO_STORED; |
| 6081 |
#ifdef I386 |
| 6082 |
PRH_VAR_NAME[76]="TB_LINK" |
| 6083 |
#endif // ifdef I386 |
| 6084 |
// PRH_VAR_PTR[77]=&PRH_VAR_TB_LINK_CUSTOM; |
| 6085 |
PRH_VAR_EEPROM_ADDR[77]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TB_LINK_CUSTOM); |
| 6086 |
#ifdef I386 |
| 6087 |
PRH_VAR_NAME[77]="TB_LINK_CUSTOM" |
| 6088 |
#endif // ifdef I386 |
| 6089 |
// PRH_VAR_PTR[78]=&PRH_VAR_BUF_LEN_TB_SET_ALARM_MASK; |
| 6090 |
PRH_VAR_EEPROM_ADDR[78]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TB_SET_ALARM_MASK); |
| 6091 |
#ifdef I386 |
| 6092 |
PRH_VAR_NAME[78]="BUF_LEN_TB_SET_ALARM_MASK" |
| 6093 |
#endif // ifdef I386 |
| 6094 |
// PRH_VAR_PTR[79]=&PRH_VAR_BUF_LEN_TB_SET_PMT_MASK; |
| 6095 |
PRH_VAR_EEPROM_ADDR[79]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TB_SET_PMT_MASK); |
| 6096 |
#ifdef I386 |
| 6097 |
PRH_VAR_NAME[79]="BUF_LEN_TB_SET_PMT_MASK" |
| 6098 |
#endif // ifdef I386 |
| 6099 |
// PRH_VAR_PTR[80]=&PRH_VAR_BUF_LEN_TB_SET_S4_CAL_MASK; |
| 6100 |
PRH_VAR_EEPROM_ADDR[80]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TB_SET_S4_CAL_MASK); |
| 6101 |
#ifdef I386 |
| 6102 |
PRH_VAR_NAME[80]="BUF_LEN_TB_SET_S4_CAL_MASK" |
| 6103 |
#endif // ifdef I386 |
| 6104 |
// PRH_VAR_PTR[81]=&PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT; |
| 6105 |
PRH_VAR_EEPROM_ADDR[81]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT); |
| 6106 |
#ifdef I386 |
| 6107 |
PRH_VAR_NAME[81]="BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT" |
| 6108 |
#endif // ifdef I386 |
| 6109 |
// PRH_VAR_PTR[82]=&PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD; |
| 6110 |
PRH_VAR_EEPROM_ADDR[82]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD); |
| 6111 |
#ifdef I386 |
| 6112 |
PRH_VAR_NAME[82]="BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD" |
| 6113 |
#endif // ifdef I386 |
| 6114 |
// PRH_VAR_PTR[83]=&PRH_VAR_TRK_OK; |
| 6115 |
PRH_VAR_EEPROM_ADDR[83]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRK_OK); |
| 6116 |
#ifdef I386 |
| 6117 |
PRH_VAR_NAME[83]="TRK_OK" |
| 6118 |
#endif // ifdef I386 |
| 6119 |
// PRH_VAR_PTR[84]=&PRH_VAR_TRK_CALIB_MODE; |
| 6120 |
PRH_VAR_EEPROM_ADDR[84]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRK_CALIB_MODE); |
| 6121 |
#ifdef I386 |
| 6122 |
PRH_VAR_NAME[84]="TRK_CALIB_MODE" |
| 6123 |
#endif // ifdef I386 |
| 6124 |
// PRH_VAR_PTR[85]=&PRH_VAR_TRK_TIME_SHORT; |
| 6125 |
PRH_VAR_EEPROM_ADDR[85]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRK_TIME_SHORT); |
| 6126 |
#ifdef I386 |
| 6127 |
PRH_VAR_NAME[85]="TRK_TIME_SHORT" |
| 6128 |
#endif // ifdef I386 |
| 6129 |
// PRH_VAR_PTR[86]=&PRH_VAR_TRK_TIME_LONG; |
| 6130 |
PRH_VAR_EEPROM_ADDR[86]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRK_TIME_LONG); |
| 6131 |
#ifdef I386 |
| 6132 |
PRH_VAR_NAME[86]="TRK_TIME_LONG" |
| 6133 |
#endif // ifdef I386 |
| 6134 |
// PRH_VAR_PTR[87]=&PRH_VAR_TRK_CALIB_INIT; |
| 6135 |
PRH_VAR_EEPROM_ADDR[87]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRK_CALIB_INIT); |
| 6136 |
#ifdef I386 |
| 6137 |
PRH_VAR_NAME[87]="TRK_CALIB_INIT" |
| 6138 |
#endif // ifdef I386 |
| 6139 |
// PRH_VAR_PTR[88]=&PRH_VAR_TRK_NLOOP; |
| 6140 |
PRH_VAR_EEPROM_ADDR[88]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TRK_NLOOP); |
| 6141 |
#ifdef I386 |
| 6142 |
PRH_VAR_NAME[88]="TRK_NLOOP" |
| 6143 |
#endif // ifdef I386 |
| 6144 |
// PRH_VAR_PTR[89]=&PRH_VAR_BUF_LEN_TRK_PROGRAM; |
| 6145 |
PRH_VAR_EEPROM_ADDR[89]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_PROGRAM); |
| 6146 |
#ifdef I386 |
| 6147 |
PRH_VAR_NAME[89]="BUF_LEN_TRK_PROGRAM" |
| 6148 |
#endif // ifdef I386 |
| 6149 |
// PRH_VAR_PTR[90]=&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_0; |
| 6150 |
PRH_VAR_EEPROM_ADDR[90]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_0); |
| 6151 |
#ifdef I386 |
| 6152 |
PRH_VAR_NAME[90]="BUF_LEN_TRK_TRAILER_PRG_0" |
| 6153 |
#endif // ifdef I386 |
| 6154 |
// PRH_VAR_PTR[91]=&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_1; |
| 6155 |
PRH_VAR_EEPROM_ADDR[91]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_1); |
| 6156 |
#ifdef I386 |
| 6157 |
PRH_VAR_NAME[91]="BUF_LEN_TRK_TRAILER_PRG_1" |
| 6158 |
#endif // ifdef I386 |
| 6159 |
// PRH_VAR_PTR[92]=&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_2; |
| 6160 |
PRH_VAR_EEPROM_ADDR[92]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_2); |
| 6161 |
#ifdef I386 |
| 6162 |
PRH_VAR_NAME[92]="BUF_LEN_TRK_TRAILER_PRG_2" |
| 6163 |
#endif // ifdef I386 |
| 6164 |
// PRH_VAR_PTR[93]=&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_3; |
| 6165 |
PRH_VAR_EEPROM_ADDR[93]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_3); |
| 6166 |
#ifdef I386 |
| 6167 |
PRH_VAR_NAME[93]="BUF_LEN_TRK_TRAILER_PRG_3" |
| 6168 |
#endif // ifdef I386 |
| 6169 |
// PRH_VAR_PTR[94]=&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_4; |
| 6170 |
PRH_VAR_EEPROM_ADDR[94]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_4); |
| 6171 |
#ifdef I386 |
| 6172 |
PRH_VAR_NAME[94]="BUF_LEN_TRK_TRAILER_PRG_4" |
| 6173 |
#endif // ifdef I386 |
| 6174 |
// PRH_VAR_PTR[95]=&PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_5; |
| 6175 |
PRH_VAR_EEPROM_ADDR[95]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_TRAILER_PRG_5); |
| 6176 |
#ifdef I386 |
| 6177 |
PRH_VAR_NAME[95]="BUF_LEN_TRK_TRAILER_PRG_5" |
| 6178 |
#endif // ifdef I386 |
| 6179 |
// PRH_VAR_PTR[96]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_0; |
| 6180 |
PRH_VAR_EEPROM_ADDR[96]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_0); |
| 6181 |
#ifdef I386 |
| 6182 |
PRH_VAR_NAME[96]="BUF_LEN_TRK_NUMBER_DSP_1_0" |
| 6183 |
#endif // ifdef I386 |
| 6184 |
// PRH_VAR_PTR[97]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_1; |
| 6185 |
PRH_VAR_EEPROM_ADDR[97]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_1); |
| 6186 |
#ifdef I386 |
| 6187 |
PRH_VAR_NAME[97]="BUF_LEN_TRK_NUMBER_DSP_1_1" |
| 6188 |
#endif // ifdef I386 |
| 6189 |
// PRH_VAR_PTR[98]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_2; |
| 6190 |
PRH_VAR_EEPROM_ADDR[98]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_2); |
| 6191 |
#ifdef I386 |
| 6192 |
PRH_VAR_NAME[98]="BUF_LEN_TRK_NUMBER_DSP_1_2" |
| 6193 |
#endif // ifdef I386 |
| 6194 |
// PRH_VAR_PTR[99]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_3; |
| 6195 |
PRH_VAR_EEPROM_ADDR[99]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_3); |
| 6196 |
#ifdef I386 |
| 6197 |
PRH_VAR_NAME[99]="BUF_LEN_TRK_NUMBER_DSP_1_3" |
| 6198 |
#endif // ifdef I386 |
| 6199 |
// PRH_VAR_PTR[100]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_4; |
| 6200 |
PRH_VAR_EEPROM_ADDR[100]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_4); |
| 6201 |
#ifdef I386 |
| 6202 |
PRH_VAR_NAME[100]="BUF_LEN_TRK_NUMBER_DSP_1_4" |
| 6203 |
#endif // ifdef I386 |
| 6204 |
// PRH_VAR_PTR[101]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_5; |
| 6205 |
PRH_VAR_EEPROM_ADDR[101]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_1_5); |
| 6206 |
#ifdef I386 |
| 6207 |
PRH_VAR_NAME[101]="BUF_LEN_TRK_NUMBER_DSP_1_5" |
| 6208 |
#endif // ifdef I386 |
| 6209 |
// PRH_VAR_PTR[102]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_0; |
| 6210 |
PRH_VAR_EEPROM_ADDR[102]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_0); |
| 6211 |
#ifdef I386 |
| 6212 |
PRH_VAR_NAME[102]="BUF_LEN_TRK_NUMBER_DSP_2_0" |
| 6213 |
#endif // ifdef I386 |
| 6214 |
// PRH_VAR_PTR[103]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_1; |
| 6215 |
PRH_VAR_EEPROM_ADDR[103]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_1); |
| 6216 |
#ifdef I386 |
| 6217 |
PRH_VAR_NAME[103]="BUF_LEN_TRK_NUMBER_DSP_2_1" |
| 6218 |
#endif // ifdef I386 |
| 6219 |
// PRH_VAR_PTR[104]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_2; |
| 6220 |
PRH_VAR_EEPROM_ADDR[104]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_2); |
| 6221 |
#ifdef I386 |
| 6222 |
PRH_VAR_NAME[104]="BUF_LEN_TRK_NUMBER_DSP_2_2" |
| 6223 |
#endif // ifdef I386 |
| 6224 |
// PRH_VAR_PTR[105]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_3; |
| 6225 |
PRH_VAR_EEPROM_ADDR[105]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_3); |
| 6226 |
#ifdef I386 |
| 6227 |
PRH_VAR_NAME[105]="BUF_LEN_TRK_NUMBER_DSP_2_3" |
| 6228 |
#endif // ifdef I386 |
| 6229 |
// PRH_VAR_PTR[106]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_4; |
| 6230 |
PRH_VAR_EEPROM_ADDR[106]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_4); |
| 6231 |
#ifdef I386 |
| 6232 |
PRH_VAR_NAME[106]="BUF_LEN_TRK_NUMBER_DSP_2_4" |
| 6233 |
#endif // ifdef I386 |
| 6234 |
// PRH_VAR_PTR[107]=&PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_5; |
| 6235 |
PRH_VAR_EEPROM_ADDR[107]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_NUMBER_DSP_2_5); |
| 6236 |
#ifdef I386 |
| 6237 |
PRH_VAR_NAME[107]="BUF_LEN_TRK_NUMBER_DSP_2_5" |
| 6238 |
#endif // ifdef I386 |
| 6239 |
// PRH_VAR_PTR[108]=&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_0; |
| 6240 |
PRH_VAR_EEPROM_ADDR[108]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_0); |
| 6241 |
#ifdef I386 |
| 6242 |
PRH_VAR_NAME[108]="BUF_LEN_TRK_OPMODE_COMP_0" |
| 6243 |
#endif // ifdef I386 |
| 6244 |
// PRH_VAR_PTR[109]=&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_0; |
| 6245 |
PRH_VAR_EEPROM_ADDR[109]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_0); |
| 6246 |
#ifdef I386 |
| 6247 |
PRH_VAR_NAME[109]="BUF_LEN_TRK_OPMODE_SPEC_0" |
| 6248 |
#endif // ifdef I386 |
| 6249 |
// PRH_VAR_PTR[110]=&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_1; |
| 6250 |
PRH_VAR_EEPROM_ADDR[110]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_1); |
| 6251 |
#ifdef I386 |
| 6252 |
PRH_VAR_NAME[110]="BUF_LEN_TRK_OPMODE_COMP_1" |
| 6253 |
#endif // ifdef I386 |
| 6254 |
// PRH_VAR_PTR[111]=&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_1; |
| 6255 |
PRH_VAR_EEPROM_ADDR[111]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_1); |
| 6256 |
#ifdef I386 |
| 6257 |
PRH_VAR_NAME[111]="BUF_LEN_TRK_OPMODE_SPEC_1" |
| 6258 |
#endif // ifdef I386 |
| 6259 |
// PRH_VAR_PTR[112]=&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_2; |
| 6260 |
PRH_VAR_EEPROM_ADDR[112]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_2); |
| 6261 |
#ifdef I386 |
| 6262 |
PRH_VAR_NAME[112]="BUF_LEN_TRK_OPMODE_COMP_2" |
| 6263 |
#endif // ifdef I386 |
| 6264 |
// PRH_VAR_PTR[113]=&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_2; |
| 6265 |
PRH_VAR_EEPROM_ADDR[113]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_2); |
| 6266 |
#ifdef I386 |
| 6267 |
PRH_VAR_NAME[113]="BUF_LEN_TRK_OPMODE_SPEC_2" |
| 6268 |
#endif // ifdef I386 |
| 6269 |
// PRH_VAR_PTR[114]=&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_3; |
| 6270 |
PRH_VAR_EEPROM_ADDR[114]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_3); |
| 6271 |
#ifdef I386 |
| 6272 |
PRH_VAR_NAME[114]="BUF_LEN_TRK_OPMODE_COMP_3" |
| 6273 |
#endif // ifdef I386 |
| 6274 |
// PRH_VAR_PTR[115]=&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_3; |
| 6275 |
PRH_VAR_EEPROM_ADDR[115]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_3); |
| 6276 |
#ifdef I386 |
| 6277 |
PRH_VAR_NAME[115]="BUF_LEN_TRK_OPMODE_SPEC_3" |
| 6278 |
#endif // ifdef I386 |
| 6279 |
// PRH_VAR_PTR[116]=&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_4; |
| 6280 |
PRH_VAR_EEPROM_ADDR[116]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_4); |
| 6281 |
#ifdef I386 |
| 6282 |
PRH_VAR_NAME[116]="BUF_LEN_TRK_OPMODE_COMP_4" |
| 6283 |
#endif // ifdef I386 |
| 6284 |
// PRH_VAR_PTR[117]=&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_4; |
| 6285 |
PRH_VAR_EEPROM_ADDR[117]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_4); |
| 6286 |
#ifdef I386 |
| 6287 |
PRH_VAR_NAME[117]="BUF_LEN_TRK_OPMODE_SPEC_4" |
| 6288 |
#endif // ifdef I386 |
| 6289 |
// PRH_VAR_PTR[118]=&PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_5; |
| 6290 |
PRH_VAR_EEPROM_ADDR[118]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_COMP_5); |
| 6291 |
#ifdef I386 |
| 6292 |
PRH_VAR_NAME[118]="BUF_LEN_TRK_OPMODE_COMP_5" |
| 6293 |
#endif // ifdef I386 |
| 6294 |
// PRH_VAR_PTR[119]=&PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_5; |
| 6295 |
PRH_VAR_EEPROM_ADDR[119]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TRK_OPMODE_SPEC_5); |
| 6296 |
#ifdef I386 |
| 6297 |
PRH_VAR_NAME[119]="BUF_LEN_TRK_OPMODE_SPEC_5" |
| 6298 |
#endif // ifdef I386 |
| 6299 |
// PRH_VAR_PTR[120]=&PRH_VAR_S4_OK; |
| 6300 |
PRH_VAR_EEPROM_ADDR[120]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_S4_OK); |
| 6301 |
#ifdef I386 |
| 6302 |
PRH_VAR_NAME[120]="S4_OK" |
| 6303 |
#endif // ifdef I386 |
| 6304 |
// PRH_VAR_PTR[121]=&PRH_VAR_S4_TRH; |
| 6305 |
PRH_VAR_EEPROM_ADDR[121]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_S4_TRH); |
| 6306 |
#ifdef I386 |
| 6307 |
PRH_VAR_NAME[121]="S4_TRH" |
| 6308 |
#endif // ifdef I386 |
| 6309 |
// PRH_VAR_PTR[122]=&PRH_VAR_S4_ATTEMPT; |
| 6310 |
PRH_VAR_EEPROM_ADDR[122]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_S4_ATTEMPT); |
| 6311 |
#ifdef I386 |
| 6312 |
PRH_VAR_NAME[122]="S4_ATTEMPT" |
| 6313 |
#endif // ifdef I386 |
| 6314 |
// PRH_VAR_PTR[123]=&PRH_VAR_S4_WORKING; |
| 6315 |
PRH_VAR_EEPROM_ADDR[123]=PRH_EEPROM_NO_STORED; |
| 6316 |
#ifdef I386 |
| 6317 |
PRH_VAR_NAME[123]="S4_WORKING" |
| 6318 |
#endif // ifdef I386 |
| 6319 |
// PRH_VAR_PTR[124]=&PRH_VAR_CAL_UPLOAD_CAL_FE_MASK; |
| 6320 |
PRH_VAR_EEPROM_ADDR[124]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CAL_UPLOAD_CAL_FE_MASK); |
| 6321 |
#ifdef I386 |
| 6322 |
PRH_VAR_NAME[124]="CAL_UPLOAD_CAL_FE_MASK" |
| 6323 |
#endif // ifdef I386 |
| 6324 |
// PRH_VAR_PTR[125]=&PRH_VAR_CAL_UPLOAD_CAL_DSP_MASK; |
| 6325 |
PRH_VAR_EEPROM_ADDR[125]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CAL_UPLOAD_CAL_DSP_MASK); |
| 6326 |
#ifdef I386 |
| 6327 |
PRH_VAR_NAME[125]="CAL_UPLOAD_CAL_DSP_MASK" |
| 6328 |
#endif // ifdef I386 |
| 6329 |
// PRH_VAR_PTR[126]=&PRH_VAR_CAL_VCAL; |
| 6330 |
PRH_VAR_EEPROM_ADDR[126]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CAL_VCAL); |
| 6331 |
#ifdef I386 |
| 6332 |
PRH_VAR_NAME[126]="CAL_VCAL" |
| 6333 |
#endif // ifdef I386 |
| 6334 |
// PRH_VAR_PTR[127]=&PRH_VAR_CAL_CH; |
| 6335 |
PRH_VAR_EEPROM_ADDR[127]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CAL_CH); |
| 6336 |
#ifdef I386 |
| 6337 |
PRH_VAR_NAME[127]="CAL_CH" |
| 6338 |
#endif // ifdef I386 |
| 6339 |
// PRH_VAR_PTR[128]=&PRH_VAR_CAL_TEMP; |
| 6340 |
PRH_VAR_EEPROM_ADDR[128]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CAL_TEMP); |
| 6341 |
#ifdef I386 |
| 6342 |
PRH_VAR_NAME[128]="CAL_TEMP" |
| 6343 |
#endif // ifdef I386 |
| 6344 |
// PRH_VAR_PTR[129]=&PRH_VAR_CAL_OK; |
| 6345 |
PRH_VAR_EEPROM_ADDR[129]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CAL_OK); |
| 6346 |
#ifdef I386 |
| 6347 |
PRH_VAR_NAME[129]="CAL_OK" |
| 6348 |
#endif // ifdef I386 |
| 6349 |
// PRH_VAR_PTR[130]=&PRH_VAR_CAL_CHECK_FE; |
| 6350 |
PRH_VAR_EEPROM_ADDR[130]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_CAL_CHECK_FE); |
| 6351 |
#ifdef I386 |
| 6352 |
PRH_VAR_NAME[130]="CAL_CHECK_FE" |
| 6353 |
#endif // ifdef I386 |
| 6354 |
// PRH_VAR_PTR[131]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I211; |
| 6355 |
PRH_VAR_EEPROM_ADDR[131]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I211); |
| 6356 |
#ifdef I386 |
| 6357 |
PRH_VAR_NAME[131]="BUF_LEN_CAL_WRITE_FPGA_REG_I211" |
| 6358 |
#endif // ifdef I386 |
| 6359 |
// PRH_VAR_PTR[132]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I221; |
| 6360 |
PRH_VAR_EEPROM_ADDR[132]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I221); |
| 6361 |
#ifdef I386 |
| 6362 |
PRH_VAR_NAME[132]="BUF_LEN_CAL_WRITE_FPGA_REG_I221" |
| 6363 |
#endif // ifdef I386 |
| 6364 |
// PRH_VAR_PTR[133]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I231; |
| 6365 |
PRH_VAR_EEPROM_ADDR[133]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I231); |
| 6366 |
#ifdef I386 |
| 6367 |
PRH_VAR_NAME[133]="BUF_LEN_CAL_WRITE_FPGA_REG_I231" |
| 6368 |
#endif // ifdef I386 |
| 6369 |
// PRH_VAR_PTR[134]=&PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I41; |
| 6370 |
PRH_VAR_EEPROM_ADDR[134]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I41); |
| 6371 |
#ifdef I386 |
| 6372 |
PRH_VAR_NAME[134]="BUF_LEN_CAL_WRITE_DSP_MEM_I41" |
| 6373 |
#endif // ifdef I386 |
| 6374 |
// PRH_VAR_PTR[135]=&PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I42; |
| 6375 |
PRH_VAR_EEPROM_ADDR[135]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I42); |
| 6376 |
#ifdef I386 |
| 6377 |
PRH_VAR_NAME[135]="BUF_LEN_CAL_WRITE_DSP_MEM_I42" |
| 6378 |
#endif // ifdef I386 |
| 6379 |
// PRH_VAR_PTR[136]=&PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I43; |
| 6380 |
PRH_VAR_EEPROM_ADDR[136]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_DSP_MEM_I43); |
| 6381 |
#ifdef I386 |
| 6382 |
PRH_VAR_NAME[136]="BUF_LEN_CAL_WRITE_DSP_MEM_I43" |
| 6383 |
#endif // ifdef I386 |
| 6384 |
// PRH_VAR_PTR[137]=&PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C31; |
| 6385 |
PRH_VAR_EEPROM_ADDR[137]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C31); |
| 6386 |
#ifdef I386 |
| 6387 |
PRH_VAR_NAME[137]="BUF_LEN_CAL_READ_DSP_MEM_C31" |
| 6388 |
#endif // ifdef I386 |
| 6389 |
// PRH_VAR_PTR[138]=&PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C32; |
| 6390 |
PRH_VAR_EEPROM_ADDR[138]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_READ_DSP_MEM_C32); |
| 6391 |
#ifdef I386 |
| 6392 |
PRH_VAR_NAME[138]="BUF_LEN_CAL_READ_DSP_MEM_C32" |
| 6393 |
#endif // ifdef I386 |
| 6394 |
// PRH_VAR_PTR[139]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_1; |
| 6395 |
PRH_VAR_EEPROM_ADDR[139]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_1); |
| 6396 |
#ifdef I386 |
| 6397 |
PRH_VAR_NAME[139]="BUF_LEN_CAL_WRITE_FPGA_REG_I241_1" |
| 6398 |
#endif // ifdef I386 |
| 6399 |
// PRH_VAR_PTR[140]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_2; |
| 6400 |
PRH_VAR_EEPROM_ADDR[140]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_2); |
| 6401 |
#ifdef I386 |
| 6402 |
PRH_VAR_NAME[140]="BUF_LEN_CAL_WRITE_FPGA_REG_I241_2" |
| 6403 |
#endif // ifdef I386 |
| 6404 |
// PRH_VAR_PTR[141]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_3; |
| 6405 |
PRH_VAR_EEPROM_ADDR[141]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_3); |
| 6406 |
#ifdef I386 |
| 6407 |
PRH_VAR_NAME[141]="BUF_LEN_CAL_WRITE_FPGA_REG_I241_3" |
| 6408 |
#endif // ifdef I386 |
| 6409 |
// PRH_VAR_PTR[142]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_4; |
| 6410 |
PRH_VAR_EEPROM_ADDR[142]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I241_4); |
| 6411 |
#ifdef I386 |
| 6412 |
PRH_VAR_NAME[142]="BUF_LEN_CAL_WRITE_FPGA_REG_I241_4" |
| 6413 |
#endif // ifdef I386 |
| 6414 |
// PRH_VAR_PTR[143]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_1; |
| 6415 |
PRH_VAR_EEPROM_ADDR[143]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_1); |
| 6416 |
#ifdef I386 |
| 6417 |
PRH_VAR_NAME[143]="BUF_LEN_CAL_WRITE_FPGA_REG_I251_1" |
| 6418 |
#endif // ifdef I386 |
| 6419 |
// PRH_VAR_PTR[144]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_2; |
| 6420 |
PRH_VAR_EEPROM_ADDR[144]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_2); |
| 6421 |
#ifdef I386 |
| 6422 |
PRH_VAR_NAME[144]="BUF_LEN_CAL_WRITE_FPGA_REG_I251_2" |
| 6423 |
#endif // ifdef I386 |
| 6424 |
// PRH_VAR_PTR[145]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_3; |
| 6425 |
PRH_VAR_EEPROM_ADDR[145]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_3); |
| 6426 |
#ifdef I386 |
| 6427 |
PRH_VAR_NAME[145]="BUF_LEN_CAL_WRITE_FPGA_REG_I251_3" |
| 6428 |
#endif // ifdef I386 |
| 6429 |
// PRH_VAR_PTR[146]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_4; |
| 6430 |
PRH_VAR_EEPROM_ADDR[146]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I251_4); |
| 6431 |
#ifdef I386 |
| 6432 |
PRH_VAR_NAME[146]="BUF_LEN_CAL_WRITE_FPGA_REG_I251_4" |
| 6433 |
#endif // ifdef I386 |
| 6434 |
// PRH_VAR_PTR[147]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_1; |
| 6435 |
PRH_VAR_EEPROM_ADDR[147]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_1); |
| 6436 |
#ifdef I386 |
| 6437 |
PRH_VAR_NAME[147]="BUF_LEN_CAL_WRITE_FPGA_REG_I261_1" |
| 6438 |
#endif // ifdef I386 |
| 6439 |
// PRH_VAR_PTR[148]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_2; |
| 6440 |
PRH_VAR_EEPROM_ADDR[148]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_2); |
| 6441 |
#ifdef I386 |
| 6442 |
PRH_VAR_NAME[148]="BUF_LEN_CAL_WRITE_FPGA_REG_I261_2" |
| 6443 |
#endif // ifdef I386 |
| 6444 |
// PRH_VAR_PTR[149]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_3; |
| 6445 |
PRH_VAR_EEPROM_ADDR[149]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_3); |
| 6446 |
#ifdef I386 |
| 6447 |
PRH_VAR_NAME[149]="BUF_LEN_CAL_WRITE_FPGA_REG_I261_3" |
| 6448 |
#endif // ifdef I386 |
| 6449 |
// PRH_VAR_PTR[150]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_4; |
| 6450 |
PRH_VAR_EEPROM_ADDR[150]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I261_4); |
| 6451 |
#ifdef I386 |
| 6452 |
PRH_VAR_NAME[150]="BUF_LEN_CAL_WRITE_FPGA_REG_I261_4" |
| 6453 |
#endif // ifdef I386 |
| 6454 |
// PRH_VAR_PTR[151]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_1; |
| 6455 |
PRH_VAR_EEPROM_ADDR[151]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_1); |
| 6456 |
#ifdef I386 |
| 6457 |
PRH_VAR_NAME[151]="BUF_LEN_CAL_WRITE_FPGA_REG_I260_1" |
| 6458 |
#endif // ifdef I386 |
| 6459 |
// PRH_VAR_PTR[152]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_2; |
| 6460 |
PRH_VAR_EEPROM_ADDR[152]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_2); |
| 6461 |
#ifdef I386 |
| 6462 |
PRH_VAR_NAME[152]="BUF_LEN_CAL_WRITE_FPGA_REG_I260_2" |
| 6463 |
#endif // ifdef I386 |
| 6464 |
// PRH_VAR_PTR[153]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_3; |
| 6465 |
PRH_VAR_EEPROM_ADDR[153]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_3); |
| 6466 |
#ifdef I386 |
| 6467 |
PRH_VAR_NAME[153]="BUF_LEN_CAL_WRITE_FPGA_REG_I260_3" |
| 6468 |
#endif // ifdef I386 |
| 6469 |
// PRH_VAR_PTR[154]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_4; |
| 6470 |
PRH_VAR_EEPROM_ADDR[154]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I260_4); |
| 6471 |
#ifdef I386 |
| 6472 |
PRH_VAR_NAME[154]="BUF_LEN_CAL_WRITE_FPGA_REG_I260_4" |
| 6473 |
#endif // ifdef I386 |
| 6474 |
// PRH_VAR_PTR[155]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_1; |
| 6475 |
PRH_VAR_EEPROM_ADDR[155]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_1); |
| 6476 |
#ifdef I386 |
| 6477 |
PRH_VAR_NAME[155]="BUF_LEN_CAL_WRITE_FPGA_REG_I311_1" |
| 6478 |
#endif // ifdef I386 |
| 6479 |
// PRH_VAR_PTR[156]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_2; |
| 6480 |
PRH_VAR_EEPROM_ADDR[156]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_2); |
| 6481 |
#ifdef I386 |
| 6482 |
PRH_VAR_NAME[156]="BUF_LEN_CAL_WRITE_FPGA_REG_I311_2" |
| 6483 |
#endif // ifdef I386 |
| 6484 |
// PRH_VAR_PTR[157]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_3; |
| 6485 |
PRH_VAR_EEPROM_ADDR[157]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_3); |
| 6486 |
#ifdef I386 |
| 6487 |
PRH_VAR_NAME[157]="BUF_LEN_CAL_WRITE_FPGA_REG_I311_3" |
| 6488 |
#endif // ifdef I386 |
| 6489 |
// PRH_VAR_PTR[158]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_4; |
| 6490 |
PRH_VAR_EEPROM_ADDR[158]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I311_4); |
| 6491 |
#ifdef I386 |
| 6492 |
PRH_VAR_NAME[158]="BUF_LEN_CAL_WRITE_FPGA_REG_I311_4" |
| 6493 |
#endif // ifdef I386 |
| 6494 |
// PRH_VAR_PTR[159]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_1; |
| 6495 |
PRH_VAR_EEPROM_ADDR[159]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_1); |
| 6496 |
#ifdef I386 |
| 6497 |
PRH_VAR_NAME[159]="BUF_LEN_CAL_WRITE_FPGA_REG_I310_1" |
| 6498 |
#endif // ifdef I386 |
| 6499 |
// PRH_VAR_PTR[160]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_2; |
| 6500 |
PRH_VAR_EEPROM_ADDR[160]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_2); |
| 6501 |
#ifdef I386 |
| 6502 |
PRH_VAR_NAME[160]="BUF_LEN_CAL_WRITE_FPGA_REG_I310_2" |
| 6503 |
#endif // ifdef I386 |
| 6504 |
// PRH_VAR_PTR[161]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_3; |
| 6505 |
PRH_VAR_EEPROM_ADDR[161]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_3); |
| 6506 |
#ifdef I386 |
| 6507 |
PRH_VAR_NAME[161]="BUF_LEN_CAL_WRITE_FPGA_REG_I310_3" |
| 6508 |
#endif // ifdef I386 |
| 6509 |
// PRH_VAR_PTR[162]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_4; |
| 6510 |
PRH_VAR_EEPROM_ADDR[162]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I310_4); |
| 6511 |
#ifdef I386 |
| 6512 |
PRH_VAR_NAME[162]="BUF_LEN_CAL_WRITE_FPGA_REG_I310_4" |
| 6513 |
#endif // ifdef I386 |
| 6514 |
// PRH_VAR_PTR[163]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I321; |
| 6515 |
PRH_VAR_EEPROM_ADDR[163]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I321); |
| 6516 |
#ifdef I386 |
| 6517 |
PRH_VAR_NAME[163]="BUF_LEN_CAL_WRITE_FPGA_REG_I321" |
| 6518 |
#endif // ifdef I386 |
| 6519 |
// PRH_VAR_PTR[164]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_1; |
| 6520 |
PRH_VAR_EEPROM_ADDR[164]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_1); |
| 6521 |
#ifdef I386 |
| 6522 |
PRH_VAR_NAME[164]="BUF_LEN_CAL_WRITE_FPGA_REG_I331_1" |
| 6523 |
#endif // ifdef I386 |
| 6524 |
// PRH_VAR_PTR[165]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_2; |
| 6525 |
PRH_VAR_EEPROM_ADDR[165]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_2); |
| 6526 |
#ifdef I386 |
| 6527 |
PRH_VAR_NAME[165]="BUF_LEN_CAL_WRITE_FPGA_REG_I331_2" |
| 6528 |
#endif // ifdef I386 |
| 6529 |
// PRH_VAR_PTR[166]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_3; |
| 6530 |
PRH_VAR_EEPROM_ADDR[166]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_3); |
| 6531 |
#ifdef I386 |
| 6532 |
PRH_VAR_NAME[166]="BUF_LEN_CAL_WRITE_FPGA_REG_I331_3" |
| 6533 |
#endif // ifdef I386 |
| 6534 |
// PRH_VAR_PTR[167]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_4; |
| 6535 |
PRH_VAR_EEPROM_ADDR[167]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I331_4); |
| 6536 |
#ifdef I386 |
| 6537 |
PRH_VAR_NAME[167]="BUF_LEN_CAL_WRITE_FPGA_REG_I331_4" |
| 6538 |
#endif // ifdef I386 |
| 6539 |
// PRH_VAR_PTR[168]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_OFF; |
| 6540 |
PRH_VAR_EEPROM_ADDR[168]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_OFF); |
| 6541 |
#ifdef I386 |
| 6542 |
PRH_VAR_NAME[168]="BUF_LEN_CAL_WRITE_FPGA_REG_OFF" |
| 6543 |
#endif // ifdef I386 |
| 6544 |
// PRH_VAR_PTR[169]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_1; |
| 6545 |
PRH_VAR_EEPROM_ADDR[169]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_1); |
| 6546 |
#ifdef I386 |
| 6547 |
PRH_VAR_NAME[169]="BUF_LEN_CAL_WRITE_FPGA_REG_I341_1" |
| 6548 |
#endif // ifdef I386 |
| 6549 |
// PRH_VAR_PTR[170]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_2; |
| 6550 |
PRH_VAR_EEPROM_ADDR[170]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_2); |
| 6551 |
#ifdef I386 |
| 6552 |
PRH_VAR_NAME[170]="BUF_LEN_CAL_WRITE_FPGA_REG_I341_2" |
| 6553 |
#endif // ifdef I386 |
| 6554 |
// PRH_VAR_PTR[171]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_3; |
| 6555 |
PRH_VAR_EEPROM_ADDR[171]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_3); |
| 6556 |
#ifdef I386 |
| 6557 |
PRH_VAR_NAME[171]="BUF_LEN_CAL_WRITE_FPGA_REG_I341_3" |
| 6558 |
#endif // ifdef I386 |
| 6559 |
// PRH_VAR_PTR[172]=&PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_4; |
| 6560 |
PRH_VAR_EEPROM_ADDR[172]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_CAL_WRITE_FPGA_REG_I341_4); |
| 6561 |
#ifdef I386 |
| 6562 |
PRH_VAR_NAME[172]="BUF_LEN_CAL_WRITE_FPGA_REG_I341_4" |
| 6563 |
#endif // ifdef I386 |
| 6564 |
// PRH_VAR_PTR[173]=&PRH_VAR_AC_1_OK; |
| 6565 |
PRH_VAR_EEPROM_ADDR[173]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_AC_1_OK); |
| 6566 |
#ifdef I386 |
| 6567 |
PRH_VAR_NAME[173]="AC_1_OK" |
| 6568 |
#endif // ifdef I386 |
| 6569 |
// PRH_VAR_PTR[174]=&PRH_VAR_AC_2_OK; |
| 6570 |
PRH_VAR_EEPROM_ADDR[174]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_AC_2_OK); |
| 6571 |
#ifdef I386 |
| 6572 |
PRH_VAR_NAME[174]="AC_2_OK" |
| 6573 |
#endif // ifdef I386 |
| 6574 |
// PRH_VAR_PTR[175]=&PRH_VAR_AC_1_CHECK; |
| 6575 |
PRH_VAR_EEPROM_ADDR[175]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_AC_1_CHECK); |
| 6576 |
#ifdef I386 |
| 6577 |
PRH_VAR_NAME[175]="AC_1_CHECK" |
| 6578 |
#endif // ifdef I386 |
| 6579 |
// PRH_VAR_PTR[176]=&PRH_VAR_AC_2_CHECK; |
| 6580 |
PRH_VAR_EEPROM_ADDR[176]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_AC_2_CHECK); |
| 6581 |
#ifdef I386 |
| 6582 |
PRH_VAR_NAME[176]="AC_2_CHECK" |
| 6583 |
#endif // ifdef I386 |
| 6584 |
// PRH_VAR_PTR[177]=&PRH_VAR_AC_LOOP; |
| 6585 |
PRH_VAR_EEPROM_ADDR[177]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_AC_LOOP); |
| 6586 |
#ifdef I386 |
| 6587 |
PRH_VAR_NAME[177]="AC_LOOP" |
| 6588 |
#endif // ifdef I386 |
| 6589 |
// PRH_VAR_PTR[178]=&PRH_VAR_AC_LOOP2; |
| 6590 |
PRH_VAR_EEPROM_ADDR[178]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_AC_LOOP2); |
| 6591 |
#ifdef I386 |
| 6592 |
PRH_VAR_NAME[178]="AC_LOOP2" |
| 6593 |
#endif // ifdef I386 |
| 6594 |
// PRH_VAR_PTR[179]=&PRH_VAR_BUF_LEN_AC_1_SET_DAQ; |
| 6595 |
PRH_VAR_EEPROM_ADDR[179]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_1_SET_DAQ); |
| 6596 |
#ifdef I386 |
| 6597 |
PRH_VAR_NAME[179]="BUF_LEN_AC_1_SET_DAQ" |
| 6598 |
#endif // ifdef I386 |
| 6599 |
// PRH_VAR_PTR[180]=&PRH_VAR_BUF_LEN_AC_2_SET_DAQ; |
| 6600 |
PRH_VAR_EEPROM_ADDR[180]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_2_SET_DAQ); |
| 6601 |
#ifdef I386 |
| 6602 |
PRH_VAR_NAME[180]="BUF_LEN_AC_2_SET_DAQ" |
| 6603 |
#endif // ifdef I386 |
| 6604 |
// PRH_VAR_PTR[181]=&PRH_VAR_BUF_LEN_AC_SEND_DSP_PROG1; |
| 6605 |
PRH_VAR_EEPROM_ADDR[181]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_SEND_DSP_PROG1); |
| 6606 |
#ifdef I386 |
| 6607 |
PRH_VAR_NAME[181]="BUF_LEN_AC_SEND_DSP_PROG1" |
| 6608 |
#endif // ifdef I386 |
| 6609 |
// PRH_VAR_PTR[182]=&PRH_VAR_BUF_LEN_AC_1_SEND_DSP_PROG2; |
| 6610 |
PRH_VAR_EEPROM_ADDR[182]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_1_SEND_DSP_PROG2); |
| 6611 |
#ifdef I386 |
| 6612 |
PRH_VAR_NAME[182]="BUF_LEN_AC_1_SEND_DSP_PROG2" |
| 6613 |
#endif // ifdef I386 |
| 6614 |
// PRH_VAR_PTR[183]=&PRH_VAR_BUF_LEN_AC_2_SEND_DSP_PROG2; |
| 6615 |
PRH_VAR_EEPROM_ADDR[183]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_2_SEND_DSP_PROG2); |
| 6616 |
#ifdef I386 |
| 6617 |
PRH_VAR_NAME[183]="BUF_LEN_AC_2_SEND_DSP_PROG2" |
| 6618 |
#endif // ifdef I386 |
| 6619 |
// PRH_VAR_PTR[184]=&PRH_VAR_BUF_LEN_AC_2_WRITE_REG; |
| 6620 |
PRH_VAR_EEPROM_ADDR[184]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_2_WRITE_REG); |
| 6621 |
#ifdef I386 |
| 6622 |
PRH_VAR_NAME[184]="BUF_LEN_AC_2_WRITE_REG" |
| 6623 |
#endif // ifdef I386 |
| 6624 |
// PRH_VAR_PTR[185]=&PRH_VAR_BUF_LEN_AC_1_WRITE_REG; |
| 6625 |
PRH_VAR_EEPROM_ADDR[185]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_1_WRITE_REG); |
| 6626 |
#ifdef I386 |
| 6627 |
PRH_VAR_NAME[185]="BUF_LEN_AC_1_WRITE_REG" |
| 6628 |
#endif // ifdef I386 |
| 6629 |
// PRH_VAR_PTR[186]=&PRH_VAR_BUF_LEN_AC_READ_DSP_MEM; |
| 6630 |
PRH_VAR_EEPROM_ADDR[186]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_AC_READ_DSP_MEM); |
| 6631 |
#ifdef I386 |
| 6632 |
PRH_VAR_NAME[186]="BUF_LEN_AC_READ_DSP_MEM" |
| 6633 |
#endif // ifdef I386 |
| 6634 |
// PRH_VAR_PTR[187]=&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_1; |
| 6635 |
PRH_VAR_EEPROM_ADDR[187]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_1); |
| 6636 |
#ifdef I386 |
| 6637 |
PRH_VAR_NAME[187]="BUF_LEN_TOF_WRITE_PMT_THR_1" |
| 6638 |
#endif // ifdef I386 |
| 6639 |
// PRH_VAR_PTR[188]=&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_2; |
| 6640 |
PRH_VAR_EEPROM_ADDR[188]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_2); |
| 6641 |
#ifdef I386 |
| 6642 |
PRH_VAR_NAME[188]="BUF_LEN_TOF_WRITE_PMT_THR_2" |
| 6643 |
#endif // ifdef I386 |
| 6644 |
// PRH_VAR_PTR[189]=&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_3; |
| 6645 |
PRH_VAR_EEPROM_ADDR[189]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_3); |
| 6646 |
#ifdef I386 |
| 6647 |
PRH_VAR_NAME[189]="BUF_LEN_TOF_WRITE_PMT_THR_3" |
| 6648 |
#endif // ifdef I386 |
| 6649 |
// PRH_VAR_PTR[190]=&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_4; |
| 6650 |
PRH_VAR_EEPROM_ADDR[190]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_4); |
| 6651 |
#ifdef I386 |
| 6652 |
PRH_VAR_NAME[190]="BUF_LEN_TOF_WRITE_PMT_THR_4" |
| 6653 |
#endif // ifdef I386 |
| 6654 |
// PRH_VAR_PTR[191]=&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_5; |
| 6655 |
PRH_VAR_EEPROM_ADDR[191]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_5); |
| 6656 |
#ifdef I386 |
| 6657 |
PRH_VAR_NAME[191]="BUF_LEN_TOF_WRITE_PMT_THR_5" |
| 6658 |
#endif // ifdef I386 |
| 6659 |
// PRH_VAR_PTR[192]=&PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_6; |
| 6660 |
PRH_VAR_EEPROM_ADDR[192]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_BUF_LEN_TOF_WRITE_PMT_THR_6); |
| 6661 |
#ifdef I386 |
| 6662 |
PRH_VAR_NAME[192]="BUF_LEN_TOF_WRITE_PMT_THR_6" |
| 6663 |
#endif // ifdef I386 |
| 6664 |
// PRH_VAR_PTR[193]=&PRH_VAR_TOF_OK; |
| 6665 |
PRH_VAR_EEPROM_ADDR[193]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TOF_OK); |
| 6666 |
#ifdef I386 |
| 6667 |
PRH_VAR_NAME[193]="TOF_OK" |
| 6668 |
#endif // ifdef I386 |
| 6669 |
// PRH_VAR_PTR[194]=&PRH_VAR_ND_OK; |
| 6670 |
PRH_VAR_EEPROM_ADDR[194]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_ND_OK); |
| 6671 |
#ifdef I386 |
| 6672 |
PRH_VAR_NAME[194]="ND_OK" |
| 6673 |
#endif // ifdef I386 |
| 6674 |
// PRH_VAR_PTR[195]=&PRH_VAR_ND_ATTEMPT; |
| 6675 |
PRH_VAR_EEPROM_ADDR[195]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_ND_ATTEMPT); |
| 6676 |
#ifdef I386 |
| 6677 |
PRH_VAR_NAME[195]="ND_ATTEMPT" |
| 6678 |
#endif // ifdef I386 |
| 6679 |
// PRH_VAR_PTR[196]=&PRH_VAR_ND_CMDS; |
| 6680 |
PRH_VAR_EEPROM_ADDR[196]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_ND_CMDS); |
| 6681 |
#ifdef I386 |
| 6682 |
PRH_VAR_NAME[196]="ND_CMDS" |
| 6683 |
#endif // ifdef I386 |
| 6684 |
// PRH_VAR_PTR[197]=&PRH_VAR_SCM_TM_DO_CHECK_VALUES_FREQ; |
| 6685 |
PRH_VAR_EEPROM_ADDR[197]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_SCM_TM_DO_CHECK_VALUES_FREQ); |
| 6686 |
#ifdef I386 |
| 6687 |
PRH_VAR_NAME[197]="SCM_TM_DO_CHECK_VALUES_FREQ" |
| 6688 |
#endif // ifdef I386 |
| 6689 |
// PRH_VAR_PTR[198]=&PRH_VAR_POWER_KHB; |
| 6690 |
PRH_VAR_EEPROM_ADDR[198]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_POWER_KHB); |
| 6691 |
#ifdef I386 |
| 6692 |
PRH_VAR_NAME[198]="POWER_KHB" |
| 6693 |
#endif // ifdef I386 |
| 6694 |
// PRH_VAR_PTR[199]=&PRH_VAR_PSB_TRB_S9004_ALL_ON_DELAY; |
| 6695 |
PRH_VAR_EEPROM_ADDR[199]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PSB_TRB_S9004_ALL_ON_DELAY); |
| 6696 |
#ifdef I386 |
| 6697 |
PRH_VAR_NAME[199]="PSB_TRB_S9004_ALL_ON_DELAY" |
| 6698 |
#endif // ifdef I386 |
| 6699 |
// PRH_VAR_PTR[200]=&PRH_VAR_PSB_TRB_BIAS_WAIT; |
| 6700 |
PRH_VAR_EEPROM_ADDR[200]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PSB_TRB_BIAS_WAIT); |
| 6701 |
#ifdef I386 |
| 6702 |
PRH_VAR_NAME[200]="PSB_TRB_BIAS_WAIT" |
| 6703 |
#endif // ifdef I386 |
| 6704 |
// PRH_VAR_PTR[201]=&PRH_VAR_PSB_CALOFE_DELAY; |
| 6705 |
PRH_VAR_EEPROM_ADDR[201]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_PSB_CALOFE_DELAY); |
| 6706 |
#ifdef I386 |
| 6707 |
PRH_VAR_NAME[201]="PSB_CALOFE_DELAY" |
| 6708 |
#endif // ifdef I386 |
| 6709 |
// PRH_VAR_PTR[202]=&PRH_VAR_HV_OK; |
| 6710 |
PRH_VAR_EEPROM_ADDR[202]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_HV_OK); |
| 6711 |
#ifdef I386 |
| 6712 |
PRH_VAR_NAME[202]="HV_OK" |
| 6713 |
#endif // ifdef I386 |
| 6714 |
// PRH_VAR_PTR[203]=&PRH_VAR_TSB_T_OK; |
| 6715 |
PRH_VAR_EEPROM_ADDR[203]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TSB_T_OK); |
| 6716 |
#ifdef I386 |
| 6717 |
PRH_VAR_NAME[203]="TSB_T_OK" |
| 6718 |
#endif // ifdef I386 |
| 6719 |
// PRH_VAR_PTR[204]=&PRH_VAR_TSB_B_OK; |
| 6720 |
PRH_VAR_EEPROM_ADDR[204]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_TSB_B_OK); |
| 6721 |
#ifdef I386 |
| 6722 |
PRH_VAR_NAME[204]="TSB_B_OK" |
| 6723 |
#endif // ifdef I386 |
| 6724 |
// PRH_VAR_PTR[205]=&PRH_VAR_ALLPAGEAVAIL_ATTEMPT; |
| 6725 |
PRH_VAR_EEPROM_ADDR[205]=prec_eeprom; prec_eeprom+=sizeof(PRH_VAR_ALLPAGEAVAIL_ATTEMPT); |
| 6726 |
#ifdef I386 |
| 6727 |
PRH_VAR_NAME[205]="ALLPAGEAVAIL_ATTEMPT" |
| 6728 |
#endif // ifdef I386 |
| 6729 |
|
| 6730 |
// init PTR look-up for ARRAYs: |
| 6731 |
|
| 6732 |
|
| 6733 |
// PRH_ARR_PTR[0]=PRH_ARR_LOG_MASK; |
| 6734 |
// PRH_ARR_N[0]=PRH_ARR_N_LOG_MASK; |
| 6735 |
PRH_ARR_EEPROM_ADDR[0]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_LOG_MASK); |
| 6736 |
#ifdef I386 |
| 6737 |
PRH_ARR_NAME[0]="LOG_MASK" |
| 6738 |
#endif // ifdef I386 |
| 6739 |
|
| 6740 |
// PRH_ARR_PTR[1]=PRH_ARR_THERM_LOW; |
| 6741 |
// PRH_ARR_N[1]=PRH_ARR_N_THERM_LOW; |
| 6742 |
PRH_ARR_EEPROM_ADDR[1]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_THERM_LOW); |
| 6743 |
#ifdef I386 |
| 6744 |
PRH_ARR_NAME[1]="THERM_LOW" |
| 6745 |
#endif // ifdef I386 |
| 6746 |
|
| 6747 |
// PRH_ARR_PTR[2]=PRH_ARR_THERM_HIGH; |
| 6748 |
// PRH_ARR_N[2]=PRH_ARR_N_THERM_HIGH; |
| 6749 |
PRH_ARR_EEPROM_ADDR[2]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_THERM_HIGH); |
| 6750 |
#ifdef I386 |
| 6751 |
PRH_ARR_NAME[2]="THERM_HIGH" |
| 6752 |
#endif // ifdef I386 |
| 6753 |
|
| 6754 |
// PRH_ARR_PTR[3]=PRH_ARR_BUF_TRIG_II_INIT; |
| 6755 |
// PRH_ARR_N[3]=PRH_ARR_N_BUF_TRIG_II_INIT; |
| 6756 |
PRH_ARR_EEPROM_ADDR[3]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRIG_II_INIT); |
| 6757 |
#ifdef I386 |
| 6758 |
PRH_ARR_NAME[3]="BUF_TRIG_II_INIT" |
| 6759 |
#endif // ifdef I386 |
| 6760 |
|
| 6761 |
// PRH_ARR_PTR[4]=PRH_ARR_BUF_TRIG_II_ACQ; |
| 6762 |
// PRH_ARR_N[4]=PRH_ARR_N_BUF_TRIG_II_ACQ; |
| 6763 |
PRH_ARR_EEPROM_ADDR[4]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRIG_II_ACQ); |
| 6764 |
#ifdef I386 |
| 6765 |
PRH_ARR_NAME[4]="BUF_TRIG_II_ACQ" |
| 6766 |
#endif // ifdef I386 |
| 6767 |
|
| 6768 |
// PRH_ARR_PTR[5]=PRH_ARR_WS_1_SETTING; |
| 6769 |
// PRH_ARR_N[5]=PRH_ARR_N_WS_1_SETTING; |
| 6770 |
PRH_ARR_EEPROM_ADDR[5]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_WS_1_SETTING); |
| 6771 |
#ifdef I386 |
| 6772 |
PRH_ARR_NAME[5]="WS_1_SETTING" |
| 6773 |
#endif // ifdef I386 |
| 6774 |
|
| 6775 |
// PRH_ARR_PTR[6]=PRH_ARR_RM_RATE_METER_S1_TRH; |
| 6776 |
// PRH_ARR_N[6]=PRH_ARR_N_RM_RATE_METER_S1_TRH; |
| 6777 |
PRH_ARR_EEPROM_ADDR[6]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_RM_RATE_METER_S1_TRH); |
| 6778 |
#ifdef I386 |
| 6779 |
PRH_ARR_NAME[6]="RM_RATE_METER_S1_TRH" |
| 6780 |
#endif // ifdef I386 |
| 6781 |
|
| 6782 |
// PRH_ARR_PTR[7]=PRH_ARR_PWR_IPM_CONF; |
| 6783 |
// PRH_ARR_N[7]=PRH_ARR_N_PWR_IPM_CONF; |
| 6784 |
PRH_ARR_EEPROM_ADDR[7]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PWR_IPM_CONF); |
| 6785 |
#ifdef I386 |
| 6786 |
PRH_ARR_NAME[7]="PWR_IPM_CONF" |
| 6787 |
#endif // ifdef I386 |
| 6788 |
|
| 6789 |
// PRH_ARR_PTR[8]=PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MAX; |
| 6790 |
// PRH_ARR_N[8]=PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_ON_MAX; |
| 6791 |
PRH_ARR_EEPROM_ADDR[8]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MAX); |
| 6792 |
#ifdef I386 |
| 6793 |
PRH_ARR_NAME[8]="PWR_VOLTAGE_IPM_RANGE_ON_MAX" |
| 6794 |
#endif // ifdef I386 |
| 6795 |
|
| 6796 |
// PRH_ARR_PTR[9]=PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MIN; |
| 6797 |
// PRH_ARR_N[9]=PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_ON_MIN; |
| 6798 |
PRH_ARR_EEPROM_ADDR[9]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PWR_VOLTAGE_IPM_RANGE_ON_MIN); |
| 6799 |
#ifdef I386 |
| 6800 |
PRH_ARR_NAME[9]="PWR_VOLTAGE_IPM_RANGE_ON_MIN" |
| 6801 |
#endif // ifdef I386 |
| 6802 |
|
| 6803 |
// PRH_ARR_PTR[10]=PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MAX; |
| 6804 |
// PRH_ARR_N[10]=PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_OFF_MAX; |
| 6805 |
PRH_ARR_EEPROM_ADDR[10]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MAX); |
| 6806 |
#ifdef I386 |
| 6807 |
PRH_ARR_NAME[10]="PWR_VOLTAGE_IPM_RANGE_OFF_MAX" |
| 6808 |
#endif // ifdef I386 |
| 6809 |
|
| 6810 |
// PRH_ARR_PTR[11]=PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MIN; |
| 6811 |
// PRH_ARR_N[11]=PRH_ARR_N_PWR_VOLTAGE_IPM_RANGE_OFF_MIN; |
| 6812 |
PRH_ARR_EEPROM_ADDR[11]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PWR_VOLTAGE_IPM_RANGE_OFF_MIN); |
| 6813 |
#ifdef I386 |
| 6814 |
PRH_ARR_NAME[11]="PWR_VOLTAGE_IPM_RANGE_OFF_MIN" |
| 6815 |
#endif // ifdef I386 |
| 6816 |
|
| 6817 |
// PRH_ARR_PTR[12]=PRH_ARR_TM_FILTER_OPERATION; |
| 6818 |
// PRH_ARR_N[12]=PRH_ARR_N_TM_FILTER_OPERATION; |
| 6819 |
PRH_ARR_EEPROM_ADDR[12]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_TM_FILTER_OPERATION); |
| 6820 |
#ifdef I386 |
| 6821 |
PRH_ARR_NAME[12]="TM_FILTER_OPERATION" |
| 6822 |
#endif // ifdef I386 |
| 6823 |
|
| 6824 |
// PRH_ARR_PTR[13]=PRH_ARR_TM_FILTER_VALUE; |
| 6825 |
// PRH_ARR_N[13]=PRH_ARR_N_TM_FILTER_VALUE; |
| 6826 |
PRH_ARR_EEPROM_ADDR[13]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_TM_FILTER_VALUE); |
| 6827 |
#ifdef I386 |
| 6828 |
PRH_ARR_NAME[13]="TM_FILTER_VALUE" |
| 6829 |
#endif // ifdef I386 |
| 6830 |
|
| 6831 |
// PRH_ARR_PTR[14]=PRH_ARR_BUF_TB_SET_ALARM_MASK; |
| 6832 |
// PRH_ARR_N[14]=PRH_ARR_N_BUF_TB_SET_ALARM_MASK; |
| 6833 |
PRH_ARR_EEPROM_ADDR[14]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TB_SET_ALARM_MASK); |
| 6834 |
#ifdef I386 |
| 6835 |
PRH_ARR_NAME[14]="BUF_TB_SET_ALARM_MASK" |
| 6836 |
#endif // ifdef I386 |
| 6837 |
|
| 6838 |
// PRH_ARR_PTR[15]=PRH_ARR_BUF_TB_SET_PMT_MASK; |
| 6839 |
// PRH_ARR_N[15]=PRH_ARR_N_BUF_TB_SET_PMT_MASK; |
| 6840 |
PRH_ARR_EEPROM_ADDR[15]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TB_SET_PMT_MASK); |
| 6841 |
#ifdef I386 |
| 6842 |
PRH_ARR_NAME[15]="BUF_TB_SET_PMT_MASK" |
| 6843 |
#endif // ifdef I386 |
| 6844 |
|
| 6845 |
// PRH_ARR_PTR[16]=PRH_ARR_BUF_TB_SET_S4_CAL_MASK; |
| 6846 |
// PRH_ARR_N[16]=PRH_ARR_N_BUF_TB_SET_S4_CAL_MASK; |
| 6847 |
PRH_ARR_EEPROM_ADDR[16]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TB_SET_S4_CAL_MASK); |
| 6848 |
#ifdef I386 |
| 6849 |
PRH_ARR_NAME[16]="BUF_TB_SET_S4_CAL_MASK" |
| 6850 |
#endif // ifdef I386 |
| 6851 |
|
| 6852 |
// PRH_ARR_PTR[17]=PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_HOT; |
| 6853 |
// PRH_ARR_N[17]=PRH_ARR_N_BUF_TB_SET_BUSY_MASK_IDAQ_HOT; |
| 6854 |
PRH_ARR_EEPROM_ADDR[17]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_HOT); |
| 6855 |
#ifdef I386 |
| 6856 |
PRH_ARR_NAME[17]="BUF_TB_SET_BUSY_MASK_IDAQ_HOT" |
| 6857 |
#endif // ifdef I386 |
| 6858 |
|
| 6859 |
// PRH_ARR_PTR[18]=PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_COLD; |
| 6860 |
// PRH_ARR_N[18]=PRH_ARR_N_BUF_TB_SET_BUSY_MASK_IDAQ_COLD; |
| 6861 |
PRH_ARR_EEPROM_ADDR[18]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TB_SET_BUSY_MASK_IDAQ_COLD); |
| 6862 |
#ifdef I386 |
| 6863 |
PRH_ARR_NAME[18]="BUF_TB_SET_BUSY_MASK_IDAQ_COLD" |
| 6864 |
#endif // ifdef I386 |
| 6865 |
|
| 6866 |
// PRH_ARR_PTR[19]=PRH_ARR_TRK_LOAD_PRG; |
| 6867 |
// PRH_ARR_N[19]=PRH_ARR_N_TRK_LOAD_PRG; |
| 6868 |
PRH_ARR_EEPROM_ADDR[19]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_TRK_LOAD_PRG); |
| 6869 |
#ifdef I386 |
| 6870 |
PRH_ARR_NAME[19]="TRK_LOAD_PRG" |
| 6871 |
#endif // ifdef I386 |
| 6872 |
|
| 6873 |
// PRH_ARR_PTR[20]=PRH_ARR_BUF_TRK_PROGRAM; |
| 6874 |
// PRH_ARR_N[20]=PRH_ARR_N_BUF_TRK_PROGRAM; |
| 6875 |
PRH_ARR_EEPROM_ADDR[20]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_PROGRAM); |
| 6876 |
#ifdef I386 |
| 6877 |
PRH_ARR_NAME[20]="BUF_TRK_PROGRAM" |
| 6878 |
#endif // ifdef I386 |
| 6879 |
|
| 6880 |
// PRH_ARR_PTR[21]=PRH_ARR_BUF_TRK_TRAILER_PRG_0; |
| 6881 |
// PRH_ARR_N[21]=PRH_ARR_N_BUF_TRK_TRAILER_PRG_0; |
| 6882 |
PRH_ARR_EEPROM_ADDR[21]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_TRAILER_PRG_0); |
| 6883 |
#ifdef I386 |
| 6884 |
PRH_ARR_NAME[21]="BUF_TRK_TRAILER_PRG_0" |
| 6885 |
#endif // ifdef I386 |
| 6886 |
|
| 6887 |
// PRH_ARR_PTR[22]=PRH_ARR_BUF_TRK_TRAILER_PRG_1; |
| 6888 |
// PRH_ARR_N[22]=PRH_ARR_N_BUF_TRK_TRAILER_PRG_1; |
| 6889 |
PRH_ARR_EEPROM_ADDR[22]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_TRAILER_PRG_1); |
| 6890 |
#ifdef I386 |
| 6891 |
PRH_ARR_NAME[22]="BUF_TRK_TRAILER_PRG_1" |
| 6892 |
#endif // ifdef I386 |
| 6893 |
|
| 6894 |
// PRH_ARR_PTR[23]=PRH_ARR_BUF_TRK_TRAILER_PRG_2; |
| 6895 |
// PRH_ARR_N[23]=PRH_ARR_N_BUF_TRK_TRAILER_PRG_2; |
| 6896 |
PRH_ARR_EEPROM_ADDR[23]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_TRAILER_PRG_2); |
| 6897 |
#ifdef I386 |
| 6898 |
PRH_ARR_NAME[23]="BUF_TRK_TRAILER_PRG_2" |
| 6899 |
#endif // ifdef I386 |
| 6900 |
|
| 6901 |
// PRH_ARR_PTR[24]=PRH_ARR_BUF_TRK_TRAILER_PRG_3; |
| 6902 |
// PRH_ARR_N[24]=PRH_ARR_N_BUF_TRK_TRAILER_PRG_3; |
| 6903 |
PRH_ARR_EEPROM_ADDR[24]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_TRAILER_PRG_3); |
| 6904 |
#ifdef I386 |
| 6905 |
PRH_ARR_NAME[24]="BUF_TRK_TRAILER_PRG_3" |
| 6906 |
#endif // ifdef I386 |
| 6907 |
|
| 6908 |
// PRH_ARR_PTR[25]=PRH_ARR_BUF_TRK_TRAILER_PRG_4; |
| 6909 |
// PRH_ARR_N[25]=PRH_ARR_N_BUF_TRK_TRAILER_PRG_4; |
| 6910 |
PRH_ARR_EEPROM_ADDR[25]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_TRAILER_PRG_4); |
| 6911 |
#ifdef I386 |
| 6912 |
PRH_ARR_NAME[25]="BUF_TRK_TRAILER_PRG_4" |
| 6913 |
#endif // ifdef I386 |
| 6914 |
|
| 6915 |
// PRH_ARR_PTR[26]=PRH_ARR_BUF_TRK_TRAILER_PRG_5; |
| 6916 |
// PRH_ARR_N[26]=PRH_ARR_N_BUF_TRK_TRAILER_PRG_5; |
| 6917 |
PRH_ARR_EEPROM_ADDR[26]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_TRAILER_PRG_5); |
| 6918 |
#ifdef I386 |
| 6919 |
PRH_ARR_NAME[26]="BUF_TRK_TRAILER_PRG_5" |
| 6920 |
#endif // ifdef I386 |
| 6921 |
|
| 6922 |
// PRH_ARR_PTR[27]=PRH_ARR_BUF_TRK_NUMBER_DSP_1_0; |
| 6923 |
// PRH_ARR_N[27]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_0; |
| 6924 |
PRH_ARR_EEPROM_ADDR[27]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_1_0); |
| 6925 |
#ifdef I386 |
| 6926 |
PRH_ARR_NAME[27]="BUF_TRK_NUMBER_DSP_1_0" |
| 6927 |
#endif // ifdef I386 |
| 6928 |
|
| 6929 |
// PRH_ARR_PTR[28]=PRH_ARR_BUF_TRK_NUMBER_DSP_1_1; |
| 6930 |
// PRH_ARR_N[28]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_1; |
| 6931 |
PRH_ARR_EEPROM_ADDR[28]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_1_1); |
| 6932 |
#ifdef I386 |
| 6933 |
PRH_ARR_NAME[28]="BUF_TRK_NUMBER_DSP_1_1" |
| 6934 |
#endif // ifdef I386 |
| 6935 |
|
| 6936 |
// PRH_ARR_PTR[29]=PRH_ARR_BUF_TRK_NUMBER_DSP_1_2; |
| 6937 |
// PRH_ARR_N[29]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_2; |
| 6938 |
PRH_ARR_EEPROM_ADDR[29]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_1_2); |
| 6939 |
#ifdef I386 |
| 6940 |
PRH_ARR_NAME[29]="BUF_TRK_NUMBER_DSP_1_2" |
| 6941 |
#endif // ifdef I386 |
| 6942 |
|
| 6943 |
// PRH_ARR_PTR[30]=PRH_ARR_BUF_TRK_NUMBER_DSP_1_3; |
| 6944 |
// PRH_ARR_N[30]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_3; |
| 6945 |
PRH_ARR_EEPROM_ADDR[30]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_1_3); |
| 6946 |
#ifdef I386 |
| 6947 |
PRH_ARR_NAME[30]="BUF_TRK_NUMBER_DSP_1_3" |
| 6948 |
#endif // ifdef I386 |
| 6949 |
|
| 6950 |
// PRH_ARR_PTR[31]=PRH_ARR_BUF_TRK_NUMBER_DSP_1_4; |
| 6951 |
// PRH_ARR_N[31]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_4; |
| 6952 |
PRH_ARR_EEPROM_ADDR[31]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_1_4); |
| 6953 |
#ifdef I386 |
| 6954 |
PRH_ARR_NAME[31]="BUF_TRK_NUMBER_DSP_1_4" |
| 6955 |
#endif // ifdef I386 |
| 6956 |
|
| 6957 |
// PRH_ARR_PTR[32]=PRH_ARR_BUF_TRK_NUMBER_DSP_1_5; |
| 6958 |
// PRH_ARR_N[32]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_1_5; |
| 6959 |
PRH_ARR_EEPROM_ADDR[32]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_1_5); |
| 6960 |
#ifdef I386 |
| 6961 |
PRH_ARR_NAME[32]="BUF_TRK_NUMBER_DSP_1_5" |
| 6962 |
#endif // ifdef I386 |
| 6963 |
|
| 6964 |
// PRH_ARR_PTR[33]=PRH_ARR_BUF_TRK_NUMBER_DSP_2_0; |
| 6965 |
// PRH_ARR_N[33]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_0; |
| 6966 |
PRH_ARR_EEPROM_ADDR[33]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_2_0); |
| 6967 |
#ifdef I386 |
| 6968 |
PRH_ARR_NAME[33]="BUF_TRK_NUMBER_DSP_2_0" |
| 6969 |
#endif // ifdef I386 |
| 6970 |
|
| 6971 |
// PRH_ARR_PTR[34]=PRH_ARR_BUF_TRK_NUMBER_DSP_2_1; |
| 6972 |
// PRH_ARR_N[34]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_1; |
| 6973 |
PRH_ARR_EEPROM_ADDR[34]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_2_1); |
| 6974 |
#ifdef I386 |
| 6975 |
PRH_ARR_NAME[34]="BUF_TRK_NUMBER_DSP_2_1" |
| 6976 |
#endif // ifdef I386 |
| 6977 |
|
| 6978 |
// PRH_ARR_PTR[35]=PRH_ARR_BUF_TRK_NUMBER_DSP_2_2; |
| 6979 |
// PRH_ARR_N[35]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_2; |
| 6980 |
PRH_ARR_EEPROM_ADDR[35]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_2_2); |
| 6981 |
#ifdef I386 |
| 6982 |
PRH_ARR_NAME[35]="BUF_TRK_NUMBER_DSP_2_2" |
| 6983 |
#endif // ifdef I386 |
| 6984 |
|
| 6985 |
// PRH_ARR_PTR[36]=PRH_ARR_BUF_TRK_NUMBER_DSP_2_3; |
| 6986 |
// PRH_ARR_N[36]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_3; |
| 6987 |
PRH_ARR_EEPROM_ADDR[36]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_2_3); |
| 6988 |
#ifdef I386 |
| 6989 |
PRH_ARR_NAME[36]="BUF_TRK_NUMBER_DSP_2_3" |
| 6990 |
#endif // ifdef I386 |
| 6991 |
|
| 6992 |
// PRH_ARR_PTR[37]=PRH_ARR_BUF_TRK_NUMBER_DSP_2_4; |
| 6993 |
// PRH_ARR_N[37]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_4; |
| 6994 |
PRH_ARR_EEPROM_ADDR[37]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_2_4); |
| 6995 |
#ifdef I386 |
| 6996 |
PRH_ARR_NAME[37]="BUF_TRK_NUMBER_DSP_2_4" |
| 6997 |
#endif // ifdef I386 |
| 6998 |
|
| 6999 |
// PRH_ARR_PTR[38]=PRH_ARR_BUF_TRK_NUMBER_DSP_2_5; |
| 7000 |
// PRH_ARR_N[38]=PRH_ARR_N_BUF_TRK_NUMBER_DSP_2_5; |
| 7001 |
PRH_ARR_EEPROM_ADDR[38]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_NUMBER_DSP_2_5); |
| 7002 |
#ifdef I386 |
| 7003 |
PRH_ARR_NAME[38]="BUF_TRK_NUMBER_DSP_2_5" |
| 7004 |
#endif // ifdef I386 |
| 7005 |
|
| 7006 |
// PRH_ARR_PTR[39]=PRH_ARR_BUF_TRK_OPMODE_COMP_0; |
| 7007 |
// PRH_ARR_N[39]=PRH_ARR_N_BUF_TRK_OPMODE_COMP_0; |
| 7008 |
PRH_ARR_EEPROM_ADDR[39]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_COMP_0); |
| 7009 |
#ifdef I386 |
| 7010 |
PRH_ARR_NAME[39]="BUF_TRK_OPMODE_COMP_0" |
| 7011 |
#endif // ifdef I386 |
| 7012 |
|
| 7013 |
// PRH_ARR_PTR[40]=PRH_ARR_BUF_TRK_OPMODE_SPEC_0; |
| 7014 |
// PRH_ARR_N[40]=PRH_ARR_N_BUF_TRK_OPMODE_SPEC_0; |
| 7015 |
PRH_ARR_EEPROM_ADDR[40]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_SPEC_0); |
| 7016 |
#ifdef I386 |
| 7017 |
PRH_ARR_NAME[40]="BUF_TRK_OPMODE_SPEC_0" |
| 7018 |
#endif // ifdef I386 |
| 7019 |
|
| 7020 |
// PRH_ARR_PTR[41]=PRH_ARR_BUF_TRK_OPMODE_COMP_1; |
| 7021 |
// PRH_ARR_N[41]=PRH_ARR_N_BUF_TRK_OPMODE_COMP_1; |
| 7022 |
PRH_ARR_EEPROM_ADDR[41]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_COMP_1); |
| 7023 |
#ifdef I386 |
| 7024 |
PRH_ARR_NAME[41]="BUF_TRK_OPMODE_COMP_1" |
| 7025 |
#endif // ifdef I386 |
| 7026 |
|
| 7027 |
// PRH_ARR_PTR[42]=PRH_ARR_BUF_TRK_OPMODE_SPEC_1; |
| 7028 |
// PRH_ARR_N[42]=PRH_ARR_N_BUF_TRK_OPMODE_SPEC_1; |
| 7029 |
PRH_ARR_EEPROM_ADDR[42]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_SPEC_1); |
| 7030 |
#ifdef I386 |
| 7031 |
PRH_ARR_NAME[42]="BUF_TRK_OPMODE_SPEC_1" |
| 7032 |
#endif // ifdef I386 |
| 7033 |
|
| 7034 |
// PRH_ARR_PTR[43]=PRH_ARR_BUF_TRK_OPMODE_COMP_2; |
| 7035 |
// PRH_ARR_N[43]=PRH_ARR_N_BUF_TRK_OPMODE_COMP_2; |
| 7036 |
PRH_ARR_EEPROM_ADDR[43]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_COMP_2); |
| 7037 |
#ifdef I386 |
| 7038 |
PRH_ARR_NAME[43]="BUF_TRK_OPMODE_COMP_2" |
| 7039 |
#endif // ifdef I386 |
| 7040 |
|
| 7041 |
// PRH_ARR_PTR[44]=PRH_ARR_BUF_TRK_OPMODE_SPEC_2; |
| 7042 |
// PRH_ARR_N[44]=PRH_ARR_N_BUF_TRK_OPMODE_SPEC_2; |
| 7043 |
PRH_ARR_EEPROM_ADDR[44]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_SPEC_2); |
| 7044 |
#ifdef I386 |
| 7045 |
PRH_ARR_NAME[44]="BUF_TRK_OPMODE_SPEC_2" |
| 7046 |
#endif // ifdef I386 |
| 7047 |
|
| 7048 |
// PRH_ARR_PTR[45]=PRH_ARR_BUF_TRK_OPMODE_COMP_3; |
| 7049 |
// PRH_ARR_N[45]=PRH_ARR_N_BUF_TRK_OPMODE_COMP_3; |
| 7050 |
PRH_ARR_EEPROM_ADDR[45]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_COMP_3); |
| 7051 |
#ifdef I386 |
| 7052 |
PRH_ARR_NAME[45]="BUF_TRK_OPMODE_COMP_3" |
| 7053 |
#endif // ifdef I386 |
| 7054 |
|
| 7055 |
// PRH_ARR_PTR[46]=PRH_ARR_BUF_TRK_OPMODE_SPEC_3; |
| 7056 |
// PRH_ARR_N[46]=PRH_ARR_N_BUF_TRK_OPMODE_SPEC_3; |
| 7057 |
PRH_ARR_EEPROM_ADDR[46]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_SPEC_3); |
| 7058 |
#ifdef I386 |
| 7059 |
PRH_ARR_NAME[46]="BUF_TRK_OPMODE_SPEC_3" |
| 7060 |
#endif // ifdef I386 |
| 7061 |
|
| 7062 |
// PRH_ARR_PTR[47]=PRH_ARR_BUF_TRK_OPMODE_COMP_4; |
| 7063 |
// PRH_ARR_N[47]=PRH_ARR_N_BUF_TRK_OPMODE_COMP_4; |
| 7064 |
PRH_ARR_EEPROM_ADDR[47]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_COMP_4); |
| 7065 |
#ifdef I386 |
| 7066 |
PRH_ARR_NAME[47]="BUF_TRK_OPMODE_COMP_4" |
| 7067 |
#endif // ifdef I386 |
| 7068 |
|
| 7069 |
// PRH_ARR_PTR[48]=PRH_ARR_BUF_TRK_OPMODE_SPEC_4; |
| 7070 |
// PRH_ARR_N[48]=PRH_ARR_N_BUF_TRK_OPMODE_SPEC_4; |
| 7071 |
PRH_ARR_EEPROM_ADDR[48]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_SPEC_4); |
| 7072 |
#ifdef I386 |
| 7073 |
PRH_ARR_NAME[48]="BUF_TRK_OPMODE_SPEC_4" |
| 7074 |
#endif // ifdef I386 |
| 7075 |
|
| 7076 |
// PRH_ARR_PTR[49]=PRH_ARR_BUF_TRK_OPMODE_COMP_5; |
| 7077 |
// PRH_ARR_N[49]=PRH_ARR_N_BUF_TRK_OPMODE_COMP_5; |
| 7078 |
PRH_ARR_EEPROM_ADDR[49]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_COMP_5); |
| 7079 |
#ifdef I386 |
| 7080 |
PRH_ARR_NAME[49]="BUF_TRK_OPMODE_COMP_5" |
| 7081 |
#endif // ifdef I386 |
| 7082 |
|
| 7083 |
// PRH_ARR_PTR[50]=PRH_ARR_BUF_TRK_OPMODE_SPEC_5; |
| 7084 |
// PRH_ARR_N[50]=PRH_ARR_N_BUF_TRK_OPMODE_SPEC_5; |
| 7085 |
PRH_ARR_EEPROM_ADDR[50]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TRK_OPMODE_SPEC_5); |
| 7086 |
#ifdef I386 |
| 7087 |
PRH_ARR_NAME[50]="BUF_TRK_OPMODE_SPEC_5" |
| 7088 |
#endif // ifdef I386 |
| 7089 |
|
| 7090 |
// PRH_ARR_PTR[51]=PRH_ARR_CAL_COUNT; |
| 7091 |
// PRH_ARR_N[51]=PRH_ARR_N_CAL_COUNT; |
| 7092 |
PRH_ARR_EEPROM_ADDR[51]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_CAL_COUNT); |
| 7093 |
#ifdef I386 |
| 7094 |
PRH_ARR_NAME[51]="CAL_COUNT" |
| 7095 |
#endif // ifdef I386 |
| 7096 |
|
| 7097 |
// PRH_ARR_PTR[52]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I211; |
| 7098 |
// PRH_ARR_N[52]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I211; |
| 7099 |
PRH_ARR_EEPROM_ADDR[52]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I211); |
| 7100 |
#ifdef I386 |
| 7101 |
PRH_ARR_NAME[52]="BUF_CAL_WRITE_FPGA_REG_I211" |
| 7102 |
#endif // ifdef I386 |
| 7103 |
|
| 7104 |
// PRH_ARR_PTR[53]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I221; |
| 7105 |
// PRH_ARR_N[53]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I221; |
| 7106 |
PRH_ARR_EEPROM_ADDR[53]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I221); |
| 7107 |
#ifdef I386 |
| 7108 |
PRH_ARR_NAME[53]="BUF_CAL_WRITE_FPGA_REG_I221" |
| 7109 |
#endif // ifdef I386 |
| 7110 |
|
| 7111 |
// PRH_ARR_PTR[54]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I231; |
| 7112 |
// PRH_ARR_N[54]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I231; |
| 7113 |
PRH_ARR_EEPROM_ADDR[54]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I231); |
| 7114 |
#ifdef I386 |
| 7115 |
PRH_ARR_NAME[54]="BUF_CAL_WRITE_FPGA_REG_I231" |
| 7116 |
#endif // ifdef I386 |
| 7117 |
|
| 7118 |
// PRH_ARR_PTR[55]=PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I41; |
| 7119 |
// PRH_ARR_N[55]=PRH_ARR_N_BUF_CAL_WRITE_DSP_MEM_I41; |
| 7120 |
PRH_ARR_EEPROM_ADDR[55]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I41); |
| 7121 |
#ifdef I386 |
| 7122 |
PRH_ARR_NAME[55]="BUF_CAL_WRITE_DSP_MEM_I41" |
| 7123 |
#endif // ifdef I386 |
| 7124 |
|
| 7125 |
// PRH_ARR_PTR[56]=PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I42; |
| 7126 |
// PRH_ARR_N[56]=PRH_ARR_N_BUF_CAL_WRITE_DSP_MEM_I42; |
| 7127 |
PRH_ARR_EEPROM_ADDR[56]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I42); |
| 7128 |
#ifdef I386 |
| 7129 |
PRH_ARR_NAME[56]="BUF_CAL_WRITE_DSP_MEM_I42" |
| 7130 |
#endif // ifdef I386 |
| 7131 |
|
| 7132 |
// PRH_ARR_PTR[57]=PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I43; |
| 7133 |
// PRH_ARR_N[57]=PRH_ARR_N_BUF_CAL_WRITE_DSP_MEM_I43; |
| 7134 |
PRH_ARR_EEPROM_ADDR[57]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_DSP_MEM_I43); |
| 7135 |
#ifdef I386 |
| 7136 |
PRH_ARR_NAME[57]="BUF_CAL_WRITE_DSP_MEM_I43" |
| 7137 |
#endif // ifdef I386 |
| 7138 |
|
| 7139 |
// PRH_ARR_PTR[58]=PRH_ARR_BUF_CAL_READ_DSP_MEM_C31; |
| 7140 |
// PRH_ARR_N[58]=PRH_ARR_N_BUF_CAL_READ_DSP_MEM_C31; |
| 7141 |
PRH_ARR_EEPROM_ADDR[58]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_READ_DSP_MEM_C31); |
| 7142 |
#ifdef I386 |
| 7143 |
PRH_ARR_NAME[58]="BUF_CAL_READ_DSP_MEM_C31" |
| 7144 |
#endif // ifdef I386 |
| 7145 |
|
| 7146 |
// PRH_ARR_PTR[59]=PRH_ARR_BUF_CAL_READ_DSP_MEM_C32; |
| 7147 |
// PRH_ARR_N[59]=PRH_ARR_N_BUF_CAL_READ_DSP_MEM_C32; |
| 7148 |
PRH_ARR_EEPROM_ADDR[59]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_READ_DSP_MEM_C32); |
| 7149 |
#ifdef I386 |
| 7150 |
PRH_ARR_NAME[59]="BUF_CAL_READ_DSP_MEM_C32" |
| 7151 |
#endif // ifdef I386 |
| 7152 |
|
| 7153 |
// PRH_ARR_PTR[60]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_1; |
| 7154 |
// PRH_ARR_N[60]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_1; |
| 7155 |
PRH_ARR_EEPROM_ADDR[60]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_1); |
| 7156 |
#ifdef I386 |
| 7157 |
PRH_ARR_NAME[60]="BUF_CAL_WRITE_FPGA_REG_I241_1" |
| 7158 |
#endif // ifdef I386 |
| 7159 |
|
| 7160 |
// PRH_ARR_PTR[61]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_2; |
| 7161 |
// PRH_ARR_N[61]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_2; |
| 7162 |
PRH_ARR_EEPROM_ADDR[61]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_2); |
| 7163 |
#ifdef I386 |
| 7164 |
PRH_ARR_NAME[61]="BUF_CAL_WRITE_FPGA_REG_I241_2" |
| 7165 |
#endif // ifdef I386 |
| 7166 |
|
| 7167 |
// PRH_ARR_PTR[62]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_3; |
| 7168 |
// PRH_ARR_N[62]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_3; |
| 7169 |
PRH_ARR_EEPROM_ADDR[62]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_3); |
| 7170 |
#ifdef I386 |
| 7171 |
PRH_ARR_NAME[62]="BUF_CAL_WRITE_FPGA_REG_I241_3" |
| 7172 |
#endif // ifdef I386 |
| 7173 |
|
| 7174 |
// PRH_ARR_PTR[63]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_4; |
| 7175 |
// PRH_ARR_N[63]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I241_4; |
| 7176 |
PRH_ARR_EEPROM_ADDR[63]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I241_4); |
| 7177 |
#ifdef I386 |
| 7178 |
PRH_ARR_NAME[63]="BUF_CAL_WRITE_FPGA_REG_I241_4" |
| 7179 |
#endif // ifdef I386 |
| 7180 |
|
| 7181 |
// PRH_ARR_PTR[64]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_1; |
| 7182 |
// PRH_ARR_N[64]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_1; |
| 7183 |
PRH_ARR_EEPROM_ADDR[64]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_1); |
| 7184 |
#ifdef I386 |
| 7185 |
PRH_ARR_NAME[64]="BUF_CAL_WRITE_FPGA_REG_I251_1" |
| 7186 |
#endif // ifdef I386 |
| 7187 |
|
| 7188 |
// PRH_ARR_PTR[65]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_2; |
| 7189 |
// PRH_ARR_N[65]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_2; |
| 7190 |
PRH_ARR_EEPROM_ADDR[65]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_2); |
| 7191 |
#ifdef I386 |
| 7192 |
PRH_ARR_NAME[65]="BUF_CAL_WRITE_FPGA_REG_I251_2" |
| 7193 |
#endif // ifdef I386 |
| 7194 |
|
| 7195 |
// PRH_ARR_PTR[66]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_3; |
| 7196 |
// PRH_ARR_N[66]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_3; |
| 7197 |
PRH_ARR_EEPROM_ADDR[66]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_3); |
| 7198 |
#ifdef I386 |
| 7199 |
PRH_ARR_NAME[66]="BUF_CAL_WRITE_FPGA_REG_I251_3" |
| 7200 |
#endif // ifdef I386 |
| 7201 |
|
| 7202 |
// PRH_ARR_PTR[67]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_4; |
| 7203 |
// PRH_ARR_N[67]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I251_4; |
| 7204 |
PRH_ARR_EEPROM_ADDR[67]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I251_4); |
| 7205 |
#ifdef I386 |
| 7206 |
PRH_ARR_NAME[67]="BUF_CAL_WRITE_FPGA_REG_I251_4" |
| 7207 |
#endif // ifdef I386 |
| 7208 |
|
| 7209 |
// PRH_ARR_PTR[68]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_1; |
| 7210 |
// PRH_ARR_N[68]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_1; |
| 7211 |
PRH_ARR_EEPROM_ADDR[68]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_1); |
| 7212 |
#ifdef I386 |
| 7213 |
PRH_ARR_NAME[68]="BUF_CAL_WRITE_FPGA_REG_I261_1" |
| 7214 |
#endif // ifdef I386 |
| 7215 |
|
| 7216 |
// PRH_ARR_PTR[69]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_2; |
| 7217 |
// PRH_ARR_N[69]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_2; |
| 7218 |
PRH_ARR_EEPROM_ADDR[69]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_2); |
| 7219 |
#ifdef I386 |
| 7220 |
PRH_ARR_NAME[69]="BUF_CAL_WRITE_FPGA_REG_I261_2" |
| 7221 |
#endif // ifdef I386 |
| 7222 |
|
| 7223 |
// PRH_ARR_PTR[70]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_3; |
| 7224 |
// PRH_ARR_N[70]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_3; |
| 7225 |
PRH_ARR_EEPROM_ADDR[70]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_3); |
| 7226 |
#ifdef I386 |
| 7227 |
PRH_ARR_NAME[70]="BUF_CAL_WRITE_FPGA_REG_I261_3" |
| 7228 |
#endif // ifdef I386 |
| 7229 |
|
| 7230 |
// PRH_ARR_PTR[71]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_4; |
| 7231 |
// PRH_ARR_N[71]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I261_4; |
| 7232 |
PRH_ARR_EEPROM_ADDR[71]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I261_4); |
| 7233 |
#ifdef I386 |
| 7234 |
PRH_ARR_NAME[71]="BUF_CAL_WRITE_FPGA_REG_I261_4" |
| 7235 |
#endif // ifdef I386 |
| 7236 |
|
| 7237 |
// PRH_ARR_PTR[72]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_1; |
| 7238 |
// PRH_ARR_N[72]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_1; |
| 7239 |
PRH_ARR_EEPROM_ADDR[72]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_1); |
| 7240 |
#ifdef I386 |
| 7241 |
PRH_ARR_NAME[72]="BUF_CAL_WRITE_FPGA_REG_I260_1" |
| 7242 |
#endif // ifdef I386 |
| 7243 |
|
| 7244 |
// PRH_ARR_PTR[73]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_2; |
| 7245 |
// PRH_ARR_N[73]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_2; |
| 7246 |
PRH_ARR_EEPROM_ADDR[73]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_2); |
| 7247 |
#ifdef I386 |
| 7248 |
PRH_ARR_NAME[73]="BUF_CAL_WRITE_FPGA_REG_I260_2" |
| 7249 |
#endif // ifdef I386 |
| 7250 |
|
| 7251 |
// PRH_ARR_PTR[74]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_3; |
| 7252 |
// PRH_ARR_N[74]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_3; |
| 7253 |
PRH_ARR_EEPROM_ADDR[74]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_3); |
| 7254 |
#ifdef I386 |
| 7255 |
PRH_ARR_NAME[74]="BUF_CAL_WRITE_FPGA_REG_I260_3" |
| 7256 |
#endif // ifdef I386 |
| 7257 |
|
| 7258 |
// PRH_ARR_PTR[75]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_4; |
| 7259 |
// PRH_ARR_N[75]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I260_4; |
| 7260 |
PRH_ARR_EEPROM_ADDR[75]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I260_4); |
| 7261 |
#ifdef I386 |
| 7262 |
PRH_ARR_NAME[75]="BUF_CAL_WRITE_FPGA_REG_I260_4" |
| 7263 |
#endif // ifdef I386 |
| 7264 |
|
| 7265 |
// PRH_ARR_PTR[76]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_1; |
| 7266 |
// PRH_ARR_N[76]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_1; |
| 7267 |
PRH_ARR_EEPROM_ADDR[76]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_1); |
| 7268 |
#ifdef I386 |
| 7269 |
PRH_ARR_NAME[76]="BUF_CAL_WRITE_FPGA_REG_I311_1" |
| 7270 |
#endif // ifdef I386 |
| 7271 |
|
| 7272 |
// PRH_ARR_PTR[77]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_2; |
| 7273 |
// PRH_ARR_N[77]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_2; |
| 7274 |
PRH_ARR_EEPROM_ADDR[77]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_2); |
| 7275 |
#ifdef I386 |
| 7276 |
PRH_ARR_NAME[77]="BUF_CAL_WRITE_FPGA_REG_I311_2" |
| 7277 |
#endif // ifdef I386 |
| 7278 |
|
| 7279 |
// PRH_ARR_PTR[78]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_3; |
| 7280 |
// PRH_ARR_N[78]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_3; |
| 7281 |
PRH_ARR_EEPROM_ADDR[78]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_3); |
| 7282 |
#ifdef I386 |
| 7283 |
PRH_ARR_NAME[78]="BUF_CAL_WRITE_FPGA_REG_I311_3" |
| 7284 |
#endif // ifdef I386 |
| 7285 |
|
| 7286 |
// PRH_ARR_PTR[79]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_4; |
| 7287 |
// PRH_ARR_N[79]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I311_4; |
| 7288 |
PRH_ARR_EEPROM_ADDR[79]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I311_4); |
| 7289 |
#ifdef I386 |
| 7290 |
PRH_ARR_NAME[79]="BUF_CAL_WRITE_FPGA_REG_I311_4" |
| 7291 |
#endif // ifdef I386 |
| 7292 |
|
| 7293 |
// PRH_ARR_PTR[80]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_1; |
| 7294 |
// PRH_ARR_N[80]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_1; |
| 7295 |
PRH_ARR_EEPROM_ADDR[80]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_1); |
| 7296 |
#ifdef I386 |
| 7297 |
PRH_ARR_NAME[80]="BUF_CAL_WRITE_FPGA_REG_I310_1" |
| 7298 |
#endif // ifdef I386 |
| 7299 |
|
| 7300 |
// PRH_ARR_PTR[81]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_2; |
| 7301 |
// PRH_ARR_N[81]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_2; |
| 7302 |
PRH_ARR_EEPROM_ADDR[81]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_2); |
| 7303 |
#ifdef I386 |
| 7304 |
PRH_ARR_NAME[81]="BUF_CAL_WRITE_FPGA_REG_I310_2" |
| 7305 |
#endif // ifdef I386 |
| 7306 |
|
| 7307 |
// PRH_ARR_PTR[82]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_3; |
| 7308 |
// PRH_ARR_N[82]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_3; |
| 7309 |
PRH_ARR_EEPROM_ADDR[82]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_3); |
| 7310 |
#ifdef I386 |
| 7311 |
PRH_ARR_NAME[82]="BUF_CAL_WRITE_FPGA_REG_I310_3" |
| 7312 |
#endif // ifdef I386 |
| 7313 |
|
| 7314 |
// PRH_ARR_PTR[83]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_4; |
| 7315 |
// PRH_ARR_N[83]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I310_4; |
| 7316 |
PRH_ARR_EEPROM_ADDR[83]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I310_4); |
| 7317 |
#ifdef I386 |
| 7318 |
PRH_ARR_NAME[83]="BUF_CAL_WRITE_FPGA_REG_I310_4" |
| 7319 |
#endif // ifdef I386 |
| 7320 |
|
| 7321 |
// PRH_ARR_PTR[84]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I321; |
| 7322 |
// PRH_ARR_N[84]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I321; |
| 7323 |
PRH_ARR_EEPROM_ADDR[84]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I321); |
| 7324 |
#ifdef I386 |
| 7325 |
PRH_ARR_NAME[84]="BUF_CAL_WRITE_FPGA_REG_I321" |
| 7326 |
#endif // ifdef I386 |
| 7327 |
|
| 7328 |
// PRH_ARR_PTR[85]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_1; |
| 7329 |
// PRH_ARR_N[85]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_1; |
| 7330 |
PRH_ARR_EEPROM_ADDR[85]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_1); |
| 7331 |
#ifdef I386 |
| 7332 |
PRH_ARR_NAME[85]="BUF_CAL_WRITE_FPGA_REG_I331_1" |
| 7333 |
#endif // ifdef I386 |
| 7334 |
|
| 7335 |
// PRH_ARR_PTR[86]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_2; |
| 7336 |
// PRH_ARR_N[86]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_2; |
| 7337 |
PRH_ARR_EEPROM_ADDR[86]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_2); |
| 7338 |
#ifdef I386 |
| 7339 |
PRH_ARR_NAME[86]="BUF_CAL_WRITE_FPGA_REG_I331_2" |
| 7340 |
#endif // ifdef I386 |
| 7341 |
|
| 7342 |
// PRH_ARR_PTR[87]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_3; |
| 7343 |
// PRH_ARR_N[87]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_3; |
| 7344 |
PRH_ARR_EEPROM_ADDR[87]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_3); |
| 7345 |
#ifdef I386 |
| 7346 |
PRH_ARR_NAME[87]="BUF_CAL_WRITE_FPGA_REG_I331_3" |
| 7347 |
#endif // ifdef I386 |
| 7348 |
|
| 7349 |
// PRH_ARR_PTR[88]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_4; |
| 7350 |
// PRH_ARR_N[88]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I331_4; |
| 7351 |
PRH_ARR_EEPROM_ADDR[88]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I331_4); |
| 7352 |
#ifdef I386 |
| 7353 |
PRH_ARR_NAME[88]="BUF_CAL_WRITE_FPGA_REG_I331_4" |
| 7354 |
#endif // ifdef I386 |
| 7355 |
|
| 7356 |
// PRH_ARR_PTR[89]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_OFF; |
| 7357 |
// PRH_ARR_N[89]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_OFF; |
| 7358 |
PRH_ARR_EEPROM_ADDR[89]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_OFF); |
| 7359 |
#ifdef I386 |
| 7360 |
PRH_ARR_NAME[89]="BUF_CAL_WRITE_FPGA_REG_OFF" |
| 7361 |
#endif // ifdef I386 |
| 7362 |
|
| 7363 |
// PRH_ARR_PTR[90]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_1; |
| 7364 |
// PRH_ARR_N[90]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_1; |
| 7365 |
PRH_ARR_EEPROM_ADDR[90]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_1); |
| 7366 |
#ifdef I386 |
| 7367 |
PRH_ARR_NAME[90]="BUF_CAL_WRITE_FPGA_REG_I341_1" |
| 7368 |
#endif // ifdef I386 |
| 7369 |
|
| 7370 |
// PRH_ARR_PTR[91]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_2; |
| 7371 |
// PRH_ARR_N[91]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_2; |
| 7372 |
PRH_ARR_EEPROM_ADDR[91]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_2); |
| 7373 |
#ifdef I386 |
| 7374 |
PRH_ARR_NAME[91]="BUF_CAL_WRITE_FPGA_REG_I341_2" |
| 7375 |
#endif // ifdef I386 |
| 7376 |
|
| 7377 |
// PRH_ARR_PTR[92]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_3; |
| 7378 |
// PRH_ARR_N[92]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_3; |
| 7379 |
PRH_ARR_EEPROM_ADDR[92]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_3); |
| 7380 |
#ifdef I386 |
| 7381 |
PRH_ARR_NAME[92]="BUF_CAL_WRITE_FPGA_REG_I341_3" |
| 7382 |
#endif // ifdef I386 |
| 7383 |
|
| 7384 |
// PRH_ARR_PTR[93]=PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_4; |
| 7385 |
// PRH_ARR_N[93]=PRH_ARR_N_BUF_CAL_WRITE_FPGA_REG_I341_4; |
| 7386 |
PRH_ARR_EEPROM_ADDR[93]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_CAL_WRITE_FPGA_REG_I341_4); |
| 7387 |
#ifdef I386 |
| 7388 |
PRH_ARR_NAME[93]="BUF_CAL_WRITE_FPGA_REG_I341_4" |
| 7389 |
#endif // ifdef I386 |
| 7390 |
|
| 7391 |
// PRH_ARR_PTR[94]=PRH_ARR_BUF_AC_1_SET_DAQ; |
| 7392 |
// PRH_ARR_N[94]=PRH_ARR_N_BUF_AC_1_SET_DAQ; |
| 7393 |
PRH_ARR_EEPROM_ADDR[94]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_1_SET_DAQ); |
| 7394 |
#ifdef I386 |
| 7395 |
PRH_ARR_NAME[94]="BUF_AC_1_SET_DAQ" |
| 7396 |
#endif // ifdef I386 |
| 7397 |
|
| 7398 |
// PRH_ARR_PTR[95]=PRH_ARR_BUF_AC_2_SET_DAQ; |
| 7399 |
// PRH_ARR_N[95]=PRH_ARR_N_BUF_AC_2_SET_DAQ; |
| 7400 |
PRH_ARR_EEPROM_ADDR[95]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_2_SET_DAQ); |
| 7401 |
#ifdef I386 |
| 7402 |
PRH_ARR_NAME[95]="BUF_AC_2_SET_DAQ" |
| 7403 |
#endif // ifdef I386 |
| 7404 |
|
| 7405 |
// PRH_ARR_PTR[96]=PRH_ARR_BUF_AC_SEND_DSP_PROG1; |
| 7406 |
// PRH_ARR_N[96]=PRH_ARR_N_BUF_AC_SEND_DSP_PROG1; |
| 7407 |
PRH_ARR_EEPROM_ADDR[96]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_SEND_DSP_PROG1); |
| 7408 |
#ifdef I386 |
| 7409 |
PRH_ARR_NAME[96]="BUF_AC_SEND_DSP_PROG1" |
| 7410 |
#endif // ifdef I386 |
| 7411 |
|
| 7412 |
// PRH_ARR_PTR[97]=PRH_ARR_BUF_AC_1_SEND_DSP_PROG2; |
| 7413 |
// PRH_ARR_N[97]=PRH_ARR_N_BUF_AC_1_SEND_DSP_PROG2; |
| 7414 |
PRH_ARR_EEPROM_ADDR[97]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_1_SEND_DSP_PROG2); |
| 7415 |
#ifdef I386 |
| 7416 |
PRH_ARR_NAME[97]="BUF_AC_1_SEND_DSP_PROG2" |
| 7417 |
#endif // ifdef I386 |
| 7418 |
|
| 7419 |
// PRH_ARR_PTR[98]=PRH_ARR_BUF_AC_2_SEND_DSP_PROG2; |
| 7420 |
// PRH_ARR_N[98]=PRH_ARR_N_BUF_AC_2_SEND_DSP_PROG2; |
| 7421 |
PRH_ARR_EEPROM_ADDR[98]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_2_SEND_DSP_PROG2); |
| 7422 |
#ifdef I386 |
| 7423 |
PRH_ARR_NAME[98]="BUF_AC_2_SEND_DSP_PROG2" |
| 7424 |
#endif // ifdef I386 |
| 7425 |
|
| 7426 |
// PRH_ARR_PTR[99]=PRH_ARR_BUF_AC_2_WRITE_REG; |
| 7427 |
// PRH_ARR_N[99]=PRH_ARR_N_BUF_AC_2_WRITE_REG; |
| 7428 |
PRH_ARR_EEPROM_ADDR[99]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_2_WRITE_REG); |
| 7429 |
#ifdef I386 |
| 7430 |
PRH_ARR_NAME[99]="BUF_AC_2_WRITE_REG" |
| 7431 |
#endif // ifdef I386 |
| 7432 |
|
| 7433 |
// PRH_ARR_PTR[100]=PRH_ARR_BUF_AC_1_WRITE_REG; |
| 7434 |
// PRH_ARR_N[100]=PRH_ARR_N_BUF_AC_1_WRITE_REG; |
| 7435 |
PRH_ARR_EEPROM_ADDR[100]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_1_WRITE_REG); |
| 7436 |
#ifdef I386 |
| 7437 |
PRH_ARR_NAME[100]="BUF_AC_1_WRITE_REG" |
| 7438 |
#endif // ifdef I386 |
| 7439 |
|
| 7440 |
// PRH_ARR_PTR[101]=PRH_ARR_BUF_AC_READ_DSP_MEM; |
| 7441 |
// PRH_ARR_N[101]=PRH_ARR_N_BUF_AC_READ_DSP_MEM; |
| 7442 |
PRH_ARR_EEPROM_ADDR[101]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_AC_READ_DSP_MEM); |
| 7443 |
#ifdef I386 |
| 7444 |
PRH_ARR_NAME[101]="BUF_AC_READ_DSP_MEM" |
| 7445 |
#endif // ifdef I386 |
| 7446 |
|
| 7447 |
// PRH_ARR_PTR[102]=PRH_ARR_BUF_TOF_WRITE_PMT_THR_1; |
| 7448 |
// PRH_ARR_N[102]=PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_1; |
| 7449 |
PRH_ARR_EEPROM_ADDR[102]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TOF_WRITE_PMT_THR_1); |
| 7450 |
#ifdef I386 |
| 7451 |
PRH_ARR_NAME[102]="BUF_TOF_WRITE_PMT_THR_1" |
| 7452 |
#endif // ifdef I386 |
| 7453 |
|
| 7454 |
// PRH_ARR_PTR[103]=PRH_ARR_BUF_TOF_WRITE_PMT_THR_2; |
| 7455 |
// PRH_ARR_N[103]=PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_2; |
| 7456 |
PRH_ARR_EEPROM_ADDR[103]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TOF_WRITE_PMT_THR_2); |
| 7457 |
#ifdef I386 |
| 7458 |
PRH_ARR_NAME[103]="BUF_TOF_WRITE_PMT_THR_2" |
| 7459 |
#endif // ifdef I386 |
| 7460 |
|
| 7461 |
// PRH_ARR_PTR[104]=PRH_ARR_BUF_TOF_WRITE_PMT_THR_3; |
| 7462 |
// PRH_ARR_N[104]=PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_3; |
| 7463 |
PRH_ARR_EEPROM_ADDR[104]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TOF_WRITE_PMT_THR_3); |
| 7464 |
#ifdef I386 |
| 7465 |
PRH_ARR_NAME[104]="BUF_TOF_WRITE_PMT_THR_3" |
| 7466 |
#endif // ifdef I386 |
| 7467 |
|
| 7468 |
// PRH_ARR_PTR[105]=PRH_ARR_BUF_TOF_WRITE_PMT_THR_4; |
| 7469 |
// PRH_ARR_N[105]=PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_4; |
| 7470 |
PRH_ARR_EEPROM_ADDR[105]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TOF_WRITE_PMT_THR_4); |
| 7471 |
#ifdef I386 |
| 7472 |
PRH_ARR_NAME[105]="BUF_TOF_WRITE_PMT_THR_4" |
| 7473 |
#endif // ifdef I386 |
| 7474 |
|
| 7475 |
// PRH_ARR_PTR[106]=PRH_ARR_BUF_TOF_WRITE_PMT_THR_5; |
| 7476 |
// PRH_ARR_N[106]=PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_5; |
| 7477 |
PRH_ARR_EEPROM_ADDR[106]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TOF_WRITE_PMT_THR_5); |
| 7478 |
#ifdef I386 |
| 7479 |
PRH_ARR_NAME[106]="BUF_TOF_WRITE_PMT_THR_5" |
| 7480 |
#endif // ifdef I386 |
| 7481 |
|
| 7482 |
// PRH_ARR_PTR[107]=PRH_ARR_BUF_TOF_WRITE_PMT_THR_6; |
| 7483 |
// PRH_ARR_N[107]=PRH_ARR_N_BUF_TOF_WRITE_PMT_THR_6; |
| 7484 |
PRH_ARR_EEPROM_ADDR[107]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_BUF_TOF_WRITE_PMT_THR_6); |
| 7485 |
#ifdef I386 |
| 7486 |
PRH_ARR_NAME[107]="BUF_TOF_WRITE_PMT_THR_6" |
| 7487 |
#endif // ifdef I386 |
| 7488 |
|
| 7489 |
// PRH_ARR_PTR[108]=PRH_ARR_TOF_PLAN; |
| 7490 |
// PRH_ARR_N[108]=PRH_ARR_N_TOF_PLAN; |
| 7491 |
PRH_ARR_EEPROM_ADDR[108]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_TOF_PLAN); |
| 7492 |
#ifdef I386 |
| 7493 |
PRH_ARR_NAME[108]="TOF_PLAN" |
| 7494 |
#endif // ifdef I386 |
| 7495 |
|
| 7496 |
// PRH_ARR_PTR[109]=PRH_ARR_PM_PERIODIC_DELAY; |
| 7497 |
// PRH_ARR_N[109]=PRH_ARR_N_PM_PERIODIC_DELAY; |
| 7498 |
PRH_ARR_EEPROM_ADDR[109]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PM_PERIODIC_DELAY); |
| 7499 |
#ifdef I386 |
| 7500 |
PRH_ARR_NAME[109]="PM_PERIODIC_DELAY" |
| 7501 |
#endif // ifdef I386 |
| 7502 |
|
| 7503 |
// PRH_ARR_PTR[110]=PRH_ARR_PSB_COMMANDS; |
| 7504 |
// PRH_ARR_N[110]=PRH_ARR_N_PSB_COMMANDS; |
| 7505 |
PRH_ARR_EEPROM_ADDR[110]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PSB_COMMANDS); |
| 7506 |
#ifdef I386 |
| 7507 |
PRH_ARR_NAME[110]="PSB_COMMANDS" |
| 7508 |
#endif // ifdef I386 |
| 7509 |
|
| 7510 |
// PRH_ARR_PTR[111]=PRH_ARR_PSB_CALO_FE_ON; |
| 7511 |
// PRH_ARR_N[111]=PRH_ARR_N_PSB_CALO_FE_ON; |
| 7512 |
PRH_ARR_EEPROM_ADDR[111]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PSB_CALO_FE_ON); |
| 7513 |
#ifdef I386 |
| 7514 |
PRH_ARR_NAME[111]="PSB_CALO_FE_ON" |
| 7515 |
#endif // ifdef I386 |
| 7516 |
|
| 7517 |
// PRH_ARR_PTR[112]=PRH_ARR_PSB_CALO_FE_OFF; |
| 7518 |
// PRH_ARR_N[112]=PRH_ARR_N_PSB_CALO_FE_OFF; |
| 7519 |
PRH_ARR_EEPROM_ADDR[112]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PSB_CALO_FE_OFF); |
| 7520 |
#ifdef I386 |
| 7521 |
PRH_ARR_NAME[112]="PSB_CALO_FE_OFF" |
| 7522 |
#endif // ifdef I386 |
| 7523 |
|
| 7524 |
// PRH_ARR_PTR[113]=PRH_ARR_PSB_CALO_FE; |
| 7525 |
// PRH_ARR_N[113]=PRH_ARR_N_PSB_CALO_FE; |
| 7526 |
PRH_ARR_EEPROM_ADDR[113]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_PSB_CALO_FE); |
| 7527 |
#ifdef I386 |
| 7528 |
PRH_ARR_NAME[113]="PSB_CALO_FE" |
| 7529 |
#endif // ifdef I386 |
| 7530 |
|
| 7531 |
// PRH_ARR_PTR[114]=PRH_ARR_HVB_COMMANDS; |
| 7532 |
// PRH_ARR_N[114]=PRH_ARR_N_HVB_COMMANDS; |
| 7533 |
PRH_ARR_EEPROM_ADDR[114]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_HVB_COMMANDS); |
| 7534 |
#ifdef I386 |
| 7535 |
PRH_ARR_NAME[114]="HVB_COMMANDS" |
| 7536 |
#endif // ifdef I386 |
| 7537 |
|
| 7538 |
// PRH_ARR_PTR[115]=PRH_ARR_TSB_BOARD_OK; |
| 7539 |
// PRH_ARR_N[115]=PRH_ARR_N_TSB_BOARD_OK; |
| 7540 |
PRH_ARR_EEPROM_ADDR[115]=prec_eeprom; prec_eeprom+=sizeof(PRH_ARR_TSB_BOARD_OK); |
| 7541 |
#ifdef I386 |
| 7542 |
PRH_ARR_NAME[115]="TSB_BOARD_OK" |
| 7543 |
#endif // ifdef I386 |
| 7544 |
|
| 7545 |
// init PTR look-up for TABLEs: |
| 7546 |
|
| 7547 |
|
| 7548 |
// PRH_TAB_PTR[0]=(PRH_VAR_TYPE *)PRH_TAB_CONF; |
| 7549 |
// PRH_TAB_NCOL[0]=PRH_TAB_NCOL_CONF; |
| 7550 |
// PRH_TAB_NROW[0]=PRH_TAB_NROW_CONF; |
| 7551 |
PRH_TAB_EEPROM_ADDR[0]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_CONF); |
| 7552 |
#ifdef I386 |
| 7553 |
PRH_TAB_NAME[0]="CONF" |
| 7554 |
#endif // ifdef I386 |
| 7555 |
|
| 7556 |
// PRH_TAB_PTR[1]=(PRH_VAR_TYPE *)PRH_TAB_PWR_IPM_ACTION; |
| 7557 |
// PRH_TAB_NCOL[1]=PRH_TAB_NCOL_PWR_IPM_ACTION; |
| 7558 |
// PRH_TAB_NROW[1]=PRH_TAB_NROW_PWR_IPM_ACTION; |
| 7559 |
PRH_TAB_EEPROM_ADDR[1]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_PWR_IPM_ACTION); |
| 7560 |
#ifdef I386 |
| 7561 |
PRH_TAB_NAME[1]="PWR_IPM_ACTION" |
| 7562 |
#endif // ifdef I386 |
| 7563 |
|
| 7564 |
// PRH_TAB_PTR[2]=(PRH_VAR_TYPE *)PRH_TAB_TRK_DSP_OK; |
| 7565 |
// PRH_TAB_NCOL[2]=PRH_TAB_NCOL_TRK_DSP_OK; |
| 7566 |
// PRH_TAB_NROW[2]=PRH_TAB_NROW_TRK_DSP_OK; |
| 7567 |
PRH_TAB_EEPROM_ADDR[2]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_DSP_OK); |
| 7568 |
#ifdef I386 |
| 7569 |
PRH_TAB_NAME[2]="TRK_DSP_OK" |
| 7570 |
#endif // ifdef I386 |
| 7571 |
|
| 7572 |
// PRH_TAB_PTR[3]=(PRH_VAR_TYPE *)PRH_TAB_TRK_DSP_MASK; |
| 7573 |
// PRH_TAB_NCOL[3]=PRH_TAB_NCOL_TRK_DSP_MASK; |
| 7574 |
// PRH_TAB_NROW[3]=PRH_TAB_NROW_TRK_DSP_MASK; |
| 7575 |
PRH_TAB_EEPROM_ADDR[3]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_DSP_MASK); |
| 7576 |
#ifdef I386 |
| 7577 |
PRH_TAB_NAME[3]="TRK_DSP_MASK" |
| 7578 |
#endif // ifdef I386 |
| 7579 |
|
| 7580 |
// PRH_TAB_PTR[4]=(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MIN_0; |
| 7581 |
// PRH_TAB_NCOL[4]=PRH_TAB_NCOL_TRK_PED_MIN_0; |
| 7582 |
// PRH_TAB_NROW[4]=PRH_TAB_NROW_TRK_PED_MIN_0; |
| 7583 |
PRH_TAB_EEPROM_ADDR[4]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_PED_MIN_0); |
| 7584 |
#ifdef I386 |
| 7585 |
PRH_TAB_NAME[4]="TRK_PED_MIN_0" |
| 7586 |
#endif // ifdef I386 |
| 7587 |
|
| 7588 |
// PRH_TAB_PTR[5]=(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MIN_1; |
| 7589 |
// PRH_TAB_NCOL[5]=PRH_TAB_NCOL_TRK_PED_MIN_1; |
| 7590 |
// PRH_TAB_NROW[5]=PRH_TAB_NROW_TRK_PED_MIN_1; |
| 7591 |
PRH_TAB_EEPROM_ADDR[5]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_PED_MIN_1); |
| 7592 |
#ifdef I386 |
| 7593 |
PRH_TAB_NAME[5]="TRK_PED_MIN_1" |
| 7594 |
#endif // ifdef I386 |
| 7595 |
|
| 7596 |
// PRH_TAB_PTR[6]=(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MAX_0; |
| 7597 |
// PRH_TAB_NCOL[6]=PRH_TAB_NCOL_TRK_PED_MAX_0; |
| 7598 |
// PRH_TAB_NROW[6]=PRH_TAB_NROW_TRK_PED_MAX_0; |
| 7599 |
PRH_TAB_EEPROM_ADDR[6]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_PED_MAX_0); |
| 7600 |
#ifdef I386 |
| 7601 |
PRH_TAB_NAME[6]="TRK_PED_MAX_0" |
| 7602 |
#endif // ifdef I386 |
| 7603 |
|
| 7604 |
// PRH_TAB_PTR[7]=(PRH_VAR_TYPE *)PRH_TAB_TRK_PED_MAX_1; |
| 7605 |
// PRH_TAB_NCOL[7]=PRH_TAB_NCOL_TRK_PED_MAX_1; |
| 7606 |
// PRH_TAB_NROW[7]=PRH_TAB_NROW_TRK_PED_MAX_1; |
| 7607 |
PRH_TAB_EEPROM_ADDR[7]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_PED_MAX_1); |
| 7608 |
#ifdef I386 |
| 7609 |
PRH_TAB_NAME[7]="TRK_PED_MAX_1" |
| 7610 |
#endif // ifdef I386 |
| 7611 |
|
| 7612 |
// PRH_TAB_PTR[8]=(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MIN_0; |
| 7613 |
// PRH_TAB_NCOL[8]=PRH_TAB_NCOL_TRK_SIG_MIN_0; |
| 7614 |
// PRH_TAB_NROW[8]=PRH_TAB_NROW_TRK_SIG_MIN_0; |
| 7615 |
PRH_TAB_EEPROM_ADDR[8]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_SIG_MIN_0); |
| 7616 |
#ifdef I386 |
| 7617 |
PRH_TAB_NAME[8]="TRK_SIG_MIN_0" |
| 7618 |
#endif // ifdef I386 |
| 7619 |
|
| 7620 |
// PRH_TAB_PTR[9]=(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MIN_1; |
| 7621 |
// PRH_TAB_NCOL[9]=PRH_TAB_NCOL_TRK_SIG_MIN_1; |
| 7622 |
// PRH_TAB_NROW[9]=PRH_TAB_NROW_TRK_SIG_MIN_1; |
| 7623 |
PRH_TAB_EEPROM_ADDR[9]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_SIG_MIN_1); |
| 7624 |
#ifdef I386 |
| 7625 |
PRH_TAB_NAME[9]="TRK_SIG_MIN_1" |
| 7626 |
#endif // ifdef I386 |
| 7627 |
|
| 7628 |
// PRH_TAB_PTR[10]=(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MAX_0; |
| 7629 |
// PRH_TAB_NCOL[10]=PRH_TAB_NCOL_TRK_SIG_MAX_0; |
| 7630 |
// PRH_TAB_NROW[10]=PRH_TAB_NROW_TRK_SIG_MAX_0; |
| 7631 |
PRH_TAB_EEPROM_ADDR[10]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_SIG_MAX_0); |
| 7632 |
#ifdef I386 |
| 7633 |
PRH_TAB_NAME[10]="TRK_SIG_MAX_0" |
| 7634 |
#endif // ifdef I386 |
| 7635 |
|
| 7636 |
// PRH_TAB_PTR[11]=(PRH_VAR_TYPE *)PRH_TAB_TRK_SIG_MAX_1; |
| 7637 |
// PRH_TAB_NCOL[11]=PRH_TAB_NCOL_TRK_SIG_MAX_1; |
| 7638 |
// PRH_TAB_NROW[11]=PRH_TAB_NROW_TRK_SIG_MAX_1; |
| 7639 |
PRH_TAB_EEPROM_ADDR[11]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_SIG_MAX_1); |
| 7640 |
#ifdef I386 |
| 7641 |
PRH_TAB_NAME[11]="TRK_SIG_MAX_1" |
| 7642 |
#endif // ifdef I386 |
| 7643 |
|
| 7644 |
// PRH_TAB_PTR[12]=(PRH_VAR_TYPE *)PRH_TAB_TRK_BAD_MAX_0; |
| 7645 |
// PRH_TAB_NCOL[12]=PRH_TAB_NCOL_TRK_BAD_MAX_0; |
| 7646 |
// PRH_TAB_NROW[12]=PRH_TAB_NROW_TRK_BAD_MAX_0; |
| 7647 |
PRH_TAB_EEPROM_ADDR[12]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_BAD_MAX_0); |
| 7648 |
#ifdef I386 |
| 7649 |
PRH_TAB_NAME[12]="TRK_BAD_MAX_0" |
| 7650 |
#endif // ifdef I386 |
| 7651 |
|
| 7652 |
// PRH_TAB_PTR[13]=(PRH_VAR_TYPE *)PRH_TAB_TRK_BAD_MAX_1; |
| 7653 |
// PRH_TAB_NCOL[13]=PRH_TAB_NCOL_TRK_BAD_MAX_1; |
| 7654 |
// PRH_TAB_NROW[13]=PRH_TAB_NROW_TRK_BAD_MAX_1; |
| 7655 |
PRH_TAB_EEPROM_ADDR[13]=prec_eeprom; prec_eeprom+=sizeof(PRH_TAB_TRK_BAD_MAX_1); |
| 7656 |
#ifdef I386 |
| 7657 |
PRH_TAB_NAME[13]="TRK_BAD_MAX_1" |
| 7658 |
#endif // ifdef I386 |
| 7659 |
|
| 7660 |
|
| 7661 |
PRH_var_dump_len=0; |
| 7662 |
for(i=0;i<PRH_VAR_MAX;i++) { |
| 7663 |
if(PRH_int_var_is_in_mm(i,&mm) == CM_RC_SUCCESSFUL && |
| 7664 |
mm) |
| 7665 |
PRH_var_dump_len+=PRH_SIZEOF_VAR + 1 /* id */; |
| 7666 |
} |
| 7667 |
PRH_arr_dump_len=0; |
| 7668 |
for(i=0;i<PRH_ARR_MAX;i++) { |
| 7669 |
if(PRH_int_arr_is_in_mm(i,&mm) == CM_RC_SUCCESSFUL && |
| 7670 |
mm && |
| 7671 |
PRH_SIZEOF_ARR(i,&size)==CM_RC_SUCCESSFUL) |
| 7672 |
PRH_arr_dump_len+=1 /* id */ +2 /* len */ + size ; |
| 7673 |
} |
| 7674 |
PRH_tab_dump_len=0; |
| 7675 |
for(i=0;i<PRH_TAB_MAX;i++) { |
| 7676 |
if(PRH_int_tab_is_in_mm(i,&mm) == CM_RC_SUCCESSFUL && |
| 7677 |
mm && |
| 7678 |
PRH_SIZEOF_TABLE(i,&size)==CM_RC_SUCCESSFUL) |
| 7679 |
PRH_tab_dump_len+=1 /* id */ +1 /* row */ + 1 /* col */ + size ; |
| 7680 |
} |
| 7681 |
} |
| 7682 |
|
| 7683 |
static BOOL PRH_automatic_log = FALSE; |
| 7684 |
|
| 7685 |
|
| 7686 |
|
| 7687 |
/* these functions (set_XXX_all_to_default) |
| 7688 |
must be invoked before the pamela software starts and after array_and_table_init |
| 7689 |
they can be also invoked at any time to set the all values to the default values |
| 7690 |
*/ |
| 7691 |
status_code PRH_int_set_var_default(unsigned int i) { |
| 7692 |
|
| 7693 |
return PRH_int_var_read_eeprom(PRH_EEPROM_DEFAULT,i); |
| 7694 |
} |
| 7695 |
status_code PRH_int_set_arr_default(unsigned int i) { |
| 7696 |
|
| 7697 |
return PRH_int_arr_read_eeprom(PRH_EEPROM_DEFAULT,i); |
| 7698 |
} |
| 7699 |
status_code PRH_int_set_tab_default(unsigned int i) { |
| 7700 |
|
| 7701 |
return PRH_int_tab_read_eeprom(PRH_EEPROM_DEFAULT,i); |
| 7702 |
} |
| 7703 |
status_code PRH_int_set_var_all_to_default() { |
| 7704 |
|
| 7705 |
unsigned int i=0; |
| 7706 |
status_code status = 0; |
| 7707 |
for(;(i<PRH_VAR_MAX) && (status == 0);i++) |
| 7708 |
status = PRH_int_set_var_default(i); |
| 7709 |
return status; |
| 7710 |
} |
| 7711 |
status_code PRH_int_set_arr_all_to_default() { |
| 7712 |
|
| 7713 |
unsigned int i=0; |
| 7714 |
status_code status = 0; |
| 7715 |
for(;(i<PRH_ARR_MAX) && (status == 0);i++) |
| 7716 |
status = PRH_int_set_arr_default(i); |
| 7717 |
return status; |
| 7718 |
} |
| 7719 |
status_code PRH_int_set_tab_all_to_default() { |
| 7720 |
|
| 7721 |
unsigned int i=0; |
| 7722 |
status_code status = 0; |
| 7723 |
for(;(i<PRH_TAB_MAX) && (status == 0);i++) |
| 7724 |
status = PRH_int_set_tab_default(i); |
| 7725 |
return status; |
| 7726 |
} |
| 7727 |
void PRH_int_set_automatic_log(BOOL flag) { |
| 7728 |
|
| 7729 |
PRH_automatic_log = flag; |
| 7730 |
} |
| 7731 |
BOOL PRH_int_get_automatic_log() { |
| 7732 |
|
| 7733 |
return PRH_automatic_log; |
| 7734 |
} |
| 7735 |
static status_code PRH_int_log_error(CM_RETURN_CODE errcode,unsigned int info,unsigned int fileid,unsigned int line) { |
| 7736 |
|
| 7737 |
#ifdef I386 |
| 7738 |
fprintf(stderr," ERROR! errocode:%d info:%d",errcode,info); |
| 7739 |
#else |
| 7740 |
if(PRH_automatic_log) { |
| 7741 |
LU_INFN_LOG(LU_INTERNAL,LU_MASK(fileid),fileid,line,errcode); |
| 7742 |
LU_INFN_LOG(LU_INTERNAL,LU_MASK(fileid),fileid,line,info); |
| 7743 |
} |
| 7744 |
#endif // I386 |
| 7745 |
return errcode; |
| 7746 |
} |
| 7747 |
status_code PRH_SIZEOF_ARR(unsigned int id,unsigned int *size) { |
| 7748 |
|
| 7749 |
if(id >= PRH_ARR_MAX) |
| 7750 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 7751 |
*size = PRH_ARR_N[(id)]*PRH_SIZEOF_VAR; |
| 7752 |
return CM_RC_SUCCESSFUL; |
| 7753 |
} |
| 7754 |
status_code PRH_SIZEOF_TABLE(unsigned int id,unsigned int *size) { |
| 7755 |
|
| 7756 |
if(id >= PRH_TAB_MAX) |
| 7757 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7758 |
*size = PRH_TAB_NROW[id]*PRH_TAB_NCOL[id]*PRH_SIZEOF_VAR; |
| 7759 |
return CM_RC_SUCCESSFUL; |
| 7760 |
} |
| 7761 |
status_code PRH_int_set_var(unsigned int id,PRH_VAR_TYPE value) { |
| 7762 |
|
| 7763 |
UINT32 level; |
| 7764 |
if(id >= PRH_VAR_MAX) |
| 7765 |
return PRH_int_log_error(CM_RC_INVALID_VARID,id,__FILEID__,__LINE__); |
| 7766 |
OS_piInterDisable(&level); |
| 7767 |
*PRH_VAR_PTR[id]=value; |
| 7768 |
OS_piInterEnable(level); |
| 7769 |
return CM_RC_SUCCESSFUL; |
| 7770 |
} |
| 7771 |
status_code PRH_int_get_var(unsigned int id,PRH_VAR_TYPE* val) { |
| 7772 |
|
| 7773 |
UINT32 level; |
| 7774 |
if(id >= PRH_VAR_MAX) |
| 7775 |
return PRH_int_log_error(CM_RC_INVALID_VARID,id,__FILEID__,__LINE__); |
| 7776 |
OS_piInterDisable(&level); |
| 7777 |
*val=*PRH_VAR_PTR[id]; |
| 7778 |
OS_piInterEnable(level); |
| 7779 |
return CM_RC_SUCCESSFUL; |
| 7780 |
} |
| 7781 |
status_code PRH_int_set_arr(unsigned int id,unsigned int idx,PRH_VAR_TYPE value) { |
| 7782 |
|
| 7783 |
UINT32 level; |
| 7784 |
if(id >= PRH_ARR_MAX) |
| 7785 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 7786 |
if(idx >= PRH_ARR_N[id]) |
| 7787 |
return PRH_int_log_error(CM_RC_INVALID_ARRIDX,idx,__FILEID__,__LINE__); |
| 7788 |
OS_piInterDisable(&level); |
| 7789 |
(PRH_ARR_PTR[id])[idx]=value; |
| 7790 |
OS_piInterEnable(level); |
| 7791 |
return CM_RC_SUCCESSFUL; |
| 7792 |
} |
| 7793 |
status_code PRH_int_set_arr_raw(unsigned int id,void *p) { |
| 7794 |
|
| 7795 |
unsigned int size; |
| 7796 |
UINT32 level; |
| 7797 |
if(id >= PRH_ARR_MAX) |
| 7798 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 7799 |
PRH_SIZEOF_ARR(id,&size); |
| 7800 |
OS_piInterDisable(&level); |
| 7801 |
memcpy(PRH_ARR_PTR[id],p,size); |
| 7802 |
OS_piInterEnable(level); |
| 7803 |
return CM_RC_SUCCESSFUL; |
| 7804 |
} |
| 7805 |
status_code PRH_int_get_arr_raw(unsigned int id,void *p) { |
| 7806 |
|
| 7807 |
unsigned int size; |
| 7808 |
UINT32 level; |
| 7809 |
if(id >= PRH_ARR_MAX) |
| 7810 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 7811 |
PRH_SIZEOF_ARR(id,&size); |
| 7812 |
OS_piInterDisable(&level); |
| 7813 |
memcpy(p,PRH_ARR_PTR[id],size); |
| 7814 |
OS_piInterEnable(level); |
| 7815 |
return CM_RC_SUCCESSFUL; |
| 7816 |
} |
| 7817 |
status_code PRH_int_get_arr(unsigned int id,unsigned int idx,PRH_VAR_TYPE* val) { |
| 7818 |
|
| 7819 |
UINT32 level; |
| 7820 |
if(id >= PRH_ARR_MAX) |
| 7821 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 7822 |
if(idx >= PRH_ARR_N[id]) |
| 7823 |
return PRH_int_log_error(CM_RC_INVALID_ARRIDX,idx,__FILEID__,__LINE__); |
| 7824 |
OS_piInterDisable(&level); |
| 7825 |
*val=(PRH_ARR_PTR[id])[idx]; |
| 7826 |
OS_piInterEnable(level); |
| 7827 |
return CM_RC_SUCCESSFUL; |
| 7828 |
} |
| 7829 |
status_code PRH_int_get_arr_ptr(unsigned int id,PRH_VAR_TYPE **p) { |
| 7830 |
|
| 7831 |
if(id >= PRH_ARR_MAX) |
| 7832 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 7833 |
*p=PRH_ARR_PTR[id]; |
| 7834 |
return CM_RC_SUCCESSFUL; |
| 7835 |
} |
| 7836 |
status_code PRH_int_set_tab(unsigned int id,unsigned int r,unsigned int c,PRH_VAR_TYPE value) { |
| 7837 |
|
| 7838 |
UINT32 level; |
| 7839 |
if(id >= PRH_TAB_MAX) |
| 7840 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7841 |
if(r >= PRH_TAB_NROW[id]) |
| 7842 |
return PRH_int_log_error(CM_RC_INVALID_TABROW,r,__FILEID__,__LINE__); |
| 7843 |
if(c >= PRH_TAB_NCOL[id]) |
| 7844 |
return PRH_int_log_error(CM_RC_INVALID_TABROW,c,__FILEID__,__LINE__); |
| 7845 |
OS_piInterDisable(&level); |
| 7846 |
(PRH_TAB_PTR[id])[r*PRH_TAB_NCOL[id]+c]=value; |
| 7847 |
OS_piInterEnable(level); |
| 7848 |
return CM_RC_SUCCESSFUL; |
| 7849 |
} |
| 7850 |
|
| 7851 |
status_code PRH_int_set_tab_raw(unsigned int id,void *p) { |
| 7852 |
|
| 7853 |
UINT32 level; |
| 7854 |
unsigned int size; |
| 7855 |
if(id >= PRH_TAB_MAX) |
| 7856 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7857 |
PRH_SIZEOF_TABLE(id,&size); |
| 7858 |
OS_piInterDisable(&level); |
| 7859 |
memcpy(PRH_TAB_PTR[id],p,size); |
| 7860 |
OS_piInterEnable(level); |
| 7861 |
return CM_RC_SUCCESSFUL; |
| 7862 |
} |
| 7863 |
|
| 7864 |
status_code PRH_int_get_tab_raw(unsigned int id,void *p) { |
| 7865 |
|
| 7866 |
unsigned int size; |
| 7867 |
UINT32 level; |
| 7868 |
if(id >= PRH_TAB_MAX) |
| 7869 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7870 |
PRH_SIZEOF_TABLE(id,&size); |
| 7871 |
OS_piInterDisable(&level); |
| 7872 |
memcpy(p,PRH_TAB_PTR[id],size); |
| 7873 |
OS_piInterEnable(level); |
| 7874 |
return CM_RC_SUCCESSFUL; |
| 7875 |
} |
| 7876 |
|
| 7877 |
status_code PRH_int_get_tab(unsigned int id,unsigned int r,unsigned int c,PRH_VAR_TYPE *val) { |
| 7878 |
|
| 7879 |
UINT32 level; |
| 7880 |
if(id >= PRH_TAB_MAX) |
| 7881 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7882 |
if(r >= PRH_TAB_NROW[id]) |
| 7883 |
return PRH_int_log_error(CM_RC_INVALID_TABROW,r,__FILEID__,__LINE__); |
| 7884 |
if(c >= PRH_TAB_NCOL[id]) |
| 7885 |
return PRH_int_log_error(CM_RC_INVALID_TABCOL,c,__FILEID__,__LINE__); |
| 7886 |
OS_piInterDisable(&level); |
| 7887 |
*val=(PRH_TAB_PTR[id])[r*PRH_TAB_NCOL[id]+c]; |
| 7888 |
OS_piInterEnable(level); |
| 7889 |
return CM_RC_SUCCESSFUL; |
| 7890 |
} |
| 7891 |
|
| 7892 |
status_code PRH_int_get_tab_ptr(unsigned int id,PRH_VAR_TYPE **p) { |
| 7893 |
|
| 7894 |
if(id >= PRH_TAB_MAX) |
| 7895 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7896 |
*p=PRH_TAB_PTR[id]; |
| 7897 |
return CM_RC_SUCCESSFUL; |
| 7898 |
} |
| 7899 |
|
| 7900 |
status_code PRH_int_get_var_eeprom_address(PRH_EEPROM_REGION region,unsigned int id,PRH_VAR_TYPE** addr) { |
| 7901 |
|
| 7902 |
if(id >= PRH_VAR_MAX) |
| 7903 |
return PRH_int_log_error(CM_RC_INVALID_VARID,id,__FILEID__,__LINE__); |
| 7904 |
if(PRH_VAR_EEPROM_ADDR[id] == PRH_EEPROM_NO_STORED) |
| 7905 |
*addr=(PRH_VAR_TYPE*)PRH_EEPROM_NO_STORED; |
| 7906 |
else |
| 7907 |
*addr=(PRH_VAR_TYPE*) (PRH_VAR_EEPROM_ADDR[id]+region); |
| 7908 |
return CM_RC_SUCCESSFUL; |
| 7909 |
} |
| 7910 |
status_code PRH_int_get_arr_eeprom_address(PRH_EEPROM_REGION region,unsigned int id,PRH_VAR_TYPE** addr) { |
| 7911 |
|
| 7912 |
if(id >= PRH_ARR_MAX) |
| 7913 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 7914 |
if(PRH_ARR_EEPROM_ADDR[id] == PRH_EEPROM_NO_STORED) |
| 7915 |
*addr=(PRH_VAR_TYPE*)PRH_EEPROM_NO_STORED; |
| 7916 |
else |
| 7917 |
*addr=(PRH_VAR_TYPE*) (PRH_ARR_EEPROM_ADDR[id]+region); |
| 7918 |
return CM_RC_SUCCESSFUL; |
| 7919 |
} |
| 7920 |
status_code PRH_int_get_tab_eeprom_address(PRH_EEPROM_REGION region,unsigned int id,PRH_VAR_TYPE** addr) { |
| 7921 |
|
| 7922 |
if(id >= PRH_TAB_MAX) |
| 7923 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7924 |
if(PRH_TAB_EEPROM_ADDR[id] == PRH_EEPROM_NO_STORED) |
| 7925 |
*addr=(PRH_VAR_TYPE*)PRH_EEPROM_NO_STORED; |
| 7926 |
else |
| 7927 |
*addr=(PRH_VAR_TYPE*) (PRH_TAB_EEPROM_ADDR[id]+region); |
| 7928 |
return CM_RC_SUCCESSFUL; |
| 7929 |
} |
| 7930 |
status_code PRH_int_write_eeprom_and_check(UINT32 *peeprom,UINT32 *pram,UINT16 n_dword) { |
| 7931 |
|
| 7932 |
UINT16 i; |
| 7933 |
PD_ifEEPROMWrite(peeprom,pram,n_dword); |
| 7934 |
for(i=0;i<n_dword;i++) |
| 7935 |
if( *(peeprom+i) != *(pram+i)) |
| 7936 |
return CM_RC_WRITE_EEPROM_ERROR; |
| 7937 |
return CM_RC_SUCCESSFUL; |
| 7938 |
} |
| 7939 |
status_code PRH_int_get_arr_n(unsigned int id,UINT32 *n) { |
| 7940 |
|
| 7941 |
if(id >= PRH_ARR_MAX) |
| 7942 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7943 |
*n= PRH_ARR_N[id]; |
| 7944 |
return CM_RC_SUCCESSFUL; |
| 7945 |
} |
| 7946 |
status_code PRH_int_get_tab_dim(unsigned int id,UINT32 *nrow,UINT32 *ncol) { |
| 7947 |
|
| 7948 |
if(id >= PRH_TAB_MAX) |
| 7949 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7950 |
*ncol= PRH_TAB_NCOL[id]; |
| 7951 |
*nrow= PRH_TAB_NROW[id]; |
| 7952 |
return CM_RC_SUCCESSFUL; |
| 7953 |
} |
| 7954 |
status_code PRH_int_var_is_in_mm(unsigned int id,BOOL *mm) { |
| 7955 |
|
| 7956 |
if(id >= PRH_VAR_MAX) |
| 7957 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7958 |
*mm=PRH_VAR_MM_FLAG[id]; |
| 7959 |
/* actually always return true */ |
| 7960 |
// *mm = TRUE; |
| 7961 |
return CM_RC_SUCCESSFUL; |
| 7962 |
} |
| 7963 |
status_code PRH_int_arr_is_in_mm(unsigned int id,BOOL *mm) { |
| 7964 |
|
| 7965 |
if(id >= PRH_ARR_MAX) |
| 7966 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7967 |
*mm=PRH_ARR_MM_FLAG[id]; |
| 7968 |
return CM_RC_SUCCESSFUL; |
| 7969 |
} |
| 7970 |
status_code PRH_int_tab_is_in_mm(unsigned int id,BOOL *mm) { |
| 7971 |
|
| 7972 |
if(id >= PRH_TAB_MAX) |
| 7973 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 7974 |
*mm=PRH_TAB_MM_FLAG[id]; |
| 7975 |
return CM_RC_SUCCESSFUL; |
| 7976 |
} |
| 7977 |
|
| 7978 |
#ifndef I386 |
| 7979 |
status_code PRH_int_var_write2eeprom(PRH_EEPROM_REGION region,unsigned int id) { |
| 7980 |
|
| 7981 |
PRH_VAR_TYPE* p; |
| 7982 |
status_code s=PRH_int_get_var_eeprom_address(region,id,&p); |
| 7983 |
if(s == CM_RC_SUCCESSFUL) { |
| 7984 |
if ( (UINT32)p == PRH_EEPROM_NO_STORED ) |
| 7985 |
return PRH_int_log_error(CM_RC_VAR_NOT_IN_EEPROM,id,__FILEID__,__LINE__); |
| 7986 |
if(*p != *(PRH_VAR_PTR[id])) |
| 7987 |
return PRH_int_write_eeprom_and_check(p,PRH_VAR_PTR[id],1); |
| 7988 |
return CM_RC_SUCCESSFUL; |
| 7989 |
}else |
| 7990 |
return s; |
| 7991 |
} |
| 7992 |
status_code PRH_int_var_read_eeprom(PRH_EEPROM_REGION region,unsigned int id) { |
| 7993 |
|
| 7994 |
PRH_VAR_TYPE* p; |
| 7995 |
status_code s=PRH_int_get_var_eeprom_address(region,id,&p); |
| 7996 |
if(s == CM_RC_SUCCESSFUL) { |
| 7997 |
if ( (UINT32)p == PRH_EEPROM_NO_STORED ) |
| 7998 |
return PRH_int_log_error(CM_RC_VAR_NOT_IN_EEPROM,id,__FILEID__,__LINE__); |
| 7999 |
return PRH_int_set_var(id,*p); |
| 8000 |
}else |
| 8001 |
return s; |
| 8002 |
} |
| 8003 |
status_code PRH_int_arr_write2eeprom(PRH_EEPROM_REGION region,unsigned int id) { |
| 8004 |
|
| 8005 |
PRH_VAR_TYPE* p; |
| 8006 |
status_code s=PRH_int_get_arr_eeprom_address(region,id,&p); |
| 8007 |
if(s == CM_RC_SUCCESSFUL) { |
| 8008 |
if ( (UINT32)p == PRH_EEPROM_NO_STORED ) |
| 8009 |
return PRH_int_log_error(CM_RC_ARR_NOT_IN_EEPROM,id,__FILEID__,__LINE__); |
| 8010 |
return PRH_int_write_eeprom_and_check(p,PRH_ARR_PTR[id],PRH_ARR_N[id]); |
| 8011 |
return CM_RC_SUCCESSFUL; |
| 8012 |
}else |
| 8013 |
return s; |
| 8014 |
} |
| 8015 |
status_code PRH_int_arr_read_eeprom(PRH_EEPROM_REGION region,unsigned int id) { |
| 8016 |
|
| 8017 |
PRH_VAR_TYPE* p; |
| 8018 |
unsigned int size; |
| 8019 |
status_code s=PRH_int_get_arr_eeprom_address(region,id,&p); |
| 8020 |
if(s == CM_RC_SUCCESSFUL) { |
| 8021 |
if ( (UINT32)p == PRH_EEPROM_NO_STORED ) |
| 8022 |
return PRH_int_log_error(CM_RC_ARR_NOT_IN_EEPROM,id,__FILEID__,__LINE__); |
| 8023 |
PRH_SIZEOF_ARR(id,&size); |
| 8024 |
memcpy(PRH_ARR_PTR[id],p,size); |
| 8025 |
return CM_RC_SUCCESSFUL; |
| 8026 |
}else |
| 8027 |
return s; |
| 8028 |
} |
| 8029 |
status_code PRH_int_tab_write2eeprom(PRH_EEPROM_REGION region,unsigned int id) { |
| 8030 |
|
| 8031 |
PRH_VAR_TYPE* p; |
| 8032 |
status_code s=PRH_int_get_tab_eeprom_address(region,id,&p); |
| 8033 |
if(s == CM_RC_SUCCESSFUL) { |
| 8034 |
if ( (UINT32)p == PRH_EEPROM_NO_STORED ) |
| 8035 |
return PRH_int_log_error(CM_RC_TAB_NOT_IN_EEPROM,id,__FILEID__,__LINE__); |
| 8036 |
return PRH_int_write_eeprom_and_check(p,PRH_TAB_PTR[id],PRH_TAB_NROW[id]*PRH_TAB_NCOL[id]); |
| 8037 |
return CM_RC_SUCCESSFUL; |
| 8038 |
}else |
| 8039 |
return s; |
| 8040 |
} |
| 8041 |
status_code PRH_int_tab_read_eeprom(PRH_EEPROM_REGION region,unsigned int id) { |
| 8042 |
|
| 8043 |
PRH_VAR_TYPE* p; |
| 8044 |
unsigned int size; |
| 8045 |
status_code s=PRH_int_get_tab_eeprom_address(region,id,&p); |
| 8046 |
if(s == CM_RC_SUCCESSFUL) { |
| 8047 |
if ( (UINT32)p == PRH_EEPROM_NO_STORED ) |
| 8048 |
return PRH_int_log_error(CM_RC_TAB_NOT_IN_EEPROM,id,__FILEID__,__LINE__); |
| 8049 |
PRH_SIZEOF_TABLE(id,&size); |
| 8050 |
memcpy(PRH_TAB_PTR[id],p,size); |
| 8051 |
return CM_RC_SUCCESSFUL; |
| 8052 |
}else |
| 8053 |
return s; |
| 8054 |
} |
| 8055 |
|
| 8056 |
#endif // ndef I386 |
| 8057 |
|
| 8058 |
#ifdef I386 |
| 8059 |
status_code PRH_int_get_var_name(unsigned int id,char *str_id) { |
| 8060 |
|
| 8061 |
if(id >= PRH_VAR_MAX) |
| 8062 |
return PRH_int_log_error(CM_RC_INVALID_VARID,id,__FILEID__,__LINE__); |
| 8063 |
return PRH_VAR_NAME[id]; |
| 8064 |
} |
| 8065 |
status_code PRH_int_get_arr_name(unsigned int id,char *str_id) { |
| 8066 |
|
| 8067 |
if(id >= PRH_ARR_MAX) |
| 8068 |
return PRH_int_log_error(CM_RC_INVALID_ARRID,id,__FILEID__,__LINE__); |
| 8069 |
return PRH_ARR_NAME[id]; |
| 8070 |
} |
| 8071 |
status_code PRH_int_get_tab_name(unsigned int id,char *str_id) { |
| 8072 |
|
| 8073 |
if(id >= PRH_TAB_MAX) |
| 8074 |
return PRH_int_log_error(CM_RC_INVALID_TABID,id,__FILEID__,__LINE__); |
| 8075 |
return PRH_TAB_NAME[id]; |
| 8076 |
} |
| 8077 |
|
| 8078 |
#endif // I386 |
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