| 1 |
/**************************************************************************** |
| 2 |
/* F i l e D a t a |
| 3 |
/* |
| 4 |
/* Module : BootStrap |
| 5 |
/* C.I. No. : |
| 6 |
/* $Revision: 1.1.1.1 $ |
| 7 |
/* $Date: 2003/08/04 09:40:21 $ |
| 8 |
/* Belonging to : |
| 9 |
/* : |
| 10 |
/* $RCSfile: promload.c,v $ |
| 11 |
/* Program Type : |
| 12 |
/* Sub-modules : |
| 13 |
/* |
| 14 |
/**************************************************************************** |
| 15 |
/* S W D e v e l o p m e n t E n v i r o n m e n t |
| 16 |
/* |
| 17 |
/* Host system : |
| 18 |
/* SW Compiler : |
| 19 |
/* Author Daniele Cortesi $ |
| 20 |
/* : |
| 21 |
/**************************************************************************** |
| 22 |
/* U p d a t i n g |
| 23 |
/* 10/07/20000 - Created |
| 24 |
/* |
| 25 |
/* $Log: promload.c,v $ |
| 26 |
/* Revision 1.1.1.1 2003/08/04 09:40:21 sebastiani |
| 27 |
/* Imported sources laben rel. 19.06.2003 integrated with pam2 |
| 28 |
/* |
| 29 |
/* Revision 1.5 2002/07/25 09:24:46 zulia |
| 30 |
/* FM PROM - Configurated version |
| 31 |
/* |
| 32 |
/* Revision 1.4 2002/07/16 07:12:50 zulia |
| 33 |
/* setup for 4MB |
| 34 |
/* |
| 35 |
/* Revision 1.3 2002/05/09 08:16:34 zulia |
| 36 |
/* * acceptance release |
| 37 |
/* |
| 38 |
/* |
| 39 |
/*****************************************************************************/ |
| 40 |
|
| 41 |
|
| 42 |
/*****************************************************************************/ |
| 43 |
/* Copyright (C) 2000 LABEN all rights reserved */ |
| 44 |
/*****************************************************************************/ |
| 45 |
|
| 46 |
|
| 47 |
/*============================= Include File ================================*/ |
| 48 |
|
| 49 |
#include <src/BootStrap/Boot/la695eEos.h> |
| 50 |
#include <src/BootStrap/Boot/la695e.h> |
| 51 |
|
| 52 |
/*****************************************************************************/ |
| 53 |
/*============================= Local define ================================*/ |
| 54 |
|
| 55 |
/** GPI data Register (to see if the test connector is connected) **/ |
| 56 |
#define GPI_DAT_REG 0xac |
| 57 |
/** Pin 0 of GPI (If ==0x08 TEST CONNECTOR connected) **/ |
| 58 |
#define TEST_PIN 0x08 |
| 59 |
|
| 60 |
#define USR 0xe8/4 |
| 61 |
#define TXA 0xe0/4 |
| 62 |
#define ERSR 0xb0/4 |
| 63 |
|
| 64 |
#define SECMAX 32 |
| 65 |
#define SECNAME 16 |
| 66 |
|
| 67 |
typedef struct sectype { |
| 68 |
unsigned int paddr; |
| 69 |
unsigned int raddr; |
| 70 |
unsigned int len; |
| 71 |
unsigned int comp; |
| 72 |
unsigned char name[SECNAME]; |
| 73 |
}tt; |
| 74 |
|
| 75 |
|
| 76 |
extern char filename[]; |
| 77 |
extern struct sectype sections[]; |
| 78 |
extern int prot; |
| 79 |
|
| 80 |
void |
| 81 |
putsx(s) |
| 82 |
unsigned char *s; |
| 83 |
{ |
| 84 |
volatile unsigned int *mec = (unsigned int *) 0x1f80000; |
| 85 |
|
| 86 |
while (s[0] != 0) { |
| 87 |
while ((mec[USR] & 4) == 0); |
| 88 |
mec[TXA] = *s; |
| 89 |
s++; |
| 90 |
} |
| 91 |
} |
| 92 |
|
| 93 |
memprotect(start, end) |
| 94 |
unsigned int start, end; |
| 95 |
{ |
| 96 |
int sbr, ser; |
| 97 |
volatile unsigned int *mec = (unsigned int *) 0x1f80000; |
| 98 |
|
| 99 |
mec[0x24 / 4] = ((end & 0x007fffff) >> 2); |
| 100 |
mec[0x20 / 4] = ((start & 0x007fffff) >> 2) | 0x01800000; |
| 101 |
} |
| 102 |
|
| 103 |
extern int stack; |
| 104 |
set_stack(top) |
| 105 |
unsigned int top; |
| 106 |
{ |
| 107 |
asm(" |
| 108 |
retl |
| 109 |
mov %o0, %sp |
| 110 |
"); |
| 111 |
} |
| 112 |
|
| 113 |
__main() |
| 114 |
{ |
| 115 |
} |
| 116 |
|
| 117 |
/*****************************************************************************/ |
| 118 |
/*========================== Global Function prototype ======================*/ |
| 119 |
int eosBoardTest (void) ; |
| 120 |
int eosEepromCheckSumTest (void); |
| 121 |
|
| 122 |
/*============================ Extern Variables =============================*/ |
| 123 |
extern int ramsize, etext, freq; |
| 124 |
void clean(); |
| 125 |
extern int Decode(); |
| 126 |
extern char configmsg[]; |
| 127 |
|
| 128 |
main() |
| 129 |
{ |
| 130 |
unsigned char *p; |
| 131 |
int paddr, raddr, len, secnum; |
| 132 |
void (*prog) (); |
| 133 |
int (*func) (); |
| 134 |
char pbuf[8192]; |
| 135 |
volatile unsigned int *mec = (unsigned int *) 0x1f80000; |
| 136 |
|
| 137 |
prog = (void *) sections[0].paddr; |
| 138 |
putsx("\n\n\r ERC32 boot loader v1.1\n\n\r"); |
| 139 |
putsx(configmsg); |
| 140 |
putsx("\n\r"); |
| 141 |
mmov(clean,pbuf,0x100); |
| 142 |
putsx(" initialising ram memory\n\r"); |
| 143 |
func = (void *)pbuf; |
| 144 |
func(0x2000000,ramsize - 0x10000); |
| 145 |
secnum = 0; |
| 146 |
|
| 147 |
/**------------------------------------------------------------- |
| 148 |
**---- check on TEST CONNECTOR --> |
| 149 |
**---- if not CONNECTED load APPLICATION |
| 150 |
**---- else load MONITOR(section 0,1) |
| 151 |
**---- |
| 152 |
**------------------------------------------------------------- |
| 153 |
**/ |
| 154 |
|
| 155 |
if (mec[GPI_DAT_REG / 4] & TEST_PIN) |
| 156 |
{ |
| 157 |
/** TEST CONNECTOR not connected **/ |
| 158 |
putsx("\n\r ************ STARTING APPLICATION **********\n\r"); |
| 159 |
|
| 160 |
mec[0x20 / 4] = 0; |
| 161 |
mec[0x24 / 4] = 0; |
| 162 |
mec[0x14 / 4] =0x0000001f; |
| 163 |
|
| 164 |
prog = (void *) RAM_START_EXE; |
| 165 |
//prog =(void*)0x02001000; |
| 166 |
|
| 167 |
raddr =EEPROM_START_EXE; |
| 168 |
paddr =RAM_START_EXE; |
| 169 |
len =EEPROM_LEN_EXE; |
| 170 |
putsx(" Loading .text \n\r"); |
| 171 |
putsx(" Loding .data \n\r"); |
| 172 |
|
| 173 |
func = (void *)((int)mmov + (int)pbuf - (int)clean); |
| 174 |
func(raddr, paddr,len); |
| 175 |
putsx("\n\r End\n\r"); |
| 176 |
|
| 177 |
*((int *) (RAM_START_EXE + 0x7e0)) = freq; |
| 178 |
} |
| 179 |
else |
| 180 |
{ |
| 181 |
/** TEST CONNECTOR connected **/ |
| 182 |
putsx("\n\r ************* STARTING MONITOR **************\n\r"); |
| 183 |
|
| 184 |
while (sections[secnum].paddr) |
| 185 |
{ |
| 186 |
paddr = sections[secnum].paddr; |
| 187 |
raddr = sections[secnum].raddr; |
| 188 |
len = sections[secnum].len; |
| 189 |
putsx(" loading "); |
| 190 |
putsx(sections[secnum].name); |
| 191 |
putsx("\n\r"); |
| 192 |
func = (void *)((int)mmov + (int)pbuf - (int)clean); |
| 193 |
func(raddr, paddr,len); |
| 194 |
secnum++; |
| 195 |
} |
| 196 |
if (prot) |
| 197 |
{ |
| 198 |
memprotect(sections[0].paddr + 0x1000, |
| 199 |
sections[0].paddr + sections[0].len); |
| 200 |
} |
| 201 |
putsx("\n\r End\n\r"); |
| 202 |
*((int *) (sections[0].paddr + 0x7e0)) = freq; |
| 203 |
} |
| 204 |
|
| 205 |
putsx("\n\r ****** Program running ******\n\r"); |
| 206 |
prog(); |
| 207 |
} |
| 208 |
|
| 209 |
void clean(paddr,len) |
| 210 |
double *paddr; |
| 211 |
int len; |
| 212 |
{ |
| 213 |
len >>=3; |
| 214 |
while (len >= 0) { |
| 215 |
paddr[len] = 0; |
| 216 |
len--; |
| 217 |
} |
| 218 |
} |
| 219 |
|
| 220 |
mmov(raddr,paddr,len) |
| 221 |
int *raddr, *paddr; |
| 222 |
int len; |
| 223 |
{ |
| 224 |
len >>=2; |
| 225 |
while (len >= 0) { |
| 226 |
paddr[len] = raddr[len]; |
| 227 |
len--; |
| 228 |
} |
| 229 |
} |
| 230 |
|
| 231 |
|
| 232 |
|
| 233 |
/*****************************************************************************/ |
| 234 |
/*=================== I N T E R N A L F U N C T I O N S ==================*/ |
| 235 |
/***************************************************************************** |
| 236 |
* |
| 237 |
* eosBoardTest - test TSC695E of LA695E-CORE board |
| 238 |
* |
| 239 |
* This routine perform the test of TSC695E by using the testing facility |
| 240 |
* offered by the MEC Test Control Register |
| 241 |
* |
| 242 |
* The routine does not use RAM |
| 243 |
* The Interrupt Test is not done because it needs RAM |
| 244 |
* |
| 245 |
* RETURNS: |
| 246 |
* BIT_OK |
| 247 |
* BIT_NOK_EDAC_TEST |
| 248 |
* BIT_NOK_PARITY_TEST |
| 249 |
* BIT_NOK_INTERRUPT_TEST never |
| 250 |
* BIT_NOK_ERROR_TEST |
| 251 |
* any OR combination of BIT_NOK_xx |
| 252 |
* |
| 253 |
* |
| 254 |
*/ |
| 255 |
|
| 256 |
int eosBoardTest (void) |
| 257 |
{ |
| 258 |
unsigned int register eosBoardTestResult; |
| 259 |
unsigned int tmpData; |
| 260 |
|
| 261 |
eosBoardTestResult =0; |
| 262 |
|
| 263 |
if (edacTest()!= OK) |
| 264 |
eosBoardTestResult |=BIT_NOK_EDAC_TEST; |
| 265 |
/* |
| 266 |
if (parityTest()!= OK) |
| 267 |
eosBoardTestResult |=BIT_NOK_PARITY_TEST; |
| 268 |
*/ |
| 269 |
if (interruptTest()!= OK) |
| 270 |
eosBoardTestResult |=BIT_NOK_INTERRUPT_TEST ; |
| 271 |
|
| 272 |
if (errorTest()!= OK) |
| 273 |
eosBoardTestResult |=BIT_NOK_ERROR_TEST; |
| 274 |
|
| 275 |
return (eosBoardTestResult); |
| 276 |
|
| 277 |
} |
| 278 |
|
| 279 |
/******************************************************************************* |
| 280 |
* |
| 281 |
* edacTest - test EDAC functionalities |
| 282 |
* |
| 283 |
* |
| 284 |
*/ |
| 285 |
|
| 286 |
int edacTest (void) |
| 287 |
{ |
| 288 |
if (edacSefTest() != OK) |
| 289 |
return (NOK) ; |
| 290 |
if (edacDefTest() != OK) |
| 291 |
return (NOK); |
| 292 |
if (edacNoErrorTest() != OK) |
| 293 |
return (NOK); |
| 294 |
return(OK) ; |
| 295 |
} |
| 296 |
|
| 297 |
/******************************************************************************* |
| 298 |
* |
| 299 |
* edacSefTest - test the EDAC capability to detect and correct a single error |
| 300 |
* |
| 301 |
* RETURNS: |
| 302 |
* OK |
| 303 |
* NOK |
| 304 |
*/ |
| 305 |
|
| 306 |
asm(" |
| 307 |
.text |
| 308 |
.global _edacSefTest |
| 309 |
|
| 310 |
|
| 311 |
|
| 312 |
_edacSefTest: |
| 313 |
save ! New window |
| 314 |
|
| 315 |
|
| 316 |
! Enable traps |
| 317 |
mov %psr, %l0 ! %l0 saved psr |
| 318 |
or %l0, 0x20, %l1 ! psr.et=1 |
| 319 |
mov %l1, %psr |
| 320 |
nop |
| 321 |
nop |
| 322 |
nop |
| 323 |
|
| 324 |
! EDAC enable |
| 325 |
! set to 1 rec bit (14) of MemoryConfigurationRegister |
| 326 |
set 0x01f80010, %l1 |
| 327 |
ld [%l1], %l2 |
| 328 |
set 0x00004000, %l3 |
| 329 |
or %l2, %l3, %l2 |
| 330 |
st %l2, [%l1] |
| 331 |
|
| 332 |
! clear interrupt level 6 EDAC SEF |
| 333 |
! set to 1 bit 6 of InterruptClearRegister */ |
| 334 |
set 0x01f80050, %l1 |
| 335 |
set 0x00000040, %l2 |
| 336 |
st %l2, [%l1] |
| 337 |
|
| 338 |
! initialise test locations |
| 339 |
! GM |
| 340 |
set 0x02000000, %l1 ! first RAM valid address |
| 341 |
st %g0, [%l1] |
| 342 |
set 0x023ffffc, %l2 ! last RAM valid address (4MB) |
| 343 |
st %g0, [%l2] |
| 344 |
|
| 345 |
set 0x01f800d0, %l2 ! %l2 TestControlRegister |
| 346 |
set 2, %l3 ! %l3 loop counter |
| 347 |
|
| 348 |
|
| 349 |
SEF_LOOP: |
| 350 |
|
| 351 |
! Set EDAC test bits in TestControlRegister |
| 352 |
! et = 1 meaning EDAC test enabled |
| 353 |
! cb = 0010000 check bit of pattern 0x0 with 1 bit failed |
| 354 |
! (cb correct is 0010100) |
| 355 |
ld [%l2] , %l4 |
| 356 |
set 0x00020010, %l5 |
| 357 |
or %l4 , %l5 , %l4 |
| 358 |
st %l4 , [%l2] |
| 359 |
|
| 360 |
! store test value in test location |
| 361 |
clr %l4 |
| 362 |
st %l4 , [%l1] |
| 363 |
|
| 364 |
! Set ET =0 in TestControlRegister |
| 365 |
ld [%l2] , %l4 |
| 366 |
set 0x00020000, %l5 |
| 367 |
andn %l4 , %l5 , %l4 |
| 368 |
st %l4 , [%l2] |
| 369 |
|
| 370 |
! read back test location |
| 371 |
ld [%l1] , %l4 |
| 372 |
|
| 373 |
! If read back value is not the written value i.e. 0 then jump |
| 374 |
cmp %l4, 0 |
| 375 |
bne SEF_LOOP_TEST |
| 376 |
nop |
| 377 |
|
| 378 |
SEF_INPT_PEND_TEST: |
| 379 |
! test if intp level 6 is pending |
| 380 |
set 0x01f80048, %l5 ! InterruptPendingRegister |
| 381 |
ld [%l5], %l5 |
| 382 |
andcc %l5, 0x40, %l5 ! 0x40 mask for int lev 6 |
| 383 |
bnz SEF_OK |
| 384 |
nop |
| 385 |
|
| 386 |
SEF_LOOP_TEST: |
| 387 |
! dove e' implementato la scansione della memoria ??????? |
| 388 |
set 0x023ffffc, %l1 ! %l1 last RAM valid address (4MB) |
| 389 |
subcc %l3, 1, %l3 |
| 390 |
bnz SEF_LOOP |
| 391 |
nop |
| 392 |
|
| 393 |
SEF_FAIL : |
| 394 |
mov 1, %i0 ! i0 = 1 -> NOK |
| 395 |
ba SEF_END |
| 396 |
nop |
| 397 |
|
| 398 |
SEF_OK : |
| 399 |
mov 0, %i0 ! i0 = 0 -> OK |
| 400 |
|
| 401 |
SEF_END : |
| 402 |
! restore psr |
| 403 |
mov %l0, %psr |
| 404 |
nop |
| 405 |
nop |
| 406 |
nop |
| 407 |
|
| 408 |
ret |
| 409 |
restore |
| 410 |
nop |
| 411 |
|
| 412 |
") ; |
| 413 |
|
| 414 |
|
| 415 |
|
| 416 |
|
| 417 |
/******************************************************************************* |
| 418 |
* |
| 419 |
* edacDefTest - test the EDAC capability to detect a double error |
| 420 |
* |
| 421 |
* RETURNS: |
| 422 |
* OK |
| 423 |
* NOK |
| 424 |
* |
| 425 |
*/ |
| 426 |
|
| 427 |
asm(" |
| 428 |
.text |
| 429 |
.global _edacDefTest |
| 430 |
|
| 431 |
_edacDefTest: |
| 432 |
|
| 433 |
save ! New window |
| 434 |
set 0x02000010, %l6 !TBD for debug |
| 435 |
|
| 436 |
! Enable traps |
| 437 |
mov %psr, %l0 ! %l0 saved psr |
| 438 |
or %l0, 0x20, %l1 ! psr.et=1 |
| 439 |
mov %l1, %psr |
| 440 |
nop |
| 441 |
nop |
| 442 |
nop |
| 443 |
! st %l1, [%l6] !TBD for debug |
| 444 |
|
| 445 |
! sethi %hi(TRAP_TABLE_TEST), %l6 ! Sets trap table for test |
| 446 |
! mov %l6, %tbr |
| 447 |
|
| 448 |
! EDAC enable |
| 449 |
! set to 1 rec bit (14) of MemoryConfigurationRegister |
| 450 |
set 0x01f80010, %l1 |
| 451 |
ld [%l1], %l2 |
| 452 |
set 0x00004000, %l3 |
| 453 |
or %l2, %l3, %l2 |
| 454 |
st %l2, [%l1] |
| 455 |
! st %l2, [%l6] !TBD for debug |
| 456 |
|
| 457 |
! Mask IU Error Mode in SystemControlRegister |
| 458 |
! set to 1 iuemmsk bit 5 |
| 459 |
set 0x01f80000, %l1 |
| 460 |
ld [%l1], %l2 |
| 461 |
or %l2, 0x20, %l2 |
| 462 |
st %l2, [%l1] |
| 463 |
! st %l2, [%l6] !TBD for debug |
| 464 |
|
| 465 |
set 0x01f800d0, %l2 ! %l2 TestControlRegister |
| 466 |
set 2, %l3 ! %l3 loop counter |
| 467 |
set 0x01f800a0, %l7 ! %l7 SystemFaultStatusRegister |
| 468 |
|
| 469 |
! initialise test locations |
| 470 |
! GM |
| 471 |
set 0x02000000, %l1 ! first RAM valid address |
| 472 |
st %g0, [%l1] |
| 473 |
! end GM |
| 474 |
|
| 475 |
DEF_LOOP: |
| 476 |
! Set EDAC test bits in TestControlRegister |
| 477 |
! et= 1 meaning EDAC test enabled |
| 478 |
! cb= 0000000 check bit of pattern 0x00000000 with two bits failed TBD |
| 479 |
! (cb correct is 0010100) |
| 480 |
ld [%l2] , %l4 |
| 481 |
set 0x0002007f, %l5 |
| 482 |
andn %l4 , %l5 , %l4 ! clear et and cb |
| 483 |
set 0x00020000, %l5 |
| 484 |
or %l4 , %l5 , %l4 ! set cb |
| 485 |
st %l4 , [%l2] |
| 486 |
! st %l4, [%l6] !TBD for debug |
| 487 |
|
| 488 |
! store test value in test location |
| 489 |
clr %l4 |
| 490 |
st %l4 , [%l1] |
| 491 |
! st %l4, [%l6] !TBD for debug |
| 492 |
|
| 493 |
! Set et=0 and cb=0 in TestControlRegister |
| 494 |
ld [%l2] , %l4 |
| 495 |
set 0x0002007f, %l5 |
| 496 |
andn %l4 , %l5 , %l4 |
| 497 |
st %l4 , [%l2] |
| 498 |
! st %l4, [%l6] !TBD for debug |
| 499 |
|
| 500 |
! read back test location |
| 501 |
ld [%l1] , %l4 |
| 502 |
nop |
| 503 |
nop |
| 504 |
|
| 505 |
!Double Error Should have been detected |
| 506 |
!Read System Fault Status register |
| 507 |
ld [%l7] , %l4 |
| 508 |
! st %l4, [%l6] !TBD for debug |
| 509 |
and %l4, 0x7c, %l4 ! GM was 0x78 |
| 510 |
cmp %l4, 0x3c ! GM was 0x38 |
| 511 |
be DEF_OK |
| 512 |
nop |
| 513 |
|
| 514 |
DEF_LOOP_TEST : |
| 515 |
set 0x023ffffc, %l1 ! last RAM valid address (4MB) |
| 516 |
subcc %l3, 1, %l3 |
| 517 |
bnz DEF_LOOP |
| 518 |
nop |
| 519 |
|
| 520 |
DEF_FAIL : |
| 521 |
mov 1, %i0 ! i0 = 1 -> NOK |
| 522 |
ba DEF_END |
| 523 |
nop |
| 524 |
|
| 525 |
DEF_OK : |
| 526 |
mov 0x7c, %l4 ! 18-sep-01 GM reset System Fault Status register |
| 527 |
st %l4, [%l7] ! "" GM |
| 528 |
|
| 529 |
mov 0, %i0 ! i0 = 0 -> OK |
| 530 |
|
| 531 |
DEF_END : |
| 532 |
|
| 533 |
! sethi %hi(TRAP_TABLE), %l6 ! Restores default trap table |
| 534 |
! mov %l6, %tbr |
| 535 |
|
| 536 |
! restore psr |
| 537 |
mov %l0, %psr |
| 538 |
nop |
| 539 |
nop |
| 540 |
nop |
| 541 |
|
| 542 |
ret |
| 543 |
restore |
| 544 |
nop |
| 545 |
|
| 546 |
") ; |
| 547 |
|
| 548 |
|
| 549 |
/******************************************************************************* |
| 550 |
* |
| 551 |
* edacNoErrorTest - test the EDAC behaviour in case of no error |
| 552 |
* |
| 553 |
* RETURNS: |
| 554 |
* OK |
| 555 |
* NOK |
| 556 |
*/ |
| 557 |
|
| 558 |
asm(" |
| 559 |
.text |
| 560 |
.global _edacNoErrorTest |
| 561 |
|
| 562 |
_edacNoErrorTest: |
| 563 |
save ! New window |
| 564 |
set 0x02000010, %l6 !TBD for debug |
| 565 |
|
| 566 |
! Enable traps |
| 567 |
mov %psr, %l0 ! %l0 saved psr |
| 568 |
or %l0, 0x20, %l1 ! psr.et=1 |
| 569 |
mov %l1, %psr |
| 570 |
|
| 571 |
! EDAC enable |
| 572 |
! set to 1 rec bit (14) of MemoryConfigurationRegister |
| 573 |
set 0x01f80010, %l1 |
| 574 |
ld [%l1], %l2 |
| 575 |
set 0x00004000, %l3 |
| 576 |
or %l2, %l3, %l2 |
| 577 |
st %l2, [%l1] |
| 578 |
|
| 579 |
! clear interrupt level 6 EDAC SEF |
| 580 |
! set to 1 bit 6 of InterruptClearRegister |
| 581 |
set 0x01f80050, %l1 |
| 582 |
set 0x00000040, %l2 |
| 583 |
st %l2, [%l1] |
| 584 |
|
| 585 |
set 0x01f80048, %l2 ! %l2 InterruptPendingRegister |
| 586 |
set 2, %l3 ! %l3 loop counter |
| 587 |
|
| 588 |
! initialise test locations |
| 589 |
! GM |
| 590 |
set 0x02000000, %l1 ! first RAM valid address |
| 591 |
! st %g0, [%l1] !GP 13-12-01 executed after |
| 592 |
! end GM |
| 593 |
|
| 594 |
NOERROR_LOOP: |
| 595 |
! store test value in test location |
| 596 |
clr %l4 |
| 597 |
st %l4 , [%l1] |
| 598 |
nop |
| 599 |
nop |
| 600 |
|
| 601 |
! read back |
| 602 |
ld [%l1] , %l5 |
| 603 |
|
| 604 |
! compare written value with the read back one |
| 605 |
cmp %l4 , %l5 |
| 606 |
bne NOERROR_LOOP_TEST |
| 607 |
nop |
| 608 |
|
| 609 |
NOERROR_INTP_PEND_TEST: |
| 610 |
ld [%l2], %l5 |
| 611 |
st %l5, [%l6] !TBD for debug |
| 612 |
andcc %l5, 0x40, %l5 ! 0x40 mask for int lev 6 |
| 613 |
bz NOERROR_OK |
| 614 |
nop |
| 615 |
|
| 616 |
NOERROR_LOOP_TEST: |
| 617 |
set 0x023ffffc, %l1 ! last RAM valid address (4MB) |
| 618 |
subcc %l3, 1, %l3 |
| 619 |
bnz NOERROR_LOOP |
| 620 |
nop |
| 621 |
|
| 622 |
NOERROR_FAIL : |
| 623 |
mov 1, %i0 ! i0 = 1 -> NOK |
| 624 |
ba NOERROR_END |
| 625 |
nop |
| 626 |
|
| 627 |
NOERROR_OK : |
| 628 |
mov 0, %i0 ! i0 = 0 -> OK |
| 629 |
|
| 630 |
|
| 631 |
NOERROR_END : |
| 632 |
! restore psr |
| 633 |
mov %l0, %psr |
| 634 |
nop |
| 635 |
nop |
| 636 |
nop |
| 637 |
|
| 638 |
ret |
| 639 |
restore |
| 640 |
nop |
| 641 |
|
| 642 |
"); |
| 643 |
|
| 644 |
|
| 645 |
/************************************************************************** |
| 646 |
* |
| 647 |
* edacTh - |
| 648 |
* |
| 649 |
* RETURNS |
| 650 |
* |
| 651 |
*/ |
| 652 |
|
| 653 |
asm(" |
| 654 |
.text |
| 655 |
.global _edacTh |
| 656 |
|
| 657 |
_edacTh: |
| 658 |
|
| 659 |
jmp %l2 ! Jump to nPC |
| 660 |
rett %l2 + 4 |
| 661 |
nop |
| 662 |
") ; |
| 663 |
|
| 664 |
|
| 665 |
/******************************************************************************* |
| 666 |
* |
| 667 |
* interruptTest - interrupt test |
| 668 |
* |
| 669 |
* DESCRIPTION |
| 670 |
* Saves interrupts status, switches to the test trap table, sets interrupt test |
| 671 |
* mode and uses the IFR to force interrupts. The routine checks if the asynchronous |
| 672 |
* trap routine starts. |
| 673 |
* Finally restores interrupt status, the previous trap table (default) and returns the |
| 674 |
* result OK (0) or NOK (1). The bootstrap log record is updated in builtInTest. |
| 675 |
* |
| 676 |
*/ |
| 677 |
|
| 678 |
asm(" |
| 679 |
.text |
| 680 |
.global _interruptTest |
| 681 |
|
| 682 |
_interruptTest: |
| 683 |
save ! New window |
| 684 |
|
| 685 |
! enable traps |
| 686 |
mov %psr, %l0 ! %l0 saved psr |
| 687 |
and %l0, 0xfffff0ff, %l1 ! Clear pil bits: enable all traps |
| 688 |
or %l1, 0x20, %l1 ! psr.et=1 |
| 689 |
mov %l1, %psr |
| 690 |
nop |
| 691 |
nop |
| 692 |
nop |
| 693 |
|
| 694 |
set 0x01f80044, %l3 |
| 695 |
set 0x01f, %l1 |
| 696 |
st %l1,[%l3] ! Set all ext INT to edge |
| 697 |
|
| 698 |
! save IMR |
| 699 |
set 0x01f8004c, %l3 ! %l3 InterruptMaskReg |
| 700 |
ld [%l3], %l7 ! saves interrupt mask reg to on l3 |
| 701 |
|
| 702 |
! change TBR |
| 703 |
! sethi %hi(TRAP_TABLE_TEST), %l4 ! trap table for test |
| 704 |
! mov %l4, %tbr |
| 705 |
|
| 706 |
! enable write on IFR |
| 707 |
set 0x01f800d0, %l3 ! %l3 TestControlReg |
| 708 |
ld [%l3], %l5 ! TestControlReg value |
| 709 |
set 0x00080000, %l6 ! it bit = 1 |
| 710 |
or %l5, %l6, %l5 ! sets et bit |
| 711 |
st %l5, [%l3] ! updates TestControlReg |
| 712 |
|
| 713 |
! loop for the actual int test tr |
| 714 |
mov %g0, %o0 ! resets the result flag |
| 715 |
set 0x7ffe, %l4 ! bit mask for IMR |
| 716 |
set 0x8000, %l5 ! bit mask for IFR |
| 717 |
mov %l4, %l6 ! aux bit mask for IMR (0x7ffe) |
| 718 |
|
| 719 |
INT_CHECK_LOOP: |
| 720 |
set 0x01f8004c, %l3 ! %l3 InterruptMaskRegister |
| 721 |
st %l4, [%l3] ! unmask the i-th int to test |
| 722 |
set 0x01f80054, %l3 ! %l3 InterruptForceRegister |
| 723 |
st %l5, [%l3] ! force i-th interrupt |
| 724 |
nop |
| 725 |
nop |
| 726 |
nop |
| 727 |
nop |
| 728 |
nop |
| 729 |
nop |
| 730 |
nop |
| 731 |
nop |
| 732 |
nop |
| 733 |
nop |
| 734 |
nop |
| 735 |
nop |
| 736 |
srl %l5, 1, %l5 ! new mask for the next int (IFR) |
| 737 |
not %l5, %l4 |
| 738 |
and %l4, %l6, %l4 ! new mask for the next int (IMR) |
| 739 |
subcc %l5, 1, %g0 ! compare end of loop |
| 740 |
bnz INT_CHECK_LOOP |
| 741 |
nop |
| 742 |
|
| 743 |
! result test |
| 744 |
set 0xfffe, %l5 |
| 745 |
subcc %o0, %l5, %g0 ! if %o0 == 0xfffe, test OK, else NOK |
| 746 |
be INT_OK |
| 747 |
nop |
| 748 |
|
| 749 |
INT_FAIL: |
| 750 |
mov 1, %i0 ! i0 = 1 -> NOK |
| 751 |
ba INT_END |
| 752 |
nop |
| 753 |
INT_OK: |
| 754 |
mov 0, %i0 ! i0 = 0 -> OK |
| 755 |
|
| 756 |
INT_END: |
| 757 |
! clear any pending int |
| 758 |
set 0x01f80050, %l3 ! %l3 InterruptClearRegister |
| 759 |
set 0xfffe, %l5 |
| 760 |
st %l5, [%l3] ! resets ICR (0xfffe) |
| 761 |
|
| 762 |
! restore int mask reg status |
| 763 |
set 0x01f8004c, %l3 ! %l3 InterruptMaskRegister |
| 764 |
st %l7, [%l3] ! restores interrupt mask reg to on l3 |
| 765 |
|
| 766 |
! disable write on IFR |
| 767 |
set 0x01f800d0, %l3 ! %l3 TestControlRegister |
| 768 |
ld [%l3] , %l5 ! TCR value |
| 769 |
set 0x0016007f, %l6 ! et bit = 0 |
| 770 |
and %l5 , %l6 , %l5 ! resets et bit |
| 771 |
st %l5 , [%l3] ! updates the TCR |
| 772 |
|
| 773 |
! restore trap table |
| 774 |
! sethi %hi(TRAP_TABLE), %l4 ! default trap table |
| 775 |
! mov %l4, %tbr |
| 776 |
|
| 777 |
! restore psr |
| 778 |
mov %l0, %psr |
| 779 |
nop |
| 780 |
nop |
| 781 |
nop |
| 782 |
|
| 783 |
ret |
| 784 |
restore |
| 785 |
nop |
| 786 |
|
| 787 |
"); |
| 788 |
|
| 789 |
/******************************************************************************* |
| 790 |
* |
| 791 |
* intpTh - |
| 792 |
* |
| 793 |
* RETURNS |
| 794 |
* |
| 795 |
*/ |
| 796 |
|
| 797 |
asm(" |
| 798 |
.text |
| 799 |
.global _intpTh |
| 800 |
|
| 801 |
_intpTh: |
| 802 |
rd %tbr, %l3 ! rdtbr trap table reg |
| 803 |
|
| 804 |
! prepare int index |
| 805 |
srl %l3, 4, %l3 |
| 806 |
and %l3, 0x000000ff, %l3 |
| 807 |
sub %l3, 16, %l3 |
| 808 |
|
| 809 |
set 0x00000001, %l4 |
| 810 |
sll %l4, %l3, %l4 ! set i-th int bit |
| 811 |
or %i0, %l4, %i0 ! output paramenter |
| 812 |
|
| 813 |
jmp %l2 ! Jump to nPC |
| 814 |
rett %l2 + 4 |
| 815 |
nop |
| 816 |
") ; |
| 817 |
|
| 818 |
|
| 819 |
|
| 820 |
|
| 821 |
/******************************************************************************* |
| 822 |
* |
| 823 |
* errorTest - test the capability of TSC695E to detect errors |
| 824 |
* |
| 825 |
* DESCRIPTION: |
| 826 |
* phylosophy : by enabling ewe bit in TestControlRegister, an error could be |
| 827 |
* simulated by setting to 1 the followings bits in Error&ResetStatusRegister, |
| 828 |
* iuem |
| 829 |
* iuhe |
| 830 |
* syshe |
| 831 |
* (fpuhe=1 causes nothing according to fig.13 DataSheetRevE TBD) |
| 832 |
* The check is done by verifing that int lev 1 ("Masked hardware errors") is |
| 833 |
* pending. |
| 834 |
* So first int lev 1 shall be masked then the simulated errors shall be masked |
| 835 |
* in SystemControlRegister setting to 1 the bits |
| 836 |
* iuemmsk |
| 837 |
* iuhemmsk |
| 838 |
* syshemsk |
| 839 |
* RETURNS: |
| 840 |
* OK |
| 841 |
* NOK |
| 842 |
* |
| 843 |
*/ |
| 844 |
asm(" |
| 845 |
.text |
| 846 |
.global _errorTest |
| 847 |
|
| 848 |
_errorTest: |
| 849 |
save ! New window |
| 850 |
|
| 851 |
! save InterruptMaskRegister |
| 852 |
set 0x01f8004c, %l0 |
| 853 |
ld [%l0], %l0 ! %l0 InterruptMaskRegister |
| 854 |
|
| 855 |
! save SystemControlRegister |
| 856 |
set 0x01f80000, %l1 |
| 857 |
ld [%l1], %l1 ! %l1 SystemControlRegister |
| 858 |
|
| 859 |
! clear Pending Interrupt |
| 860 |
set 0x01f80050, %l2 |
| 861 |
set 0xfffe, %l3 |
| 862 |
st %l3, [%l2] |
| 863 |
|
| 864 |
! mask all int levs |
| 865 |
set 0x01f8004c, %l2 |
| 866 |
set 0x00007ffe, %l3 |
| 867 |
st %l3, [%l2] |
| 868 |
|
| 869 |
! Enable Error Write (ewe bit20) in TestControlRegister |
| 870 |
! ewe= 1 meaning Write to Error&ResetStatusRegister enabled |
| 871 |
set 0x01f800d0, %l2 |
| 872 |
!set 0x00010000, %l3 GP 15-10-01 |
| 873 |
set 0x00100000, %l3!GP 10-12-01 si dovrebbe fare un OR non un set |
| 874 |
st %l3, [%l2] |
| 875 |
|
| 876 |
|
| 877 |
|
| 878 |
!****************** 1) IU Error Mode ********************* |
| 879 |
! In SystemControlRegister mask the error which is going to be injected |
| 880 |
! IU Error Mode |
| 881 |
set 0x01f80000, %l2 |
| 882 |
set 0x20, %l3 ! iuemmsk bit (bit 5) |
| 883 |
or %l1, %l3, %l3 |
| 884 |
st %l3, [%l2] |
| 885 |
|
| 886 |
! inject IU error |
| 887 |
! set to 1 bit 0 iuem in Error&ResetStatusRegister |
| 888 |
set 0x01f800b0, %l2 |
| 889 |
set 0x1, %l3 ! iuem bit (bit 0)!GP 10-12-01 si dovrebbe fare un OR non un set |
| 890 |
st %l3, [%l2] |
| 891 |
|
| 892 |
! int lev 1 should be pending |
| 893 |
! set 0x01f80050, %l2 |
| 894 |
set 0x01f80048, %l2 |
| 895 |
ld [%l2], %l2 |
| 896 |
andcc %l2, 2, %l2 |
| 897 |
bz ERROR_FAIL |
| 898 |
nop |
| 899 |
|
| 900 |
! Rollback Error&ResetStatusRegister |
| 901 |
set 0x01f800b0, %l2 |
| 902 |
set 0x0, %l3 |
| 903 |
st %l3, [%l2] |
| 904 |
|
| 905 |
! clear int lev 1 pending |
| 906 |
set 0x01f80050, %l2 |
| 907 |
set 0x2, %l3 |
| 908 |
st %l3, [%l2] |
| 909 |
|
| 910 |
|
| 911 |
|
| 912 |
|
| 913 |
|
| 914 |
!****************** 2) IU HW Error ********************* |
| 915 |
! restore initial value of SystemControlRegister |
| 916 |
set 0x01f80000, %l2 |
| 917 |
st %l1, [%l2] |
| 918 |
|
| 919 |
! In SystemControlRegister mask the error which is going to be injected |
| 920 |
! IU HW Error |
| 921 |
set 0x01f80000, %l2 |
| 922 |
set 0x80, %l3 ! iuhemmsk bit (bit 7) |
| 923 |
or %l1, %l3, %l3 |
| 924 |
st %l3, [%l2] |
| 925 |
|
| 926 |
! inject IU HW error |
| 927 |
! set to 1 bit 0 iuhe in Error&ResetStatusRegister |
| 928 |
set 0x01f800b0, %l2 |
| 929 |
set 0x2, %l3 ! iuhe bit (bit 1) |
| 930 |
st %l3, [%l2] |
| 931 |
|
| 932 |
! int lev 1 should be pending |
| 933 |
! set 0x01f80050, %l2 |
| 934 |
set 0x01f80048, %l2 |
| 935 |
ld [%l2], %l2 |
| 936 |
andcc %l2, 2, %l2 |
| 937 |
bz ERROR_FAIL |
| 938 |
nop |
| 939 |
|
| 940 |
! Rollback Error&ResetStatusRegister |
| 941 |
set 0x01f800b0, %l2 |
| 942 |
set 0x0, %l3 |
| 943 |
st %l3, [%l2] |
| 944 |
|
| 945 |
! clear int lev 1 pending |
| 946 |
set 0x01f80050, %l2 |
| 947 |
set 0x2, %l3 |
| 948 |
st %l3, [%l2] |
| 949 |
|
| 950 |
|
| 951 |
|
| 952 |
|
| 953 |
|
| 954 |
!****************** 3) SYStem HW Error ********************* |
| 955 |
! restore initial value of SystemControlRegister |
| 956 |
set 0x01f80000, %l2 |
| 957 |
st %l1, [%l2] |
| 958 |
|
| 959 |
! In SystemControlRegister mask the error which is going to be injected |
| 960 |
! SYStem HW Error |
| 961 |
set 0x01f80000, %l2 |
| 962 |
set 0x2000, %l3 ! syshemsk bit (bit 13) |
| 963 |
or %l1, %l3, %l3 |
| 964 |
st %l3, [%l2] |
| 965 |
|
| 966 |
! inject SYSstem HW error |
| 967 |
! set to 1 bit 0 syshe in Error&ResetStatusRegister |
| 968 |
set 0x01f800b0, %l2 |
| 969 |
set 0x20, %l3 ! syshe bit (bit 5) |
| 970 |
st %l3, [%l2] |
| 971 |
|
| 972 |
! int lev 1 should be pending |
| 973 |
! set 0x01f80050, %l2 |
| 974 |
set 0x01f80048, %l2 |
| 975 |
ld [%l2], %l2 |
| 976 |
andcc %l2, 2, %l2 |
| 977 |
bz ERROR_FAIL |
| 978 |
nop |
| 979 |
|
| 980 |
! Rollback Error&ResetStatusRegister |
| 981 |
set 0x01f800b0, %l2 |
| 982 |
set 0x0, %l3 |
| 983 |
st %l3, [%l2] |
| 984 |
|
| 985 |
! nop |
| 986 |
! nop |
| 987 |
! nop |
| 988 |
! nop |
| 989 |
! nop |
| 990 |
! nop |
| 991 |
! nop |
| 992 |
! nop |
| 993 |
|
| 994 |
|
| 995 |
ERROR_OK: |
| 996 |
mov 0, %i0 ! i0 = 0 -> OK |
| 997 |
ba ERROR_END |
| 998 |
nop |
| 999 |
|
| 1000 |
ERROR_FAIL: |
| 1001 |
mov 1, %i0 ! i0 = 1 -> NOK |
| 1002 |
|
| 1003 |
ERROR_END: |
| 1004 |
! clear int lev 1 pending |
| 1005 |
set 0x01f80050, %l2 |
| 1006 |
set 0x2, %l3 |
| 1007 |
st %l3, [%l2] |
| 1008 |
|
| 1009 |
! Disable Error Write (ewe bit20) in TestControlRegister |
| 1010 |
! ewe= 0 |
| 1011 |
set 0x01f800d0, %l1 |
| 1012 |
clr %l2 |
| 1013 |
st %l2, [%l1] |
| 1014 |
|
| 1015 |
! restore InterruptMaskRegister |
| 1016 |
set 0x01f8004c, %l2 |
| 1017 |
st %l0, [%l2] |
| 1018 |
|
| 1019 |
! restore SystemControlRegister |
| 1020 |
set 0x01f80000, %l2 |
| 1021 |
st %l1, [%l2] |
| 1022 |
|
| 1023 |
! nop |
| 1024 |
! nop |
| 1025 |
ret |
| 1026 |
! nop |
| 1027 |
! nop |
| 1028 |
restore |
| 1029 |
nop |
| 1030 |
! nop |
| 1031 |
|
| 1032 |
"); |
| 1033 |
|
| 1034 |
|
| 1035 |
/****************************************************************************** |
| 1036 |
* |
| 1037 |
* eosEepromCheckSumTest - perform the CRC test on EEPROM of LA695E-CORE board |
| 1038 |
* |
| 1039 |
* |
| 1040 |
* RETURNS: |
| 1041 |
* EEPROM_TEST_OK |
| 1042 |
* EEPROM_TEST_NOK |
| 1043 |
* |
| 1044 |
*/ |
| 1045 |
|
| 1046 |
int eosEepromCheckSumTest (void) |
| 1047 |
{ |
| 1048 |
|
| 1049 |
unsigned short crc; |
| 1050 |
unsigned int lenApp; |
| 1051 |
unsigned short crcApp; |
| 1052 |
unsigned int* pEE; |
| 1053 |
unsigned char ch; |
| 1054 |
unsigned int temp; |
| 1055 |
unsigned int status; |
| 1056 |
int i; |
| 1057 |
|
| 1058 |
lenApp =EEPROM_LEN_EXE; |
| 1059 |
crcApp =*((unsigned int*)(EEPROM_START_EXE + EEPROM_LEN_EXE - 4)); |
| 1060 |
pEE =(unsigned int*)(EEPROM_START_EXE); |
| 1061 |
for (i=0, crc=0xffff; i< lenApp-8; i += 4,pEE++ ) |
| 1062 |
{ |
| 1063 |
temp =*pEE; |
| 1064 |
ch =(unsigned char)((temp>>24) & 0x000000ff); |
| 1065 |
crc =crcComp(&ch,crc); |
| 1066 |
ch =(unsigned char)((temp>>16) & 0x000000ff); |
| 1067 |
crc =crcComp(&ch,crc); |
| 1068 |
ch =(unsigned char)((temp>>8) & 0x000000ff); |
| 1069 |
crc =crcComp(&ch,crc); |
| 1070 |
ch =(unsigned char)(temp & 0x000000ff); |
| 1071 |
crc =crcComp(&ch,crc); |
| 1072 |
} |
| 1073 |
|
| 1074 |
if (crc == crcApp) |
| 1075 |
{ |
| 1076 |
status =EEPROM_TEST_OK; |
| 1077 |
} |
| 1078 |
else |
| 1079 |
{ |
| 1080 |
status =EEPROM_TEST_NOK; |
| 1081 |
} |
| 1082 |
return(status); |
| 1083 |
|
| 1084 |
} |
| 1085 |
|
| 1086 |
|
| 1087 |
/*****************************************************************************/ |
| 1088 |
/* @Function: PD_ifcrcComp */ |
| 1089 |
/* @Purpose : */ |
| 1090 |
/* This function calculates the CRC. */ |
| 1091 |
/* */ |
| 1092 |
/* @@ */ |
| 1093 |
/* @Parameter Name @Mode @Description */ |
| 1094 |
/* @@ */ |
| 1095 |
/*****************************************************************************/ |
| 1096 |
unsigned short crcComp (unsigned char* adrs, unsigned short Crc) |
| 1097 |
{ |
| 1098 |
unsigned int Crc16Value; |
| 1099 |
|
| 1100 |
Crc16Value =Crc; |
| 1101 |
// Calculating the CRC16 by using a LookUp table |
| 1102 |
Crc16Value = (unsigned int)(Crc16Value << 8) ^ |
| 1103 |
(unsigned int)(Crc_lookup[ (unsigned int) ( ((Crc16Value >> 8) & |
| 1104 |
0xFF) ^ *adrs) ]); |
| 1105 |
return ((unsigned short)Crc16Value); |
| 1106 |
|
| 1107 |
} |
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