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kusanagi |
1.1 |
/**************************************************************************** |
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/* F i l e D a t a |
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/* |
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/* Module : BootStrap |
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/* C.I. No. : |
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/* $Revision: 1.1.1.1 $ |
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/* $Date: 2003/08/04 09:40:21 $ |
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/* Belonging to : |
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/* : |
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/* $RCSfile: promload.c,v $ |
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/* Program Type : |
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/* Sub-modules : |
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/* |
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/**************************************************************************** |
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/* S W D e v e l o p m e n t E n v i r o n m e n t |
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/* |
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/* Host system : |
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/* SW Compiler : |
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/* Author Daniele Cortesi $ |
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/* : |
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/**************************************************************************** |
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/* U p d a t i n g |
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/* 10/07/20000 - Created |
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/* |
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/* $Log: promload.c,v $ |
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/* Revision 1.1.1.1 2003/08/04 09:40:21 sebastiani |
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/* Imported sources laben rel. 19.06.2003 integrated with pam2 |
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/* |
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/* Revision 1.5 2002/07/25 09:24:46 zulia |
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/* FM PROM - Configurated version |
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/* |
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/* Revision 1.4 2002/07/16 07:12:50 zulia |
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/* setup for 4MB |
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/* |
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/* Revision 1.3 2002/05/09 08:16:34 zulia |
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/* * acceptance release |
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/* |
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/* |
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/*****************************************************************************/ |
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/*****************************************************************************/ |
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/* Copyright (C) 2000 LABEN all rights reserved */ |
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/*****************************************************************************/ |
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/*============================= Include File ================================*/ |
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#include <src/BootStrap/Boot/la695eEos.h> |
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#include <src/BootStrap/Boot/la695e.h> |
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/*****************************************************************************/ |
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/*============================= Local define ================================*/ |
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/** GPI data Register (to see if the test connector is connected) **/ |
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#define GPI_DAT_REG 0xac |
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/** Pin 0 of GPI (If ==0x08 TEST CONNECTOR connected) **/ |
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#define TEST_PIN 0x08 |
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#define USR 0xe8/4 |
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#define TXA 0xe0/4 |
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#define ERSR 0xb0/4 |
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#define SECMAX 32 |
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#define SECNAME 16 |
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typedef struct sectype { |
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unsigned int paddr; |
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unsigned int raddr; |
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unsigned int len; |
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unsigned int comp; |
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unsigned char name[SECNAME]; |
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}tt; |
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extern char filename[]; |
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extern struct sectype sections[]; |
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extern int prot; |
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void |
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putsx(s) |
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unsigned char *s; |
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{ |
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volatile unsigned int *mec = (unsigned int *) 0x1f80000; |
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while (s[0] != 0) { |
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while ((mec[USR] & 4) == 0); |
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mec[TXA] = *s; |
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s++; |
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} |
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} |
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memprotect(start, end) |
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unsigned int start, end; |
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{ |
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int sbr, ser; |
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volatile unsigned int *mec = (unsigned int *) 0x1f80000; |
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mec[0x24 / 4] = ((end & 0x007fffff) >> 2); |
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mec[0x20 / 4] = ((start & 0x007fffff) >> 2) | 0x01800000; |
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} |
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extern int stack; |
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set_stack(top) |
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unsigned int top; |
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{ |
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asm(" |
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retl |
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mov %o0, %sp |
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"); |
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} |
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__main() |
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{ |
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} |
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/*****************************************************************************/ |
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/*========================== Global Function prototype ======================*/ |
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int eosBoardTest (void) ; |
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int eosEepromCheckSumTest (void); |
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/*============================ Extern Variables =============================*/ |
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extern int ramsize, etext, freq; |
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void clean(); |
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extern int Decode(); |
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extern char configmsg[]; |
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main() |
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{ |
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unsigned char *p; |
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int paddr, raddr, len, secnum; |
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void (*prog) (); |
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int (*func) (); |
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char pbuf[8192]; |
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volatile unsigned int *mec = (unsigned int *) 0x1f80000; |
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prog = (void *) sections[0].paddr; |
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putsx("\n\n\r ERC32 boot loader v1.1\n\n\r"); |
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putsx(configmsg); |
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putsx("\n\r"); |
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mmov(clean,pbuf,0x100); |
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putsx(" initialising ram memory\n\r"); |
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func = (void *)pbuf; |
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func(0x2000000,ramsize - 0x10000); |
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secnum = 0; |
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/**------------------------------------------------------------- |
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**---- check on TEST CONNECTOR --> |
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**---- if not CONNECTED load APPLICATION |
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**---- else load MONITOR(section 0,1) |
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**---- |
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**------------------------------------------------------------- |
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**/ |
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if (mec[GPI_DAT_REG / 4] & TEST_PIN) |
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{ |
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/** TEST CONNECTOR not connected **/ |
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putsx("\n\r ************ STARTING APPLICATION **********\n\r"); |
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mec[0x20 / 4] = 0; |
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mec[0x24 / 4] = 0; |
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mec[0x14 / 4] =0x0000001f; |
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prog = (void *) RAM_START_EXE; |
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//prog =(void*)0x02001000; |
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raddr =EEPROM_START_EXE; |
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paddr =RAM_START_EXE; |
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len =EEPROM_LEN_EXE; |
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putsx(" Loading .text \n\r"); |
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putsx(" Loding .data \n\r"); |
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func = (void *)((int)mmov + (int)pbuf - (int)clean); |
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func(raddr, paddr,len); |
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putsx("\n\r End\n\r"); |
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*((int *) (RAM_START_EXE + 0x7e0)) = freq; |
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} |
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else |
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{ |
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/** TEST CONNECTOR connected **/ |
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putsx("\n\r ************* STARTING MONITOR **************\n\r"); |
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while (sections[secnum].paddr) |
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{ |
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paddr = sections[secnum].paddr; |
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raddr = sections[secnum].raddr; |
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len = sections[secnum].len; |
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putsx(" loading "); |
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putsx(sections[secnum].name); |
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putsx("\n\r"); |
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func = (void *)((int)mmov + (int)pbuf - (int)clean); |
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func(raddr, paddr,len); |
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secnum++; |
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} |
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if (prot) |
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{ |
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memprotect(sections[0].paddr + 0x1000, |
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sections[0].paddr + sections[0].len); |
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} |
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putsx("\n\r End\n\r"); |
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*((int *) (sections[0].paddr + 0x7e0)) = freq; |
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} |
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putsx("\n\r ****** Program running ******\n\r"); |
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prog(); |
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} |
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void clean(paddr,len) |
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double *paddr; |
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int len; |
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{ |
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len >>=3; |
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while (len >= 0) { |
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paddr[len] = 0; |
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len--; |
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} |
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} |
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mmov(raddr,paddr,len) |
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int *raddr, *paddr; |
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int len; |
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{ |
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len >>=2; |
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while (len >= 0) { |
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paddr[len] = raddr[len]; |
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len--; |
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} |
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} |
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/*****************************************************************************/ |
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/*=================== I N T E R N A L F U N C T I O N S ==================*/ |
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/***************************************************************************** |
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* |
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* eosBoardTest - test TSC695E of LA695E-CORE board |
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* |
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* This routine perform the test of TSC695E by using the testing facility |
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* offered by the MEC Test Control Register |
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* |
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* The routine does not use RAM |
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* The Interrupt Test is not done because it needs RAM |
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* |
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* RETURNS: |
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* BIT_OK |
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* BIT_NOK_EDAC_TEST |
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* BIT_NOK_PARITY_TEST |
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* BIT_NOK_INTERRUPT_TEST never |
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* BIT_NOK_ERROR_TEST |
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* any OR combination of BIT_NOK_xx |
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* |
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* |
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*/ |
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int eosBoardTest (void) |
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{ |
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unsigned int register eosBoardTestResult; |
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unsigned int tmpData; |
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eosBoardTestResult =0; |
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if (edacTest()!= OK) |
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eosBoardTestResult |=BIT_NOK_EDAC_TEST; |
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/* |
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if (parityTest()!= OK) |
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eosBoardTestResult |=BIT_NOK_PARITY_TEST; |
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*/ |
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if (interruptTest()!= OK) |
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eosBoardTestResult |=BIT_NOK_INTERRUPT_TEST ; |
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if (errorTest()!= OK) |
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eosBoardTestResult |=BIT_NOK_ERROR_TEST; |
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return (eosBoardTestResult); |
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} |
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/******************************************************************************* |
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* |
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* edacTest - test EDAC functionalities |
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* |
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* |
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*/ |
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int edacTest (void) |
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{ |
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if (edacSefTest() != OK) |
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return (NOK) ; |
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if (edacDefTest() != OK) |
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return (NOK); |
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if (edacNoErrorTest() != OK) |
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return (NOK); |
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return(OK) ; |
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} |
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/******************************************************************************* |
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* |
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* edacSefTest - test the EDAC capability to detect and correct a single error |
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* |
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* RETURNS: |
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* OK |
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* NOK |
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*/ |
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asm(" |
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.text |
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.global _edacSefTest |
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_edacSefTest: |
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save ! New window |
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! Enable traps |
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mov %psr, %l0 ! %l0 saved psr |
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or %l0, 0x20, %l1 ! psr.et=1 |
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mov %l1, %psr |
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nop |
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nop |
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nop |
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! EDAC enable |
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! set to 1 rec bit (14) of MemoryConfigurationRegister |
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set 0x01f80010, %l1 |
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ld [%l1], %l2 |
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set 0x00004000, %l3 |
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or %l2, %l3, %l2 |
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st %l2, [%l1] |
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! clear interrupt level 6 EDAC SEF |
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! set to 1 bit 6 of InterruptClearRegister */ |
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set 0x01f80050, %l1 |
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set 0x00000040, %l2 |
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st %l2, [%l1] |
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! initialise test locations |
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! GM |
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set 0x02000000, %l1 ! first RAM valid address |
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st %g0, [%l1] |
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set 0x023ffffc, %l2 ! last RAM valid address (4MB) |
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st %g0, [%l2] |
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set 0x01f800d0, %l2 ! %l2 TestControlRegister |
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set 2, %l3 ! %l3 loop counter |
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SEF_LOOP: |
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! Set EDAC test bits in TestControlRegister |
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! et = 1 meaning EDAC test enabled |
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! cb = 0010000 check bit of pattern 0x0 with 1 bit failed |
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! (cb correct is 0010100) |
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ld [%l2] , %l4 |
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set 0x00020010, %l5 |
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or %l4 , %l5 , %l4 |
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st %l4 , [%l2] |
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! store test value in test location |
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clr %l4 |
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st %l4 , [%l1] |
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! Set ET =0 in TestControlRegister |
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ld [%l2] , %l4 |
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set 0x00020000, %l5 |
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andn %l4 , %l5 , %l4 |
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st %l4 , [%l2] |
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! read back test location |
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ld [%l1] , %l4 |
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! If read back value is not the written value i.e. 0 then jump |
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cmp %l4, 0 |
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bne SEF_LOOP_TEST |
376 |
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nop |
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SEF_INPT_PEND_TEST: |
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! test if intp level 6 is pending |
380 |
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set 0x01f80048, %l5 ! InterruptPendingRegister |
381 |
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ld [%l5], %l5 |
382 |
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andcc %l5, 0x40, %l5 ! 0x40 mask for int lev 6 |
383 |
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bnz SEF_OK |
384 |
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nop |
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386 |
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SEF_LOOP_TEST: |
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! dove e' implementato la scansione della memoria ??????? |
388 |
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set 0x023ffffc, %l1 ! %l1 last RAM valid address (4MB) |
389 |
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subcc %l3, 1, %l3 |
390 |
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bnz SEF_LOOP |
391 |
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nop |
392 |
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SEF_FAIL : |
394 |
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mov 1, %i0 ! i0 = 1 -> NOK |
395 |
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ba SEF_END |
396 |
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nop |
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398 |
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SEF_OK : |
399 |
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mov 0, %i0 ! i0 = 0 -> OK |
400 |
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401 |
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SEF_END : |
402 |
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! restore psr |
403 |
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mov %l0, %psr |
404 |
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nop |
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nop |
406 |
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nop |
407 |
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408 |
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ret |
409 |
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restore |
410 |
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nop |
411 |
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412 |
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") ; |
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414 |
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415 |
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416 |
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417 |
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/******************************************************************************* |
418 |
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* |
419 |
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* edacDefTest - test the EDAC capability to detect a double error |
420 |
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* |
421 |
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* RETURNS: |
422 |
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* OK |
423 |
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* NOK |
424 |
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* |
425 |
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*/ |
426 |
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|
|
427 |
|
|
asm(" |
428 |
|
|
.text |
429 |
|
|
.global _edacDefTest |
430 |
|
|
|
431 |
|
|
_edacDefTest: |
432 |
|
|
|
433 |
|
|
save ! New window |
434 |
|
|
set 0x02000010, %l6 !TBD for debug |
435 |
|
|
|
436 |
|
|
! Enable traps |
437 |
|
|
mov %psr, %l0 ! %l0 saved psr |
438 |
|
|
or %l0, 0x20, %l1 ! psr.et=1 |
439 |
|
|
mov %l1, %psr |
440 |
|
|
nop |
441 |
|
|
nop |
442 |
|
|
nop |
443 |
|
|
! st %l1, [%l6] !TBD for debug |
444 |
|
|
|
445 |
|
|
! sethi %hi(TRAP_TABLE_TEST), %l6 ! Sets trap table for test |
446 |
|
|
! mov %l6, %tbr |
447 |
|
|
|
448 |
|
|
! EDAC enable |
449 |
|
|
! set to 1 rec bit (14) of MemoryConfigurationRegister |
450 |
|
|
set 0x01f80010, %l1 |
451 |
|
|
ld [%l1], %l2 |
452 |
|
|
set 0x00004000, %l3 |
453 |
|
|
or %l2, %l3, %l2 |
454 |
|
|
st %l2, [%l1] |
455 |
|
|
! st %l2, [%l6] !TBD for debug |
456 |
|
|
|
457 |
|
|
! Mask IU Error Mode in SystemControlRegister |
458 |
|
|
! set to 1 iuemmsk bit 5 |
459 |
|
|
set 0x01f80000, %l1 |
460 |
|
|
ld [%l1], %l2 |
461 |
|
|
or %l2, 0x20, %l2 |
462 |
|
|
st %l2, [%l1] |
463 |
|
|
! st %l2, [%l6] !TBD for debug |
464 |
|
|
|
465 |
|
|
set 0x01f800d0, %l2 ! %l2 TestControlRegister |
466 |
|
|
set 2, %l3 ! %l3 loop counter |
467 |
|
|
set 0x01f800a0, %l7 ! %l7 SystemFaultStatusRegister |
468 |
|
|
|
469 |
|
|
! initialise test locations |
470 |
|
|
! GM |
471 |
|
|
set 0x02000000, %l1 ! first RAM valid address |
472 |
|
|
st %g0, [%l1] |
473 |
|
|
! end GM |
474 |
|
|
|
475 |
|
|
DEF_LOOP: |
476 |
|
|
! Set EDAC test bits in TestControlRegister |
477 |
|
|
! et= 1 meaning EDAC test enabled |
478 |
|
|
! cb= 0000000 check bit of pattern 0x00000000 with two bits failed TBD |
479 |
|
|
! (cb correct is 0010100) |
480 |
|
|
ld [%l2] , %l4 |
481 |
|
|
set 0x0002007f, %l5 |
482 |
|
|
andn %l4 , %l5 , %l4 ! clear et and cb |
483 |
|
|
set 0x00020000, %l5 |
484 |
|
|
or %l4 , %l5 , %l4 ! set cb |
485 |
|
|
st %l4 , [%l2] |
486 |
|
|
! st %l4, [%l6] !TBD for debug |
487 |
|
|
|
488 |
|
|
! store test value in test location |
489 |
|
|
clr %l4 |
490 |
|
|
st %l4 , [%l1] |
491 |
|
|
! st %l4, [%l6] !TBD for debug |
492 |
|
|
|
493 |
|
|
! Set et=0 and cb=0 in TestControlRegister |
494 |
|
|
ld [%l2] , %l4 |
495 |
|
|
set 0x0002007f, %l5 |
496 |
|
|
andn %l4 , %l5 , %l4 |
497 |
|
|
st %l4 , [%l2] |
498 |
|
|
! st %l4, [%l6] !TBD for debug |
499 |
|
|
|
500 |
|
|
! read back test location |
501 |
|
|
ld [%l1] , %l4 |
502 |
|
|
nop |
503 |
|
|
nop |
504 |
|
|
|
505 |
|
|
!Double Error Should have been detected |
506 |
|
|
!Read System Fault Status register |
507 |
|
|
ld [%l7] , %l4 |
508 |
|
|
! st %l4, [%l6] !TBD for debug |
509 |
|
|
and %l4, 0x7c, %l4 ! GM was 0x78 |
510 |
|
|
cmp %l4, 0x3c ! GM was 0x38 |
511 |
|
|
be DEF_OK |
512 |
|
|
nop |
513 |
|
|
|
514 |
|
|
DEF_LOOP_TEST : |
515 |
|
|
set 0x023ffffc, %l1 ! last RAM valid address (4MB) |
516 |
|
|
subcc %l3, 1, %l3 |
517 |
|
|
bnz DEF_LOOP |
518 |
|
|
nop |
519 |
|
|
|
520 |
|
|
DEF_FAIL : |
521 |
|
|
mov 1, %i0 ! i0 = 1 -> NOK |
522 |
|
|
ba DEF_END |
523 |
|
|
nop |
524 |
|
|
|
525 |
|
|
DEF_OK : |
526 |
|
|
mov 0x7c, %l4 ! 18-sep-01 GM reset System Fault Status register |
527 |
|
|
st %l4, [%l7] ! "" GM |
528 |
|
|
|
529 |
|
|
mov 0, %i0 ! i0 = 0 -> OK |
530 |
|
|
|
531 |
|
|
DEF_END : |
532 |
|
|
|
533 |
|
|
! sethi %hi(TRAP_TABLE), %l6 ! Restores default trap table |
534 |
|
|
! mov %l6, %tbr |
535 |
|
|
|
536 |
|
|
! restore psr |
537 |
|
|
mov %l0, %psr |
538 |
|
|
nop |
539 |
|
|
nop |
540 |
|
|
nop |
541 |
|
|
|
542 |
|
|
ret |
543 |
|
|
restore |
544 |
|
|
nop |
545 |
|
|
|
546 |
|
|
") ; |
547 |
|
|
|
548 |
|
|
|
549 |
|
|
/******************************************************************************* |
550 |
|
|
* |
551 |
|
|
* edacNoErrorTest - test the EDAC behaviour in case of no error |
552 |
|
|
* |
553 |
|
|
* RETURNS: |
554 |
|
|
* OK |
555 |
|
|
* NOK |
556 |
|
|
*/ |
557 |
|
|
|
558 |
|
|
asm(" |
559 |
|
|
.text |
560 |
|
|
.global _edacNoErrorTest |
561 |
|
|
|
562 |
|
|
_edacNoErrorTest: |
563 |
|
|
save ! New window |
564 |
|
|
set 0x02000010, %l6 !TBD for debug |
565 |
|
|
|
566 |
|
|
! Enable traps |
567 |
|
|
mov %psr, %l0 ! %l0 saved psr |
568 |
|
|
or %l0, 0x20, %l1 ! psr.et=1 |
569 |
|
|
mov %l1, %psr |
570 |
|
|
|
571 |
|
|
! EDAC enable |
572 |
|
|
! set to 1 rec bit (14) of MemoryConfigurationRegister |
573 |
|
|
set 0x01f80010, %l1 |
574 |
|
|
ld [%l1], %l2 |
575 |
|
|
set 0x00004000, %l3 |
576 |
|
|
or %l2, %l3, %l2 |
577 |
|
|
st %l2, [%l1] |
578 |
|
|
|
579 |
|
|
! clear interrupt level 6 EDAC SEF |
580 |
|
|
! set to 1 bit 6 of InterruptClearRegister |
581 |
|
|
set 0x01f80050, %l1 |
582 |
|
|
set 0x00000040, %l2 |
583 |
|
|
st %l2, [%l1] |
584 |
|
|
|
585 |
|
|
set 0x01f80048, %l2 ! %l2 InterruptPendingRegister |
586 |
|
|
set 2, %l3 ! %l3 loop counter |
587 |
|
|
|
588 |
|
|
! initialise test locations |
589 |
|
|
! GM |
590 |
|
|
set 0x02000000, %l1 ! first RAM valid address |
591 |
|
|
! st %g0, [%l1] !GP 13-12-01 executed after |
592 |
|
|
! end GM |
593 |
|
|
|
594 |
|
|
NOERROR_LOOP: |
595 |
|
|
! store test value in test location |
596 |
|
|
clr %l4 |
597 |
|
|
st %l4 , [%l1] |
598 |
|
|
nop |
599 |
|
|
nop |
600 |
|
|
|
601 |
|
|
! read back |
602 |
|
|
ld [%l1] , %l5 |
603 |
|
|
|
604 |
|
|
! compare written value with the read back one |
605 |
|
|
cmp %l4 , %l5 |
606 |
|
|
bne NOERROR_LOOP_TEST |
607 |
|
|
nop |
608 |
|
|
|
609 |
|
|
NOERROR_INTP_PEND_TEST: |
610 |
|
|
ld [%l2], %l5 |
611 |
|
|
st %l5, [%l6] !TBD for debug |
612 |
|
|
andcc %l5, 0x40, %l5 ! 0x40 mask for int lev 6 |
613 |
|
|
bz NOERROR_OK |
614 |
|
|
nop |
615 |
|
|
|
616 |
|
|
NOERROR_LOOP_TEST: |
617 |
|
|
set 0x023ffffc, %l1 ! last RAM valid address (4MB) |
618 |
|
|
subcc %l3, 1, %l3 |
619 |
|
|
bnz NOERROR_LOOP |
620 |
|
|
nop |
621 |
|
|
|
622 |
|
|
NOERROR_FAIL : |
623 |
|
|
mov 1, %i0 ! i0 = 1 -> NOK |
624 |
|
|
ba NOERROR_END |
625 |
|
|
nop |
626 |
|
|
|
627 |
|
|
NOERROR_OK : |
628 |
|
|
mov 0, %i0 ! i0 = 0 -> OK |
629 |
|
|
|
630 |
|
|
|
631 |
|
|
NOERROR_END : |
632 |
|
|
! restore psr |
633 |
|
|
mov %l0, %psr |
634 |
|
|
nop |
635 |
|
|
nop |
636 |
|
|
nop |
637 |
|
|
|
638 |
|
|
ret |
639 |
|
|
restore |
640 |
|
|
nop |
641 |
|
|
|
642 |
|
|
"); |
643 |
|
|
|
644 |
|
|
|
645 |
|
|
/************************************************************************** |
646 |
|
|
* |
647 |
|
|
* edacTh - |
648 |
|
|
* |
649 |
|
|
* RETURNS |
650 |
|
|
* |
651 |
|
|
*/ |
652 |
|
|
|
653 |
|
|
asm(" |
654 |
|
|
.text |
655 |
|
|
.global _edacTh |
656 |
|
|
|
657 |
|
|
_edacTh: |
658 |
|
|
|
659 |
|
|
jmp %l2 ! Jump to nPC |
660 |
|
|
rett %l2 + 4 |
661 |
|
|
nop |
662 |
|
|
") ; |
663 |
|
|
|
664 |
|
|
|
665 |
|
|
/******************************************************************************* |
666 |
|
|
* |
667 |
|
|
* interruptTest - interrupt test |
668 |
|
|
* |
669 |
|
|
* DESCRIPTION |
670 |
|
|
* Saves interrupts status, switches to the test trap table, sets interrupt test |
671 |
|
|
* mode and uses the IFR to force interrupts. The routine checks if the asynchronous |
672 |
|
|
* trap routine starts. |
673 |
|
|
* Finally restores interrupt status, the previous trap table (default) and returns the |
674 |
|
|
* result OK (0) or NOK (1). The bootstrap log record is updated in builtInTest. |
675 |
|
|
* |
676 |
|
|
*/ |
677 |
|
|
|
678 |
|
|
asm(" |
679 |
|
|
.text |
680 |
|
|
.global _interruptTest |
681 |
|
|
|
682 |
|
|
_interruptTest: |
683 |
|
|
save ! New window |
684 |
|
|
|
685 |
|
|
! enable traps |
686 |
|
|
mov %psr, %l0 ! %l0 saved psr |
687 |
|
|
and %l0, 0xfffff0ff, %l1 ! Clear pil bits: enable all traps |
688 |
|
|
or %l1, 0x20, %l1 ! psr.et=1 |
689 |
|
|
mov %l1, %psr |
690 |
|
|
nop |
691 |
|
|
nop |
692 |
|
|
nop |
693 |
|
|
|
694 |
|
|
set 0x01f80044, %l3 |
695 |
|
|
set 0x01f, %l1 |
696 |
|
|
st %l1,[%l3] ! Set all ext INT to edge |
697 |
|
|
|
698 |
|
|
! save IMR |
699 |
|
|
set 0x01f8004c, %l3 ! %l3 InterruptMaskReg |
700 |
|
|
ld [%l3], %l7 ! saves interrupt mask reg to on l3 |
701 |
|
|
|
702 |
|
|
! change TBR |
703 |
|
|
! sethi %hi(TRAP_TABLE_TEST), %l4 ! trap table for test |
704 |
|
|
! mov %l4, %tbr |
705 |
|
|
|
706 |
|
|
! enable write on IFR |
707 |
|
|
set 0x01f800d0, %l3 ! %l3 TestControlReg |
708 |
|
|
ld [%l3], %l5 ! TestControlReg value |
709 |
|
|
set 0x00080000, %l6 ! it bit = 1 |
710 |
|
|
or %l5, %l6, %l5 ! sets et bit |
711 |
|
|
st %l5, [%l3] ! updates TestControlReg |
712 |
|
|
|
713 |
|
|
! loop for the actual int test tr |
714 |
|
|
mov %g0, %o0 ! resets the result flag |
715 |
|
|
set 0x7ffe, %l4 ! bit mask for IMR |
716 |
|
|
set 0x8000, %l5 ! bit mask for IFR |
717 |
|
|
mov %l4, %l6 ! aux bit mask for IMR (0x7ffe) |
718 |
|
|
|
719 |
|
|
INT_CHECK_LOOP: |
720 |
|
|
set 0x01f8004c, %l3 ! %l3 InterruptMaskRegister |
721 |
|
|
st %l4, [%l3] ! unmask the i-th int to test |
722 |
|
|
set 0x01f80054, %l3 ! %l3 InterruptForceRegister |
723 |
|
|
st %l5, [%l3] ! force i-th interrupt |
724 |
|
|
nop |
725 |
|
|
nop |
726 |
|
|
nop |
727 |
|
|
nop |
728 |
|
|
nop |
729 |
|
|
nop |
730 |
|
|
nop |
731 |
|
|
nop |
732 |
|
|
nop |
733 |
|
|
nop |
734 |
|
|
nop |
735 |
|
|
nop |
736 |
|
|
srl %l5, 1, %l5 ! new mask for the next int (IFR) |
737 |
|
|
not %l5, %l4 |
738 |
|
|
and %l4, %l6, %l4 ! new mask for the next int (IMR) |
739 |
|
|
subcc %l5, 1, %g0 ! compare end of loop |
740 |
|
|
bnz INT_CHECK_LOOP |
741 |
|
|
nop |
742 |
|
|
|
743 |
|
|
! result test |
744 |
|
|
set 0xfffe, %l5 |
745 |
|
|
subcc %o0, %l5, %g0 ! if %o0 == 0xfffe, test OK, else NOK |
746 |
|
|
be INT_OK |
747 |
|
|
nop |
748 |
|
|
|
749 |
|
|
INT_FAIL: |
750 |
|
|
mov 1, %i0 ! i0 = 1 -> NOK |
751 |
|
|
ba INT_END |
752 |
|
|
nop |
753 |
|
|
INT_OK: |
754 |
|
|
mov 0, %i0 ! i0 = 0 -> OK |
755 |
|
|
|
756 |
|
|
INT_END: |
757 |
|
|
! clear any pending int |
758 |
|
|
set 0x01f80050, %l3 ! %l3 InterruptClearRegister |
759 |
|
|
set 0xfffe, %l5 |
760 |
|
|
st %l5, [%l3] ! resets ICR (0xfffe) |
761 |
|
|
|
762 |
|
|
! restore int mask reg status |
763 |
|
|
set 0x01f8004c, %l3 ! %l3 InterruptMaskRegister |
764 |
|
|
st %l7, [%l3] ! restores interrupt mask reg to on l3 |
765 |
|
|
|
766 |
|
|
! disable write on IFR |
767 |
|
|
set 0x01f800d0, %l3 ! %l3 TestControlRegister |
768 |
|
|
ld [%l3] , %l5 ! TCR value |
769 |
|
|
set 0x0016007f, %l6 ! et bit = 0 |
770 |
|
|
and %l5 , %l6 , %l5 ! resets et bit |
771 |
|
|
st %l5 , [%l3] ! updates the TCR |
772 |
|
|
|
773 |
|
|
! restore trap table |
774 |
|
|
! sethi %hi(TRAP_TABLE), %l4 ! default trap table |
775 |
|
|
! mov %l4, %tbr |
776 |
|
|
|
777 |
|
|
! restore psr |
778 |
|
|
mov %l0, %psr |
779 |
|
|
nop |
780 |
|
|
nop |
781 |
|
|
nop |
782 |
|
|
|
783 |
|
|
ret |
784 |
|
|
restore |
785 |
|
|
nop |
786 |
|
|
|
787 |
|
|
"); |
788 |
|
|
|
789 |
|
|
/******************************************************************************* |
790 |
|
|
* |
791 |
|
|
* intpTh - |
792 |
|
|
* |
793 |
|
|
* RETURNS |
794 |
|
|
* |
795 |
|
|
*/ |
796 |
|
|
|
797 |
|
|
asm(" |
798 |
|
|
.text |
799 |
|
|
.global _intpTh |
800 |
|
|
|
801 |
|
|
_intpTh: |
802 |
|
|
rd %tbr, %l3 ! rdtbr trap table reg |
803 |
|
|
|
804 |
|
|
! prepare int index |
805 |
|
|
srl %l3, 4, %l3 |
806 |
|
|
and %l3, 0x000000ff, %l3 |
807 |
|
|
sub %l3, 16, %l3 |
808 |
|
|
|
809 |
|
|
set 0x00000001, %l4 |
810 |
|
|
sll %l4, %l3, %l4 ! set i-th int bit |
811 |
|
|
or %i0, %l4, %i0 ! output paramenter |
812 |
|
|
|
813 |
|
|
jmp %l2 ! Jump to nPC |
814 |
|
|
rett %l2 + 4 |
815 |
|
|
nop |
816 |
|
|
") ; |
817 |
|
|
|
818 |
|
|
|
819 |
|
|
|
820 |
|
|
|
821 |
|
|
/******************************************************************************* |
822 |
|
|
* |
823 |
|
|
* errorTest - test the capability of TSC695E to detect errors |
824 |
|
|
* |
825 |
|
|
* DESCRIPTION: |
826 |
|
|
* phylosophy : by enabling ewe bit in TestControlRegister, an error could be |
827 |
|
|
* simulated by setting to 1 the followings bits in Error&ResetStatusRegister, |
828 |
|
|
* iuem |
829 |
|
|
* iuhe |
830 |
|
|
* syshe |
831 |
|
|
* (fpuhe=1 causes nothing according to fig.13 DataSheetRevE TBD) |
832 |
|
|
* The check is done by verifing that int lev 1 ("Masked hardware errors") is |
833 |
|
|
* pending. |
834 |
|
|
* So first int lev 1 shall be masked then the simulated errors shall be masked |
835 |
|
|
* in SystemControlRegister setting to 1 the bits |
836 |
|
|
* iuemmsk |
837 |
|
|
* iuhemmsk |
838 |
|
|
* syshemsk |
839 |
|
|
* RETURNS: |
840 |
|
|
* OK |
841 |
|
|
* NOK |
842 |
|
|
* |
843 |
|
|
*/ |
844 |
|
|
asm(" |
845 |
|
|
.text |
846 |
|
|
.global _errorTest |
847 |
|
|
|
848 |
|
|
_errorTest: |
849 |
|
|
save ! New window |
850 |
|
|
|
851 |
|
|
! save InterruptMaskRegister |
852 |
|
|
set 0x01f8004c, %l0 |
853 |
|
|
ld [%l0], %l0 ! %l0 InterruptMaskRegister |
854 |
|
|
|
855 |
|
|
! save SystemControlRegister |
856 |
|
|
set 0x01f80000, %l1 |
857 |
|
|
ld [%l1], %l1 ! %l1 SystemControlRegister |
858 |
|
|
|
859 |
|
|
! clear Pending Interrupt |
860 |
|
|
set 0x01f80050, %l2 |
861 |
|
|
set 0xfffe, %l3 |
862 |
|
|
st %l3, [%l2] |
863 |
|
|
|
864 |
|
|
! mask all int levs |
865 |
|
|
set 0x01f8004c, %l2 |
866 |
|
|
set 0x00007ffe, %l3 |
867 |
|
|
st %l3, [%l2] |
868 |
|
|
|
869 |
|
|
! Enable Error Write (ewe bit20) in TestControlRegister |
870 |
|
|
! ewe= 1 meaning Write to Error&ResetStatusRegister enabled |
871 |
|
|
set 0x01f800d0, %l2 |
872 |
|
|
!set 0x00010000, %l3 GP 15-10-01 |
873 |
|
|
set 0x00100000, %l3!GP 10-12-01 si dovrebbe fare un OR non un set |
874 |
|
|
st %l3, [%l2] |
875 |
|
|
|
876 |
|
|
|
877 |
|
|
|
878 |
|
|
!****************** 1) IU Error Mode ********************* |
879 |
|
|
! In SystemControlRegister mask the error which is going to be injected |
880 |
|
|
! IU Error Mode |
881 |
|
|
set 0x01f80000, %l2 |
882 |
|
|
set 0x20, %l3 ! iuemmsk bit (bit 5) |
883 |
|
|
or %l1, %l3, %l3 |
884 |
|
|
st %l3, [%l2] |
885 |
|
|
|
886 |
|
|
! inject IU error |
887 |
|
|
! set to 1 bit 0 iuem in Error&ResetStatusRegister |
888 |
|
|
set 0x01f800b0, %l2 |
889 |
|
|
set 0x1, %l3 ! iuem bit (bit 0)!GP 10-12-01 si dovrebbe fare un OR non un set |
890 |
|
|
st %l3, [%l2] |
891 |
|
|
|
892 |
|
|
! int lev 1 should be pending |
893 |
|
|
! set 0x01f80050, %l2 |
894 |
|
|
set 0x01f80048, %l2 |
895 |
|
|
ld [%l2], %l2 |
896 |
|
|
andcc %l2, 2, %l2 |
897 |
|
|
bz ERROR_FAIL |
898 |
|
|
nop |
899 |
|
|
|
900 |
|
|
! Rollback Error&ResetStatusRegister |
901 |
|
|
set 0x01f800b0, %l2 |
902 |
|
|
set 0x0, %l3 |
903 |
|
|
st %l3, [%l2] |
904 |
|
|
|
905 |
|
|
! clear int lev 1 pending |
906 |
|
|
set 0x01f80050, %l2 |
907 |
|
|
set 0x2, %l3 |
908 |
|
|
st %l3, [%l2] |
909 |
|
|
|
910 |
|
|
|
911 |
|
|
|
912 |
|
|
|
913 |
|
|
|
914 |
|
|
!****************** 2) IU HW Error ********************* |
915 |
|
|
! restore initial value of SystemControlRegister |
916 |
|
|
set 0x01f80000, %l2 |
917 |
|
|
st %l1, [%l2] |
918 |
|
|
|
919 |
|
|
! In SystemControlRegister mask the error which is going to be injected |
920 |
|
|
! IU HW Error |
921 |
|
|
set 0x01f80000, %l2 |
922 |
|
|
set 0x80, %l3 ! iuhemmsk bit (bit 7) |
923 |
|
|
or %l1, %l3, %l3 |
924 |
|
|
st %l3, [%l2] |
925 |
|
|
|
926 |
|
|
! inject IU HW error |
927 |
|
|
! set to 1 bit 0 iuhe in Error&ResetStatusRegister |
928 |
|
|
set 0x01f800b0, %l2 |
929 |
|
|
set 0x2, %l3 ! iuhe bit (bit 1) |
930 |
|
|
st %l3, [%l2] |
931 |
|
|
|
932 |
|
|
! int lev 1 should be pending |
933 |
|
|
! set 0x01f80050, %l2 |
934 |
|
|
set 0x01f80048, %l2 |
935 |
|
|
ld [%l2], %l2 |
936 |
|
|
andcc %l2, 2, %l2 |
937 |
|
|
bz ERROR_FAIL |
938 |
|
|
nop |
939 |
|
|
|
940 |
|
|
! Rollback Error&ResetStatusRegister |
941 |
|
|
set 0x01f800b0, %l2 |
942 |
|
|
set 0x0, %l3 |
943 |
|
|
st %l3, [%l2] |
944 |
|
|
|
945 |
|
|
! clear int lev 1 pending |
946 |
|
|
set 0x01f80050, %l2 |
947 |
|
|
set 0x2, %l3 |
948 |
|
|
st %l3, [%l2] |
949 |
|
|
|
950 |
|
|
|
951 |
|
|
|
952 |
|
|
|
953 |
|
|
|
954 |
|
|
!****************** 3) SYStem HW Error ********************* |
955 |
|
|
! restore initial value of SystemControlRegister |
956 |
|
|
set 0x01f80000, %l2 |
957 |
|
|
st %l1, [%l2] |
958 |
|
|
|
959 |
|
|
! In SystemControlRegister mask the error which is going to be injected |
960 |
|
|
! SYStem HW Error |
961 |
|
|
set 0x01f80000, %l2 |
962 |
|
|
set 0x2000, %l3 ! syshemsk bit (bit 13) |
963 |
|
|
or %l1, %l3, %l3 |
964 |
|
|
st %l3, [%l2] |
965 |
|
|
|
966 |
|
|
! inject SYSstem HW error |
967 |
|
|
! set to 1 bit 0 syshe in Error&ResetStatusRegister |
968 |
|
|
set 0x01f800b0, %l2 |
969 |
|
|
set 0x20, %l3 ! syshe bit (bit 5) |
970 |
|
|
st %l3, [%l2] |
971 |
|
|
|
972 |
|
|
! int lev 1 should be pending |
973 |
|
|
! set 0x01f80050, %l2 |
974 |
|
|
set 0x01f80048, %l2 |
975 |
|
|
ld [%l2], %l2 |
976 |
|
|
andcc %l2, 2, %l2 |
977 |
|
|
bz ERROR_FAIL |
978 |
|
|
nop |
979 |
|
|
|
980 |
|
|
! Rollback Error&ResetStatusRegister |
981 |
|
|
set 0x01f800b0, %l2 |
982 |
|
|
set 0x0, %l3 |
983 |
|
|
st %l3, [%l2] |
984 |
|
|
|
985 |
|
|
! nop |
986 |
|
|
! nop |
987 |
|
|
! nop |
988 |
|
|
! nop |
989 |
|
|
! nop |
990 |
|
|
! nop |
991 |
|
|
! nop |
992 |
|
|
! nop |
993 |
|
|
|
994 |
|
|
|
995 |
|
|
ERROR_OK: |
996 |
|
|
mov 0, %i0 ! i0 = 0 -> OK |
997 |
|
|
ba ERROR_END |
998 |
|
|
nop |
999 |
|
|
|
1000 |
|
|
ERROR_FAIL: |
1001 |
|
|
mov 1, %i0 ! i0 = 1 -> NOK |
1002 |
|
|
|
1003 |
|
|
ERROR_END: |
1004 |
|
|
! clear int lev 1 pending |
1005 |
|
|
set 0x01f80050, %l2 |
1006 |
|
|
set 0x2, %l3 |
1007 |
|
|
st %l3, [%l2] |
1008 |
|
|
|
1009 |
|
|
! Disable Error Write (ewe bit20) in TestControlRegister |
1010 |
|
|
! ewe= 0 |
1011 |
|
|
set 0x01f800d0, %l1 |
1012 |
|
|
clr %l2 |
1013 |
|
|
st %l2, [%l1] |
1014 |
|
|
|
1015 |
|
|
! restore InterruptMaskRegister |
1016 |
|
|
set 0x01f8004c, %l2 |
1017 |
|
|
st %l0, [%l2] |
1018 |
|
|
|
1019 |
|
|
! restore SystemControlRegister |
1020 |
|
|
set 0x01f80000, %l2 |
1021 |
|
|
st %l1, [%l2] |
1022 |
|
|
|
1023 |
|
|
! nop |
1024 |
|
|
! nop |
1025 |
|
|
ret |
1026 |
|
|
! nop |
1027 |
|
|
! nop |
1028 |
|
|
restore |
1029 |
|
|
nop |
1030 |
|
|
! nop |
1031 |
|
|
|
1032 |
|
|
"); |
1033 |
|
|
|
1034 |
|
|
|
1035 |
|
|
/****************************************************************************** |
1036 |
|
|
* |
1037 |
|
|
* eosEepromCheckSumTest - perform the CRC test on EEPROM of LA695E-CORE board |
1038 |
|
|
* |
1039 |
|
|
* |
1040 |
|
|
* RETURNS: |
1041 |
|
|
* EEPROM_TEST_OK |
1042 |
|
|
* EEPROM_TEST_NOK |
1043 |
|
|
* |
1044 |
|
|
*/ |
1045 |
|
|
|
1046 |
|
|
int eosEepromCheckSumTest (void) |
1047 |
|
|
{ |
1048 |
|
|
|
1049 |
|
|
unsigned short crc; |
1050 |
|
|
unsigned int lenApp; |
1051 |
|
|
unsigned short crcApp; |
1052 |
|
|
unsigned int* pEE; |
1053 |
|
|
unsigned char ch; |
1054 |
|
|
unsigned int temp; |
1055 |
|
|
unsigned int status; |
1056 |
|
|
int i; |
1057 |
|
|
|
1058 |
|
|
lenApp =EEPROM_LEN_EXE; |
1059 |
|
|
crcApp =*((unsigned int*)(EEPROM_START_EXE + EEPROM_LEN_EXE - 4)); |
1060 |
|
|
pEE =(unsigned int*)(EEPROM_START_EXE); |
1061 |
|
|
for (i=0, crc=0xffff; i< lenApp-8; i += 4,pEE++ ) |
1062 |
|
|
{ |
1063 |
|
|
temp =*pEE; |
1064 |
|
|
ch =(unsigned char)((temp>>24) & 0x000000ff); |
1065 |
|
|
crc =crcComp(&ch,crc); |
1066 |
|
|
ch =(unsigned char)((temp>>16) & 0x000000ff); |
1067 |
|
|
crc =crcComp(&ch,crc); |
1068 |
|
|
ch =(unsigned char)((temp>>8) & 0x000000ff); |
1069 |
|
|
crc =crcComp(&ch,crc); |
1070 |
|
|
ch =(unsigned char)(temp & 0x000000ff); |
1071 |
|
|
crc =crcComp(&ch,crc); |
1072 |
|
|
} |
1073 |
|
|
|
1074 |
|
|
if (crc == crcApp) |
1075 |
|
|
{ |
1076 |
|
|
status =EEPROM_TEST_OK; |
1077 |
|
|
} |
1078 |
|
|
else |
1079 |
|
|
{ |
1080 |
|
|
status =EEPROM_TEST_NOK; |
1081 |
|
|
} |
1082 |
|
|
return(status); |
1083 |
|
|
|
1084 |
|
|
} |
1085 |
|
|
|
1086 |
|
|
|
1087 |
|
|
/*****************************************************************************/ |
1088 |
|
|
/* @Function: PD_ifcrcComp */ |
1089 |
|
|
/* @Purpose : */ |
1090 |
|
|
/* This function calculates the CRC. */ |
1091 |
|
|
/* */ |
1092 |
|
|
/* @@ */ |
1093 |
|
|
/* @Parameter Name @Mode @Description */ |
1094 |
|
|
/* @@ */ |
1095 |
|
|
/*****************************************************************************/ |
1096 |
|
|
unsigned short crcComp (unsigned char* adrs, unsigned short Crc) |
1097 |
|
|
{ |
1098 |
|
|
unsigned int Crc16Value; |
1099 |
|
|
|
1100 |
|
|
Crc16Value =Crc; |
1101 |
|
|
// Calculating the CRC16 by using a LookUp table |
1102 |
|
|
Crc16Value = (unsigned int)(Crc16Value << 8) ^ |
1103 |
|
|
(unsigned int)(Crc_lookup[ (unsigned int) ( ((Crc16Value >> 8) & |
1104 |
|
|
0xFF) ^ *adrs) ]); |
1105 |
|
|
return ((unsigned short)Crc16Value); |
1106 |
|
|
|
1107 |
|
|
} |