| 1 |
/**************************************************************************** |
| 2 |
/* F i l e D a t a |
| 3 |
/* |
| 4 |
/* Module : BasicSW |
| 5 |
/* C.I. No. : |
| 6 |
/* $Revision: 1.20 $ |
| 7 |
/* $Date: 2005/03/20 18:16:27 $ |
| 8 |
/* Belonging to : |
| 9 |
/* : |
| 10 |
/* $RCSfile: IM_InterruptManager_op.c,v $ |
| 11 |
/* Program Type : |
| 12 |
/* Sub-modules : |
| 13 |
/* |
| 14 |
/**************************************************************************** |
| 15 |
/* S W D e v e l o p m e n t E n v i r o n m e n t |
| 16 |
/* |
| 17 |
/* Host system : |
| 18 |
/* SW Compiler : |
| 19 |
/* $Author: sebastiani $ |
| 20 |
/* : |
| 21 |
/**************************************************************************** |
| 22 |
/* U p d a t i n g |
| 23 |
/* |
| 24 |
/* $Log: IM_InterruptManager_op.c,v $ |
| 25 |
/* Revision 1.20 2005/03/20 18:16:27 sebastiani |
| 26 |
/* watch dog reenabled; TIM_MMSU_DMA_DELAY cancelled in WriteEOT |
| 27 |
/* |
| 28 |
/* Revision 1.19 2005/03/06 14:51:51 sebastiani |
| 29 |
/* fix |
| 30 |
/* |
| 31 |
/* Revision 1.18 2005/02/21 08:58:28 sebastiani |
| 32 |
/* all log comments completed |
| 33 |
/* |
| 34 |
/* Revision 1.17 2005/02/19 10:05:23 sebastiani |
| 35 |
/* LU_HA introduces in a log line |
| 36 |
/* |
| 37 |
/* Revision 1.16 2005/01/26 18:46:19 sebastiani |
| 38 |
/* *** empty log message *** |
| 39 |
/* |
| 40 |
/* Revision 1.15 2004/10/06 16:38:21 sebastiani |
| 41 |
/* fix watchdog procedure |
| 42 |
/* |
| 43 |
/* Revision 1.14 2004/09/28 15:36:05 sebastiani |
| 44 |
/* interrupt manager fix |
| 45 |
/* |
| 46 |
/* Revision 1.13 2004/09/22 09:53:53 sebastiani |
| 47 |
/* added watchdog |
| 48 |
/* |
| 49 |
/* Revision 1.12 2004/09/17 15:01:00 faber |
| 50 |
/* LU_INFN_LOG flags fixing |
| 51 |
/* |
| 52 |
/* Revision 1.11 2004/09/09 14:49:25 sebastiani |
| 53 |
/* add get called |
| 54 |
/* |
| 55 |
/* Revision 1.10 2004/09/08 10:39:12 faber |
| 56 |
/* *** empty log message *** |
| 57 |
/* |
| 58 |
/* Revision 1.9 2004/08/26 16:53:48 sebastiani |
| 59 |
/* fix some bug |
| 60 |
/* |
| 61 |
/* Revision 1.8 2004/07/20 14:31:41 sebastiani |
| 62 |
/* *** empty log message *** |
| 63 |
/* |
| 64 |
/* Revision 1.7 2004/07/20 08:58:00 faber |
| 65 |
/* simulator mode for EEPROM procedures |
| 66 |
/* |
| 67 |
/* Revision 1.6 2004/07/08 16:23:29 sebastiani |
| 68 |
/* *** empty log message *** |
| 69 |
/* |
| 70 |
/* Revision 1.5 2003/11/18 09:01:14 alfarano |
| 71 |
/* laben patch fixes some problems |
| 72 |
/* |
| 73 |
/* Revision 1.4 2003/10/30 16:10:48 faber |
| 74 |
/* GPT disabled. the callback function is a null function |
| 75 |
/* |
| 76 |
/* Revision 1.3 2003/10/21 16:09:12 alfarano |
| 77 |
/* LU_LOG_INFN replacement for all remaining original log functions |
| 78 |
/* |
| 79 |
/* Revision 1.2 2003/08/07 08:49:07 wizard |
| 80 |
/* interrupt counter array introduced under DEBUF definition |
| 81 |
/* |
| 82 |
/* Revision 1.1.1.1 2003/08/04 09:40:21 sebastiani |
| 83 |
/* Imported sources laben rel. 19.06.2003 integrated with pam2 |
| 84 |
/* |
| 85 |
/* Revision 1.12 2003/05/20 12:22:24 aurora |
| 86 |
/* masked HW errors for EM |
| 87 |
/* |
| 88 |
/* Revision 1.11 2003/02/26 16:30:32 aurora |
| 89 |
/* improved response time for CRIMEA interrupts |
| 90 |
/* |
| 91 |
/* Revision 1.10 2003/01/30 09:43:26 aurora |
| 92 |
/* introduced ifdef for EM and FM |
| 93 |
/* |
| 94 |
/* Revision 1.9 2003/01/22 13:50:20 aurora |
| 95 |
/* Added the sw management for three new interrupt on Crimea |
| 96 |
/* |
| 97 |
/* Revision 1.8 2002/10/25 08:59:07 zulia |
| 98 |
/* removed clear of interrupt 5 after prepare_page |
| 99 |
/* |
| 100 |
/* Revision 1.7 2002/05/09 08:16:34 zulia |
| 101 |
/* * acceptance release |
| 102 |
/* |
| 103 |
/* |
| 104 |
/*****************************************************************************/ |
| 105 |
|
| 106 |
/*============================= Include File ================================*/ |
| 107 |
|
| 108 |
#include <src/INFN/LU_SourceFileID_INFN.h> |
| 109 |
#define __FILEID__ _IM_InterruptManager_op__c |
| 110 |
#include <src/INFN/PRH_ParamHandler_INFN_auto.h> |
| 111 |
#include <src/INFN/PRH_ParamHandler_INFN.h> |
| 112 |
#include <src/INFN/LU_LogUtility_INFN.h> |
| 113 |
|
| 114 |
#include <src/BasicSW/InterruptManager/IM_InterruptManager_op.h> |
| 115 |
#include <src/FileManager/MMSUManager/FT_MMSUManager_p.h> |
| 116 |
#include <src/BasicSW/CrimeaDriver/CD_CrimeaDriver_p.h> |
| 117 |
#include <src/HKManager/HistoryArea/HA_HistoryArea_p.h> |
| 118 |
#include <src/BasicSW/Bus1553B/BI_Bus1553B_p.h> |
| 119 |
|
| 120 |
|
| 121 |
LU_DECL_MASK(); |
| 122 |
|
| 123 |
|
| 124 |
/*****************************************************************************/ |
| 125 |
/*============================= Object variables ============================*/ |
| 126 |
|
| 127 |
#ifdef DEBUG |
| 128 |
typedef enum { |
| 129 |
IM_NULL, |
| 130 |
IM_INT1, |
| 131 |
IM_MOD1, |
| 132 |
IM_MOD2, |
| 133 |
IM_1553B, |
| 134 |
IM_PIF_ETO, |
| 135 |
IM_AUX1, |
| 136 |
IM_AUX2, |
| 137 |
IM_AUX3, |
| 138 |
IM_INT2, |
| 139 |
IM_INT3, |
| 140 |
IM_INT4, |
| 141 |
IM_INT5, |
| 142 |
IM_INT_MAX |
| 143 |
} IM_INTS; |
| 144 |
|
| 145 |
static unsigned int IM_Called[IM_INT_MAX]; |
| 146 |
#endif |
| 147 |
|
| 148 |
|
| 149 |
/*****************************************************************************/ |
| 150 |
|
| 151 |
/*=== I M _ I n t e r r u p t M a n a g e r O P E R . F U N C T I O N S ===*/ |
| 152 |
|
| 153 |
#ifdef DEBUG |
| 154 |
unsigned int IM_GetCalled(int i) { |
| 155 |
return IM_Called[i]; |
| 156 |
} |
| 157 |
unsigned int IM_opResetCalled() { |
| 158 |
int i; |
| 159 |
for(i=0;i<IM_INT_MAX;i++) |
| 160 |
IM_Called[i]=0; |
| 161 |
} |
| 162 |
#endif |
| 163 |
|
| 164 |
/*****************************************************************************/ |
| 165 |
/* @Function: IM_piIntInterruptManager */ |
| 166 |
/* @Purpose : */ |
| 167 |
/* The function performs the following initialization: */ |
| 168 |
/* - Establishes an ISR for ERC 32 Data Access interrupt. */ |
| 169 |
/* - Establishes an ISR for ERC 32 External INT 1...5. */ |
| 170 |
/* - Establishes an ISR null for for all ERC 32 interrupt not used (UART */ |
| 171 |
/* DMA ..) */ |
| 172 |
/* - Programming of the Interrupts Shape register (Edge and Plolarity of */ |
| 173 |
/* the External Interrupt) */ |
| 174 |
/* - Programming of the System Control Register */ |
| 175 |
/* - Programming of the Interrupts Mask Register */ |
| 176 |
/* - Clearing of all interrupt. */ |
| 177 |
/* */ |
| 178 |
/* @@ */ |
| 179 |
/* @Parameter Name @Mode @Description */ |
| 180 |
/* IN */ |
| 181 |
/* status_code OUT Return code */ |
| 182 |
/* @@ */ |
| 183 |
/*****************************************************************************/ |
| 184 |
|
| 185 |
void IM_ihWDINT(){ |
| 186 |
// static UINT32 intLevel; |
| 187 |
// OS_piInterDisable(&intLevel); |
| 188 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_WATCHDOG_TIMEOUT); |
| 189 |
// OS_piInterEnable(intLevel); |
| 190 |
|
| 191 |
if(PRH_VAR_WATCHDOG_RESET_DISABLE) |
| 192 |
{ |
| 193 |
WATCHDOG_RESET; |
| 194 |
#ifdef DEBUG |
| 195 |
console_outbyte_polled(0,'W'); |
| 196 |
console_outbyte_polled(0,'\n'); |
| 197 |
#endif |
| 198 |
} |
| 199 |
// PRH_WriteEEPROMBootinfo(PRH_BOOTINFO_WD_RESET); |
| 200 |
// PM_CPU_Reboot(TRUE); |
| 201 |
} |
| 202 |
|
| 203 |
|
| 204 |
|
| 205 |
|
| 206 |
status_code IM_opIntInterruptManager(void) |
| 207 |
{ |
| 208 |
status_code status; |
| 209 |
void* OldHandler; |
| 210 |
#ifdef DEBUG |
| 211 |
IM_opResetCalled(); |
| 212 |
#endif |
| 213 |
/*===========================================================================*/ |
| 214 |
/*==== DATA ACCESS INTERRUPT (ERC32) INITIALIZATION =========*/ |
| 215 |
|
| 216 |
status =OS_piIsrCatch ( IM_ihInstructionAccessINT, |
| 217 |
0x01, |
| 218 |
&OldHandler); |
| 219 |
|
| 220 |
/*===========================================================================*/ |
| 221 |
/*==== INSTR. ACCESS INTERRUPT (ERC32) INITIALIZATION ======*/ |
| 222 |
|
| 223 |
status =OS_piIsrCatch ( IM_ihDataAccessINT, |
| 224 |
0x09, |
| 225 |
&OldHandler); |
| 226 |
/*===========================================================================*/ |
| 227 |
/*==== EXTERNAL INTERRUPT (ERC32) 1 -2 -3 -4 -5 INITIALIZATION =========*/ |
| 228 |
|
| 229 |
status |=OS_piIsrCatch ( IM_ihExternalINT1, |
| 230 |
ERC32_INTERRUPT_EXTERNAL_1+0x10, |
| 231 |
&OldHandler); |
| 232 |
|
| 233 |
status |=OS_piIsrCatch ( IM_ihExternalINT2, |
| 234 |
ERC32_INTERRUPT_EXTERNAL_2+0x10, |
| 235 |
&OldHandler); |
| 236 |
status |=OS_piIsrCatch ( IM_ihExternalINT3, |
| 237 |
ERC32_INTERRUPT_EXTERNAL_3+0x10, |
| 238 |
&OldHandler); |
| 239 |
status |=OS_piIsrCatch ( IM_ihExternalINT4, |
| 240 |
ERC32_INTERRUPT_EXTERNAL_4+0x10, |
| 241 |
&OldHandler); |
| 242 |
|
| 243 |
status |=OS_piIsrCatch ( IM_ihExternalINT5, |
| 244 |
ERC32_INTERRUPT_EXTERNAL_5+0x10, |
| 245 |
&OldHandler); |
| 246 |
/*===========================================================================*/ |
| 247 |
/*=== INTERRUPT ASYNCHRONOUS (ERC32) INITIALIZATION TO A NULL FUNC.======*/ |
| 248 |
|
| 249 |
/* INTERRUPT MASKED_ERRORS */ |
| 250 |
status |=OS_piIsrCatch ( IM_ihNullINT, |
| 251 |
ERC32_INTERRUPT_MASKED_ERRORS+0x10, |
| 252 |
&OldHandler); |
| 253 |
|
| 254 |
/* INTERRUPT UART_A_RX_TX */ |
| 255 |
status |=OS_piIsrCatch ( IM_ihNullINT, |
| 256 |
ERC32_INTERRUPT_UART_A_RX_TX+0x10, |
| 257 |
&OldHandler); |
| 258 |
/* INTERRUPT UART_B_RX_TX */ |
| 259 |
status |=OS_piIsrCatch ( IM_ihNullINT, |
| 260 |
ERC32_INTERRUPT_UART_B_RX_TX+0x10, |
| 261 |
&OldHandler); |
| 262 |
/* INTERRUPT CORRECTABLE_MEMORY_ERROR */ |
| 263 |
status |=OS_piIsrCatch ( IM_ihNullINT, |
| 264 |
ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR+0x10, |
| 265 |
&OldHandler); |
| 266 |
/* INTERRUPT UART_ERROR */ |
| 267 |
status |=OS_piIsrCatch ( IM_ihNullINT, |
| 268 |
ERC32_INTERRUPT_UART_ERROR+0x10, |
| 269 |
&OldHandler); |
| 270 |
/* INTERRUPT DMA_ACCESS_ERROR */ |
| 271 |
status |=OS_piIsrCatch ( IM_ihNullINT, |
| 272 |
ERC32_INTERRUPT_DMA_ACCESS_ERROR+0x10, |
| 273 |
&OldHandler); |
| 274 |
/* INTERRUPT DMA_TIMEOUT */ |
| 275 |
status |=OS_piIsrCatch ( IM_ihNullINT, |
| 276 |
ERC32_INTERRUPT_DMA_TIMEOUT+0x10, |
| 277 |
&OldHandler); |
| 278 |
|
| 279 |
status |=OS_piIsrCatch ( IM_ihWDINT, |
| 280 |
ERC32_INTERRUPT_WATCHDOG_TIMEOUT+0x10, |
| 281 |
&OldHandler); |
| 282 |
|
| 283 |
|
| 284 |
|
| 285 |
if (status!=SUCCESSFUL) |
| 286 |
{ |
| 287 |
/* ISR not successfully established */ |
| 288 |
// LOG_INFN HA_piLogHistoryEntry10(HA_E10_SW_IM,HA_E10_INT_CATCH_ERR,status); |
| 289 |
LU_INFN_LOG(LU_FATAL | LU_HA ,LU_MASK(__FILEID__),__FILEID__,__LINE__,status); |
| 290 |
} |
| 291 |
/*===========================================================================*/ |
| 292 |
/*===== SYSTEM CONTROL REGISTER PROGRAMMING ======*/ |
| 293 |
#ifndef SIMULATOR |
| 294 |
#ifdef __FM__ |
| 295 |
ERC32_MEC.Control =0x1288801B; |
| 296 |
#else |
| 297 |
/* for EM the HW errors are masked */ |
| 298 |
ERC32_MEC.Control =0x1288A0BB; |
| 299 |
#endif |
| 300 |
#else // SIMULATOR |
| 301 |
/* same as EM */ |
| 302 |
ERC32_MEC.Control =0x1288A0BB; |
| 303 |
#endif |
| 304 |
/*===========================================================================*/ |
| 305 |
/*===== INTERRUPTS SHAPE REGISTER PROGRAMMING ======*/ |
| 306 |
|
| 307 |
/* 31.....13 12 11 10 9 8 7 6 5 4 3 2 1 0 */ |
| 308 |
/* Reserved - Polarity - Ack - Edge */ |
| 309 |
/* - 0 0 0 0 1 - 0 0 0 - 1 1 1 1 0 */ |
| 310 |
|
| 311 |
/* Edge - (0) Level Triggered (1) Edge Triggered */ |
| 312 |
/* Polarity - (0) Low Level or Falling Edge */ |
| 313 |
ERC32_MEC.Interrupt_Shape =0x0000011e; |
| 314 |
|
| 315 |
/*====== INTERRUPTS MASK REGISTER PROGRAMMING ======*/ |
| 316 |
|
| 317 |
/* 31.14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 */ |
| 318 |
/* 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 */ |
| 319 |
ERC32_MEC.Interrupt_Mask =0x000043c2; |
| 320 |
|
| 321 |
/*===========================================================================*/ |
| 322 |
/*===== ALL ERC32 INTERRUPTS ARE CLEARED ======*/ |
| 323 |
|
| 324 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_MASKED_ERRORS); |
| 325 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_EXTERNAL_1); |
| 326 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_EXTERNAL_2); |
| 327 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_UART_A_RX_TX); |
| 328 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_UART_B_RX_TX); |
| 329 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR); |
| 330 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_UART_ERROR); |
| 331 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_DMA_ACCESS_ERROR); |
| 332 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_DMA_TIMEOUT); |
| 333 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_EXTERNAL_3); |
| 334 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_EXTERNAL_4); |
| 335 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER); |
| 336 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_REAL_TIME_CLOCK); |
| 337 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_EXTERNAL_5); |
| 338 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_WATCHDOG_TIMEOUT); |
| 339 |
|
| 340 |
return (status); |
| 341 |
|
| 342 |
} |
| 343 |
|
| 344 |
|
| 345 |
/*****************************************************************************/ |
| 346 |
/* @Function: IM_opExternalINT1 */ |
| 347 |
/* @Purpose : */ |
| 348 |
/* The function implements the interrupt handler of the Data Access */ |
| 349 |
/* exception. */ |
| 350 |
/* This interrupt arises when error on data loading is found out. */ |
| 351 |
/* The function performs the following steps: */ |
| 352 |
/* - Disable all sparc interrupts. */ |
| 353 |
/* - Get error information by reading Sistem Fault Status register. */ |
| 354 |
/* - Write System Status Word =0x8000 | SYSFSR(2..15 bits) in the 1553 */ |
| 355 |
/* memory area. */ |
| 356 |
/* - Stop any task operation and continuosly perform Watchdog reset. */ |
| 357 |
/* */ |
| 358 |
/* @@ */ |
| 359 |
/* @Parameter Name @Mode @Description */ |
| 360 |
/* @@ */ |
| 361 |
/*****************************************************************************/ |
| 362 |
#ifdef SIMULATOR |
| 363 |
static unsigned int IM_DataAccessCount = 0; |
| 364 |
#endif |
| 365 |
|
| 366 |
void IM_opDataAccessINT (void) |
| 367 |
{ |
| 368 |
#ifdef SIMULATOR |
| 369 |
IM_DataAccessCount++; |
| 370 |
#else |
| 371 |
unsigned short statusWord; |
| 372 |
unsigned int level; |
| 373 |
LU_UART_CR('D'); |
| 374 |
level =sparc_disable_interrupts(); |
| 375 |
/* Get ERC32 Status Word */ |
| 376 |
statusWord =IM_GET_STATUS_WORD; |
| 377 |
/* Write Status Word in the 1553 memory area */ |
| 378 |
BI_pi1553BWriteStatusWord(statusWord); |
| 379 |
/* Stop any task operation */ |
| 380 |
while( FOREVER ) |
| 381 |
{ |
| 382 |
WATCHDOG_RESET; |
| 383 |
} |
| 384 |
#endif |
| 385 |
} |
| 386 |
|
| 387 |
|
| 388 |
|
| 389 |
/*****************************************************************************/ |
| 390 |
/* @Function: IM_opDataAccessINT */ |
| 391 |
/* @Purpose : */ |
| 392 |
/* The function implements the interrupt handler of the Erc32 */ |
| 393 |
/* Instruction Access exeception. */ |
| 394 |
/* */ |
| 395 |
/* @@ */ |
| 396 |
/* @Parameter Name @Mode @Description */ |
| 397 |
/* IN */ |
| 398 |
/* OUT */ |
| 399 |
/* @@ */ |
| 400 |
/*****************************************************************************/ |
| 401 |
|
| 402 |
|
| 403 |
|
| 404 |
|
| 405 |
|
| 406 |
|
| 407 |
|
| 408 |
|
| 409 |
|
| 410 |
#ifdef SIMULATOR |
| 411 |
static unsigned int IM_InstructionAccessCount = 0; |
| 412 |
#endif |
| 413 |
|
| 414 |
void IM_opInstructionAccessINT (void) |
| 415 |
{ |
| 416 |
#ifdef SIMULATOR |
| 417 |
IM_InstructionAccessCount++; |
| 418 |
#else |
| 419 |
unsigned short statusWord; |
| 420 |
unsigned int level; |
| 421 |
LU_UART_CR('U'); |
| 422 |
level =sparc_disable_interrupts(); |
| 423 |
/* Get ERC32 Status Word */ |
| 424 |
statusWord =IM_GET_STATUS_WORD; |
| 425 |
/* Write Status Word in the 1553 memory area */ |
| 426 |
BI_pi1553BWriteStatusWord(statusWord); |
| 427 |
/* Stop any task operation */ |
| 428 |
while( FOREVER ) |
| 429 |
{ |
| 430 |
WATCHDOG_RESET; |
| 431 |
} |
| 432 |
#endif |
| 433 |
} |
| 434 |
|
| 435 |
|
| 436 |
|
| 437 |
/*****************************************************************************/ |
| 438 |
/* @Function: IM_opExternalINT1 */ |
| 439 |
/* @Purpose : */ |
| 440 |
/* The function implements the interrupt handler of the External INT 1. */ |
| 441 |
/* This interrupt is connected to the CRIMEA component. Reading the */ |
| 442 |
/* CRIMEA Interrupt Pending register can be established which line has */ |
| 443 |
/* produced the interrupt and then called the apropriate management */ |
| 444 |
/* function. */ |
| 445 |
/* The CRIMEA and ERC32 interrupt are cleared. */ |
| 446 |
/* */ |
| 447 |
/* @@ */ |
| 448 |
/* @Parameter Name @Mode @Description */ |
| 449 |
/* @@ */ |
| 450 |
/*****************************************************************************/ |
| 451 |
|
| 452 |
void IM_opExternalINT1 (void) |
| 453 |
{ |
| 454 |
unsigned int InterVect; |
| 455 |
unsigned int mask; |
| 456 |
#ifdef DEBUG |
| 457 |
IM_Called[IM_INT1]++; |
| 458 |
#endif |
| 459 |
mask =0x00010000; |
| 460 |
CD_piGetCrimeaInterPending (&InterVect); |
| 461 |
if (InterVect & (mask << CD_INTER_MEM_MOD_1)) |
| 462 |
{ |
| 463 |
#ifdef DEBUG |
| 464 |
IM_Called[IM_MOD1]++; |
| 465 |
#endif |
| 466 |
/* Local Memory Module 1 interrupt menagement */ |
| 467 |
FT_piMemBoardMod(FT_MEM_MOD_1); |
| 468 |
CD_piSetCrimeaInterClear (mask << CD_INTER_MEM_MOD_1); |
| 469 |
} |
| 470 |
if (InterVect & (mask << CD_INTER_MEM_MOD_2)) |
| 471 |
{ |
| 472 |
#ifdef DEBUG |
| 473 |
IM_Called[IM_MOD2]++; |
| 474 |
#endif |
| 475 |
/* Local Memory Module 2 interrupt menagement */ |
| 476 |
FT_piMemBoardMod(FT_MEM_MOD_2); |
| 477 |
CD_piSetCrimeaInterClear (mask << CD_INTER_MEM_MOD_2); |
| 478 |
} |
| 479 |
if (InterVect & (mask << CD_INTER_1553B_MSG)) |
| 480 |
{ |
| 481 |
#ifdef DEBUG |
| 482 |
IM_Called[IM_1553B]++; |
| 483 |
#endif |
| 484 |
/* Bus 1553 interrupt menagement */ |
| 485 |
BI_pi1553BInterruptHandler(); |
| 486 |
CD_piSetCrimeaInterClear (mask << CD_INTER_1553B_MSG); |
| 487 |
} |
| 488 |
if (InterVect & (mask << CD_INTER_PIF_ETO)) |
| 489 |
{ |
| 490 |
#ifdef DEBUG |
| 491 |
IM_Called[IM_PIF_ETO]++; |
| 492 |
#endif |
| 493 |
/* PIF Event Timeout */ |
| 494 |
PM_piPageIsEmpty(); |
| 495 |
CD_piSetCrimeaInterClear (mask << CD_INTER_PIF_ETO); |
| 496 |
} |
| 497 |
if (InterVect & (mask << CD_AUX_1)) |
| 498 |
{ |
| 499 |
#ifdef DEBUG |
| 500 |
IM_Called[IM_AUX1]++; |
| 501 |
#endif |
| 502 |
/* External Interrupt */ |
| 503 |
/* Add here the function for its management */ |
| 504 |
//TEST!!! remove the next instruction |
| 505 |
// LOG_INFN HA_piLogHistoryEntry10(HA_E10_SW_IM,HA_E10_INT_CATCH_ERR,0x1); |
| 506 |
/*@LOG CD_AUX_1 interrupt */ |
| 507 |
LU_INFN_LOG(LU_DEBUG_TRACE|LU_HA,LU_MASK(__FILEID__),__FILEID__,__LINE__,InterVect); |
| 508 |
TI_opTimeSyncExtInterrupt(); |
| 509 |
CD_piSetCrimeaInterClear (mask << CD_AUX_1); |
| 510 |
} |
| 511 |
|
| 512 |
#ifdef __FM__ |
| 513 |
if (InterVect & (mask << CD_AUX_2)) |
| 514 |
{ |
| 515 |
#ifdef DEBUG |
| 516 |
IM_Called[IM_AUX2]++; |
| 517 |
#endif |
| 518 |
/* External Interrupt */ |
| 519 |
/* Add here the function for its management */ |
| 520 |
//TEST!!! remove the next instruction |
| 521 |
// LOG_INFN HA_piLogHistoryEntry10(HA_E10_SW_IM,HA_E10_INT_CATCH_ERR,0x2); |
| 522 |
/*@LOG CD_AUX_2 interrupt */ |
| 523 |
LU_INFN_LOG(LU_CRITICAL | LU_HA,LU_MASK(__FILEID__),__FILEID__,__LINE__,0x2); |
| 524 |
CD_piSetCrimeaInterClear (mask << CD_AUX_2); |
| 525 |
} |
| 526 |
if (InterVect & (mask << CD_AUX_3)) |
| 527 |
{ |
| 528 |
#ifdef DEBUG |
| 529 |
IM_Called[IM_AUX3]++; |
| 530 |
#endif |
| 531 |
/* External Interrupt */ |
| 532 |
/* Add here the function for its management */ |
| 533 |
//TEST!!! remove the next instruction |
| 534 |
// LOG_INFN HA_piLogHistoryEntry10(HA_E10_SW_IM,HA_E10_INT_CATCH_ERR,0x3); |
| 535 |
/*@LOG CD_AUX_3 interrupt */ |
| 536 |
LU_INFN_LOG(LU_CRITICAL | LU_HA ,LU_MASK(__FILEID__),__FILEID__,__LINE__,0x3); |
| 537 |
CD_piSetCrimeaInterClear (mask << CD_AUX_3); |
| 538 |
} |
| 539 |
#endif |
| 540 |
|
| 541 |
/* Clear ERC32 interrupt */ |
| 542 |
ERC32_Clear_interrupt(ERC32_INTERRUPT_EXTERNAL_1); |
| 543 |
} |
| 544 |
|
| 545 |
|
| 546 |
|
| 547 |
/*****************************************************************************/ |
| 548 |
/* @Function: IM_opExternalINT2 */ |
| 549 |
/* @Purpose : */ |
| 550 |
/* The function implements the interrupt handler of the External INT 2. */ |
| 551 |
/* This interrupt is connected to the Data Timeout signal. The function */ |
| 552 |
/* that menages the Data Timeout interrupt is in SRAMPageManager object. */ |
| 553 |
/* The ERC32 interrupt is cleared. */ |
| 554 |
/* */ |
| 555 |
/* @@ */ |
| 556 |
/* @Parameter Name @Mode @Description */ |
| 557 |
/* @@ */ |
| 558 |
/*****************************************************************************/ |
| 559 |
|
| 560 |
void IM_opExternalINT2 (void) |
| 561 |
{ |
| 562 |
/* Call Data Timeout menagement function in SRAMPageManager */ |
| 563 |
#ifdef DEBUG |
| 564 |
IM_Called[IM_INT2]++; |
| 565 |
#endif |
| 566 |
PM_piPageHasData(); |
| 567 |
|
| 568 |
/* Due to HW/SW synchro the interrupt pending clear is */ |
| 569 |
/* made in the above ISR */ |
| 570 |
} |
| 571 |
|
| 572 |
|
| 573 |
|
| 574 |
/*****************************************************************************/ |
| 575 |
/* @Function: IM_opExternalINT3 */ |
| 576 |
/* @Purpose : */ |
| 577 |
/* The function implements the interrupt handler of the External INT 3. */ |
| 578 |
/* This interrupt is connected to the Read EOT signal. */ |
| 579 |
/* The function that manages the Read EOT interrupt is in MMSUManager object.*/ |
| 580 |
/* The ERC32 interrupt is cleared. */ |
| 581 |
/* */ |
| 582 |
/* @@ */ |
| 583 |
/* @Parameter Name @Mode @Description */ |
| 584 |
/* @@ */ |
| 585 |
/*****************************************************************************/ |
| 586 |
|
| 587 |
void IM_opExternalINT3 (void) |
| 588 |
{ |
| 589 |
/* Call Read EOT menagement function in MMSUManager */ |
| 590 |
#ifdef DEBUG |
| 591 |
IM_Called[IM_INT3]++; |
| 592 |
#endif |
| 593 |
FT_piReadEOT(); |
| 594 |
|
| 595 |
/* Due to HW/SW synchro the interrupt pending clear is */ |
| 596 |
/* made in the above ISR */ |
| 597 |
} |
| 598 |
|
| 599 |
|
| 600 |
|
| 601 |
/*****************************************************************************/ |
| 602 |
/* @Function: IM_opExternalINT4 */ |
| 603 |
/* @Purpose : */ |
| 604 |
/* The function implements the interrupt handler of the External INT 4. */ |
| 605 |
/* This interrupt is connected to the Write EOT signal. */ |
| 606 |
/* The function that manages the Write EOT interrupt is in MMSUManager */ |
| 607 |
/* object. The ERC32 interrupt is cleared. */ |
| 608 |
/* */ |
| 609 |
/* @@ */ |
| 610 |
/* @Parameter Name @Mode @Description */ |
| 611 |
/* @@ */ |
| 612 |
/*****************************************************************************/ |
| 613 |
|
| 614 |
|
| 615 |
void IM_MMSU_ISR(rtems_id timer_id, |
| 616 |
void *unused) |
| 617 |
{ |
| 618 |
FT_piWriteEOT(); |
| 619 |
} |
| 620 |
|
| 621 |
|
| 622 |
|
| 623 |
void IM_opExternalINT4 (void) |
| 624 |
{ |
| 625 |
#ifdef DEBUG |
| 626 |
IM_Called[IM_INT4]++; |
| 627 |
#endif |
| 628 |
|
| 629 |
FT_piWriteEOT(); |
| 630 |
|
| 631 |
|
| 632 |
/* Due to HW/SW synchro the interrupt pending clear is */ |
| 633 |
/* made in the above ISR */ |
| 634 |
} |
| 635 |
|
| 636 |
|
| 637 |
|
| 638 |
/*****************************************************************************/ |
| 639 |
/* @Function: IM_opExternalINT5 */ |
| 640 |
/* @Purpose : */ |
| 641 |
/* The function implements the interrupt handler of the External INT 5. */ |
| 642 |
/* This interrupt is connected to the Event Trigger signal. */ |
| 643 |
/* The function that manages the Event Triger interrupt is in */ |
| 644 |
/* SRAMPageManager object. The ERC32 interrupt is cleared. */ |
| 645 |
/* */ |
| 646 |
/* @@ */ |
| 647 |
/* @Parameter Name @Mode @Description */ |
| 648 |
/* @@ */ |
| 649 |
/*****************************************************************************/ |
| 650 |
|
| 651 |
void IM_opExternalINT5 (void) |
| 652 |
{ |
| 653 |
#ifdef DEBUG |
| 654 |
IM_Called[IM_INT5]++; |
| 655 |
#endif |
| 656 |
/* Call Event Trigger menagement function in SRAMPageManager */ |
| 657 |
|
| 658 |
/* event trigger is not via interrupt in the new system design */ |
| 659 |
// PM_piPreparePage(); |
| 660 |
|
| 661 |
/* Due to HW/SW synchro the interrupt pending clear is */ |
| 662 |
/* made in the above ISR */ |
| 663 |
} |
| 664 |
|
| 665 |
|
| 666 |
|
| 667 |
/*****************************************************************************/ |
| 668 |
/* @Function: IM_opNullINT */ |
| 669 |
/* @Purpose : */ |
| 670 |
/* The function implements the null interrupt handler. */ |
| 671 |
/* */ |
| 672 |
/* @@ */ |
| 673 |
/* @Parameter Name @Mode @Description */ |
| 674 |
/* @@ */ |
| 675 |
/*****************************************************************************/ |
| 676 |
|
| 677 |
void IM_opNullINT (void) |
| 678 |
{ |
| 679 |
#ifdef DEBUG |
| 680 |
IM_Called[IM_NULL]++; |
| 681 |
#endif |
| 682 |
} |
| 683 |
|
| 684 |
|
| 685 |
#ifdef DEBUG |
| 686 |
unsigned int IM_opGetCalled(unsigned int i) { |
| 687 |
if(i<IM_INT_MAX) |
| 688 |
return IM_Called[i]; |
| 689 |
return -1; |
| 690 |
} |
| 691 |
|
| 692 |
#endif |
Parent Directory
| 
Revision Log