| 1 |
kusanagi |
1.1 |
0 LU_WRITE_ON_UART 1 "enable[1]/disable[0] the UART writing /RO" |
| 2 |
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1 VERBOSE_DEBUG 0 "Verbose Debug mode" |
| 3 |
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2 DOWNLOAD_HEADER 0 "download counter, to be written in Download header info /RW-E2P" |
| 4 |
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3 KHB_ALARM_REG_LOW_LEVEL_MASK 0 "mask of KHB Alarm register to be low-level masked /RO" |
| 5 |
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4 KHB_STATUS_REG_LOW_LEVEL_MASK 0 "mask of KHB status register to be low-level masked /RO" |
| 6 |
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5 PULSER_ACTION 0 "pulser action at startup; [0=none,1=Reset,2:0.25Hz,3:100Hz] /RO" |
| 7 |
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6 N_BOOT 0 "Boot Counter /RW-E2P" |
| 8 |
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7 THERMISTORS_CHECK 1 "Check if thermistor are going to be checked /RO" |
| 9 |
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8 THERM_MASK 65535 "Thermistors mask /RO" |
| 10 |
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9 IPM_VOLTAGES_CHECK 1 "Check if ipm are going to be checked /RO" |
| 11 |
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10 KHB_IDAQ_CHECK 1 "Check if khb&idaq are going to be checked /RO" |
| 12 |
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11 NTRIG 3 "Max Number of Lacks of Triggers /RO" |
| 13 |
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12 TRIG 0 "Counter of lacks of triggers /RW" |
| 14 |
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13 CONF_SEL 0 "active sensor selector /RW" |
| 15 |
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14 CONFOK 1 "whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON /RO" |
| 16 |
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15 OFF 0 "Counter of ON/OFF /RW" |
| 17 |
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16 NOFF 2 "Max Number of ON/OFF /RO" |
| 18 |
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17 NRES 6 "Max number of reset /RO" |
| 19 |
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18 RES 0 "Counter of reset /RW" |
| 20 |
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19 WATCHDOG_RESET_DISABLE 0 "disable watchdog reset: only for debugging!" |
| 21 |
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20 NFAILED_POWER_ON 3 "max number of failed power_on, before STOP&WAIT /RO" |
| 22 |
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21 AUTO_RM_MODE 0 "define the Automatic Mode for RM /RO" |
| 23 |
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22 AUTO_SCM_MODE 1 "define the Automatic Mode for scm /RO" |
| 24 |
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23 MASK_ACQ_ALARM 65535 "Alarm mask /RO" |
| 25 |
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24 GOM_DURING_ALARM 0 "General operation mode during alarm revelation /RW" |
| 26 |
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25 PM_FORCE_RUNNING_TIMEOUT 3600000 "waiting for start select mode before force go to running" |
| 27 |
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26 PAMELA_ON 0 "Pamela status [0=OFF-1:OFF] /RW" |
| 28 |
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27 N_CALIB 0 "Counter of calibratrion since start up /RW" |
| 29 |
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28 AC_1_ON 0 "AC 1 on from initialization /RW" |
| 30 |
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29 AC_2_ON 0 "AC 2 on from initialization /RW" |
| 31 |
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30 POWER_MODE 1 "Power mode of PAMELA /RW" |
| 32 |
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31 TRIG_II 0 "TRIGGER II level mode on/off /RO" |
| 33 |
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34 EXP64_MODE 1 "if TRUE, working in exp 64 mode /RO" |
| 34 |
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35 EXP64_MODE_DELAY 0 "delay for exp 64 mode acquiring /RO" |
| 35 |
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36 MH_END_OF_DOWNLOAD_TIMEOUT 60000 "time out of the end of download /RO" |
| 36 |
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37 PM_STOP_RUNMANAGER_TIMEOUT 1000 "the maximu time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager /RO" |
| 37 |
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38 PM_STOP_RUNMANAGER_TIMES_RETRY 5 "The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle. /RO" |
| 38 |
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39 PM_N_ORBIT_CALIB 1 "Number of orbits per calibration /RO" |
| 39 |
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40 WS_TIME_ORBIT 5670000 "The duration in millisencond of the full orbit in ms /RO" |
| 40 |
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41 WS_FAVOURITE_WS 0 "The Favourite Pamela Working Schedule /RO" |
| 41 |
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42 RM_N_TRIES_PREPARE_PAGE 100 "Number of attempts to try to exec the prepar page before exit from the run procedure with an error /RO" |
| 42 |
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43 RM_TRIES_PREPARE_PAGE_SLEEP 2 "Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure /RO" |
| 43 |
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44 RM_WS3_TIMER_FIRE_AFTER 8000 "Time to wait for the WS3 timer to fire /RO" |
| 44 |
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45 RM_TIME_MAX_RUN 1800000 "Max duration for an ordinary Run in milliseconds /RO" |
| 45 |
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46 RM_TIME_SPECIAL_RUN 100000 "duration for the special run in milliseconds /RO" |
| 46 |
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47 RM_ACQCHECK_PERIOD 1000 "period of acquisition check in milliseconds /RO" |
| 47 |
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48 RM_FLUSH_TIMEOUT 20000 "timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT /RO" |
| 48 |
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49 RM_NO_FLUSH_PARAM_DUMP 200 "Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never. /RO" |
| 49 |
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50 RM_DUMP_ALL_PARAMS 0 "dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs /RO" |
| 50 |
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51 RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ 70 "number of release busy inserted in the ACQ command queue in After_Calib mode /RO" |
| 51 |
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52 PWR_WAIT_BEFORE_SENDTC 110 "time to wait before send 2 successive HL /RO" |
| 52 |
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53 PWR_CMD2PSB_DELAY 100 "time to wait before every CMD2PSB" |
| 53 |
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54 PWR_TRB_READ_ATTEMPTS 10 "number of attempts to sent a command to the TRB before a timeout /RO" |
| 54 |
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55 PWR_KHB_INITBOARD_TWICE_DELAY 500 "milliseconds to wait between two KHB Init Board in PWR_DcdcON /RO" |
| 55 |
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56 PWR_IPM_WAIT_OK_N_ATTEMPT 150 "attempts of ipm check ok at power on /RO" |
| 56 |
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57 PWR_IPM_WAIT_OK_DELAY_ATTEMPT 1000 "attempts of ipm check ok at power on /RO" |
| 57 |
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58 PWR_VOLTAGE_N_ATTEMPT 10 "no of millisecond to wait in VOLTAGE IPM procedure /RO" |
| 58 |
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59 PWR_VOLTAGE_DELAY_ATTEMPT 1000 "no of millisecond to wain in VOLTAGE IPM procedure /RO" |
| 59 |
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60 PWR_TRB1_SET 16383 "trb 1 setting /RO" |
| 60 |
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61 PWR_TRB2_SET 16383 "trb 2 setting /RO" |
| 61 |
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62 PWR_TRB_SET_DELAY 20 "delay after trb set cmd /RO" |
| 62 |
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63 PWR_TRB_READ_DELAY 20 "delay after trb read cmd /RO" |
| 63 |
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64 HB_N_ATTEMPT_WRITE2PIF 2 "Number of attempt to write on PIF after return an error /RO" |
| 64 |
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65 HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF 100 "Waint time after a failed attempt on PIF write /RO" |
| 65 |
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66 HB_WRITE2PIF_TIMEOUT 1000 "timeout time time to wait a sketchboard free in Write2PIF /RO" |
| 66 |
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67 HB_ALMOST_FULL 80 "says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage. /RM" |
| 67 |
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68 TM_VRL_SUSPEND_HCL 110 "wait time between two HCL commands for the VRL /RO" |
| 68 |
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69 TM_VRL_SUSPEND_BEFORE_START 1 "wait time before start VRL /RO" |
| 69 |
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70 DAQ_EVENT_RECEIVE_TIMEOUT 20000 "PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply /RO" |
| 70 |
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71 DAQ_WAITFREECMDIF_N 4 "Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched /RO" |
| 71 |
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72 TRB_OK 1 "Use ON_OFF tracker in ACQ /RO" |
| 72 |
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73 TRIGGER_MODE_A 1 "Trigger type for acq mode A /RO" |
| 73 |
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74 TRIGGER_MODE_B 3 "Trigger type for acq mode B /RO" |
| 74 |
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75 TRIGGER_BUSY_CONTROL 0 "Select the check mask of the busy alaarm /RO" |
| 75 |
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76 TB_LINK 1 "Trigger Board to use 1 or 2 /RO" |
| 76 |
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77 TB_LINK_CUSTOM 1 "Trigger Board CUSTOMto use 1 or 2 /RO" |
| 77 |
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78 BUF_LEN_TB_SET_ALARM_MASK 8 "TRG queue" |
| 78 |
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79 BUF_LEN_TB_SET_PMT_MASK 12 "TRG queue" |
| 79 |
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80 BUF_LEN_TB_SET_S4_CAL_MASK 7 "TRG queue" |
| 80 |
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81 BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT 9 " " |
| 81 |
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82 BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD 9 " " |
| 82 |
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83 TRK_OK 1 "Use ON_OFF tracker in ACQ /RO" |
| 83 |
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84 TRK_CALIB_MODE 1 "Tracker calibration mode /RO" |
| 84 |
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85 TRK_TIME_SHORT 13 "Tracker wait loop for 128 loop /RO" |
| 85 |
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86 TRK_TIME_LONG 0 "Tracker wait loop for 8 loop /RO" |
| 86 |
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87 TRK_CALIB_INIT 104 "modality of calibration /RO" |
| 87 |
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88 TRK_NLOOP 12 "macro loop number /RO" |
| 88 |
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90 BUF_LEN_TRK_TRAILER_PRG_0 1 "TRK DSP Program Trailer for DSP 0 /RO" |
| 89 |
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91 BUF_LEN_TRK_TRAILER_PRG_1 1 "TRK DSP Program Trailer for DSP 1 /RO" |
| 90 |
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92 BUF_LEN_TRK_TRAILER_PRG_2 1 "TRK DSP Program Trailer for DSP 2 /RO" |
| 91 |
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93 BUF_LEN_TRK_TRAILER_PRG_3 1 "TRK DSP Program Trailer for DSP 3 /RO" |
| 92 |
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94 BUF_LEN_TRK_TRAILER_PRG_4 1 "TRK DSP Program Trailer for DSP 4 /RO" |
| 93 |
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95 BUF_LEN_TRK_TRAILER_PRG_5 1 "TRK DSP Program Trailer for DSP 5 /RO" |
| 94 |
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96 BUF_LEN_TRK_NUMBER_DSP_1_0 30 "TRK command queue /RO" |
| 95 |
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97 BUF_LEN_TRK_NUMBER_DSP_1_1 30 "TRK command queue /RO" |
| 96 |
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98 BUF_LEN_TRK_NUMBER_DSP_1_2 30 "TRK command queue /RO" |
| 97 |
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99 BUF_LEN_TRK_NUMBER_DSP_1_3 30 "TRK command queue /RO" |
| 98 |
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100 BUF_LEN_TRK_NUMBER_DSP_1_4 30 "TRK command queue /RO" |
| 99 |
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101 BUF_LEN_TRK_NUMBER_DSP_1_5 30 "TRK command queue /RO" |
| 100 |
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102 BUF_LEN_TRK_NUMBER_DSP_2_0 30 "TRK command queue /RO" |
| 101 |
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103 BUF_LEN_TRK_NUMBER_DSP_2_1 30 "TRK command queue /RO" |
| 102 |
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104 BUF_LEN_TRK_NUMBER_DSP_2_2 30 "TRK command queue /RO" |
| 103 |
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105 BUF_LEN_TRK_NUMBER_DSP_2_3 30 "TRK command queue /RO" |
| 104 |
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106 BUF_LEN_TRK_NUMBER_DSP_2_4 30 "TRK command queue /RO" |
| 105 |
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107 BUF_LEN_TRK_NUMBER_DSP_2_5 30 "TRK command queue /RO" |
| 106 |
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108 BUF_LEN_TRK_OPMODE_COMP_0 10 "TRK command queue /RO" |
| 107 |
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109 BUF_LEN_TRK_OPMODE_SPEC_0 10 "TRK command queue /RO" |
| 108 |
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110 BUF_LEN_TRK_OPMODE_COMP_1 10 "TRK command queue /RO" |
| 109 |
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111 BUF_LEN_TRK_OPMODE_SPEC_1 10 "TRK command queue /RO" |
| 110 |
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112 BUF_LEN_TRK_OPMODE_COMP_2 10 "TRK command queue /RO" |
| 111 |
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113 BUF_LEN_TRK_OPMODE_SPEC_2 10 "TRK command queue /RO" |
| 112 |
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114 BUF_LEN_TRK_OPMODE_COMP_3 10 "TRK command queue /RO" |
| 113 |
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115 BUF_LEN_TRK_OPMODE_SPEC_3 10 "TRK command queue /RO" |
| 114 |
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116 BUF_LEN_TRK_OPMODE_COMP_4 10 "TRK command queue /RO" |
| 115 |
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117 BUF_LEN_TRK_OPMODE_SPEC_4 10 "TRK command queue /RO" |
| 116 |
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118 BUF_LEN_TRK_OPMODE_COMP_5 10 "TRK command queue /RO" |
| 117 |
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119 BUF_LEN_TRK_OPMODE_SPEC_5 10 "TRK command queue /RO" |
| 118 |
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120 S4_OK 1 "S4 enable/disable /RO" |
| 119 |
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121 S4_TRH 16384 "S4 command /RO" |
| 120 |
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122 S4_ATTEMPT 0 "S4 force check /RO" |
| 121 |
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123 S4_WORKING 1 "check if S4 is working or not /RO" |
| 122 |
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124 CAL_UPLOAD_CAL_FE_MASK 15 "Defines the working read-out of calorimeter /RO" |
| 123 |
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125 CAL_UPLOAD_CAL_DSP_MASK 15 "Defines the workings dsps of calorimeter /RO" |
| 124 |
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126 CAL_VCAL 32773 "Variable modified by pulse calibration /RW" |
| 125 |
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127 CAL_CH 1 "Variable modified by pulse calibration /RW" |
| 126 |
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128 CAL_TEMP 5 "Maximum calorimeter temperature alarms /RO" |
| 127 |
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129 CAL_OK 1 "calo ON_OFF in ACQ /RW" |
| 128 |
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130 CAL_CHECK_FE 0 "calo check FE /RO" |
| 129 |
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131 BUF_LEN_CAL_WRITE_FPGA_REG_I211 8 "write fpga /RO" |
| 130 |
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132 BUF_LEN_CAL_WRITE_FPGA_REG_I221 8 "write fpga /RO" |
| 131 |
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133 BUF_LEN_CAL_WRITE_FPGA_REG_I231 8 "write fpga /RO" |
| 132 |
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136 BUF_LEN_CAL_WRITE_DSP_MEM_I43 14 "dsp prog i43 /RO" |
| 133 |
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137 BUF_LEN_CAL_READ_DSP_MEM_C31 10 "dsp prog c31 /RO" |
| 134 |
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138 BUF_LEN_CAL_READ_DSP_MEM_C32 10 "dsp prog c32 /RO" |
| 135 |
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139 BUF_LEN_CAL_WRITE_FPGA_REG_I241_1 8 "write fpga i241_1 /RO" |
| 136 |
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140 BUF_LEN_CAL_WRITE_FPGA_REG_I241_2 8 "write fpga i241_2 /RO" |
| 137 |
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141 BUF_LEN_CAL_WRITE_FPGA_REG_I241_3 8 "write fpga i241_3 /RO" |
| 138 |
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142 BUF_LEN_CAL_WRITE_FPGA_REG_I241_4 8 "write fpga i241_4 /RO" |
| 139 |
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143 BUF_LEN_CAL_WRITE_FPGA_REG_I251_1 8 "write fpga i251_1 /RO" |
| 140 |
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144 BUF_LEN_CAL_WRITE_FPGA_REG_I251_2 8 "write fpga i251_2 /RO" |
| 141 |
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145 BUF_LEN_CAL_WRITE_FPGA_REG_I251_3 8 "write fpga i251_3 /RO" |
| 142 |
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146 BUF_LEN_CAL_WRITE_FPGA_REG_I251_4 8 "write fpga i251_4 /RO" |
| 143 |
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147 BUF_LEN_CAL_WRITE_FPGA_REG_I261_1 8 "write fpga i261_1 /RO" |
| 144 |
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148 BUF_LEN_CAL_WRITE_FPGA_REG_I261_2 8 "write fpga i261_2 /RO" |
| 145 |
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149 BUF_LEN_CAL_WRITE_FPGA_REG_I261_3 8 "write fpga i261_3 /RO" |
| 146 |
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150 BUF_LEN_CAL_WRITE_FPGA_REG_I261_4 8 "write fpga i261_4 /RO" |
| 147 |
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151 BUF_LEN_CAL_WRITE_FPGA_REG_I260_1 8 "write fpga i260_1 /RO" |
| 148 |
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152 BUF_LEN_CAL_WRITE_FPGA_REG_I260_2 8 "write fpga i260_2 /RO" |
| 149 |
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153 BUF_LEN_CAL_WRITE_FPGA_REG_I260_3 8 "write fpga i260_3 /RO" |
| 150 |
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154 BUF_LEN_CAL_WRITE_FPGA_REG_I260_4 8 "write fpga i260_4 /RO" |
| 151 |
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155 BUF_LEN_CAL_WRITE_FPGA_REG_I311_1 8 "write fpga i311_1 /RO" |
| 152 |
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156 BUF_LEN_CAL_WRITE_FPGA_REG_I311_2 8 "write fpga i311_2 /RO" |
| 153 |
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157 BUF_LEN_CAL_WRITE_FPGA_REG_I311_3 8 "write fpga i311_3 /RO" |
| 154 |
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158 BUF_LEN_CAL_WRITE_FPGA_REG_I311_4 8 "write fpga i311_4 /RO" |
| 155 |
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159 BUF_LEN_CAL_WRITE_FPGA_REG_I310_1 8 "write fpga i310_1 /RO" |
| 156 |
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160 BUF_LEN_CAL_WRITE_FPGA_REG_I310_2 8 "write fpga i310_2 /RO" |
| 157 |
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161 BUF_LEN_CAL_WRITE_FPGA_REG_I310_3 8 "write fpga i310_3 /RO" |
| 158 |
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162 BUF_LEN_CAL_WRITE_FPGA_REG_I310_4 8 "write fpga i310_4 /RO" |
| 159 |
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163 BUF_LEN_CAL_WRITE_FPGA_REG_I321 8 "write fpga i321 /RO" |
| 160 |
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164 BUF_LEN_CAL_WRITE_FPGA_REG_I331_1 8 "write fpga i331_1 /RO" |
| 161 |
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165 BUF_LEN_CAL_WRITE_FPGA_REG_I331_2 8 "write fpga i331_2 /RO" |
| 162 |
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166 BUF_LEN_CAL_WRITE_FPGA_REG_I331_3 8 "write fpga i331_3 /RO" |
| 163 |
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167 BUF_LEN_CAL_WRITE_FPGA_REG_I331_4 8 "write fpga i331_4 /RO" |
| 164 |
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168 BUF_LEN_CAL_WRITE_FPGA_REG_OFF 8 "write fpga reg off /RO" |
| 165 |
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169 BUF_LEN_CAL_WRITE_FPGA_REG_I341_1 8 "write fpga i341_1 /RO" |
| 166 |
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170 BUF_LEN_CAL_WRITE_FPGA_REG_I341_2 8 "write fpga i341_2 /RO" |
| 167 |
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171 BUF_LEN_CAL_WRITE_FPGA_REG_I341_3 8 "write fpga i341_3 /RO" |
| 168 |
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172 BUF_LEN_CAL_WRITE_FPGA_REG_I341_4 8 "write fpga i341_4 /RO" |
| 169 |
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173 AC_1_OK 1 "AC ON_OFF in ACQ /RW" |
| 170 |
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174 AC_2_OK 1 "AC ON_OFF in ACQ /RW" |
| 171 |
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175 AC_1_CHECK 0 "AC check /RO" |
| 172 |
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176 AC_2_CHECK 0 "AC check /RO" |
| 173 |
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177 AC_LOOP 3 "AC max loop /RO" |
| 174 |
|
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178 AC_LOOP2 3 "AC max loop 2 /RO" |
| 175 |
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179 BUF_LEN_AC_1_SET_DAQ 132 "SET DAQ command /RO" |
| 176 |
|
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180 BUF_LEN_AC_2_SET_DAQ 132 "SET DAQ command /RO" |
| 177 |
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184 BUF_LEN_AC_2_WRITE_REG 54 "/RO" |
| 178 |
|
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185 BUF_LEN_AC_1_WRITE_REG 54 "/RO" |
| 179 |
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186 BUF_LEN_AC_READ_DSP_MEM 10 " /RO" |
| 180 |
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187 BUF_LEN_TOF_WRITE_PMT_THR_1 7 "TOF set THR front end 1 /RO" |
| 181 |
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188 BUF_LEN_TOF_WRITE_PMT_THR_2 7 "TOF set THR front end 2 /RO" |
| 182 |
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189 BUF_LEN_TOF_WRITE_PMT_THR_3 7 "TOF set THR front end 3 /RO" |
| 183 |
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190 BUF_LEN_TOF_WRITE_PMT_THR_4 7 "TOF set THR front end 4 /RO" |
| 184 |
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191 BUF_LEN_TOF_WRITE_PMT_THR_5 7 "TOF set THR front end 5 /RO" |
| 185 |
|
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192 BUF_LEN_TOF_WRITE_PMT_THR_6 7 "TOF set THR front end 5 /RO" |
| 186 |
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193 TOF_OK 1 "TOF ON_OFF in ACQ /RW" |
| 187 |
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194 ND_OK 1 "ND ON_OFF in ACQ /RW" |
| 188 |
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195 ND_ATTEMPT 0 "Force ND in ACQ (1), unless ND_OK is FALSE /RO" |
| 189 |
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196 ND_CMDS 3 "Force ND in ACQ, unless ND_OK is FALSE /RO" |
| 190 |
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197 SCM_TM_DO_CHECK_VALUES_FREQ 1 "Do a Check on TM values every XXX Number of cyc acq done /RO" |
| 191 |
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198 POWER_KHB 0 "Select KHB board 0==>HOT else COLD" |
| 192 |
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199 PSB_TRB_S9004_ALL_ON_DELAY 1000 "milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on) /RO" |
| 193 |
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200 PSB_TRB_BIAS_WAIT 3000 "wait between bias TRB switch on/off /RO" |
| 194 |
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201 PSB_CALOFE_DELAY 1000 "Delay before power on CALO 5.7 /RO" |
| 195 |
|
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202 HV_OK 1 "call HV settings after TRB setting at start-up /RO" |
| 196 |
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203 TSB_T_OK 1 "Do TSB Temperature check /RO" |
| 197 |
|
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204 TSB_B_OK 1 "Do B-field TSB check /RO" |
| 198 |
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205 ALLPAGEAVAIL_ATTEMPT 50 "ATTEMP TO ALLPAGE AVAILABLE" |
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| 
Revision Log