/[PAMELA software]/quicklook/dataToXML/Data/compilationInfo/PRH_ParamHandler_INFN_auto.var.xml
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Contents of /quicklook/dataToXML/Data/compilationInfo/PRH_ParamHandler_INFN_auto.var.xml

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Revision 1.1.1.1 - (show annotations) (download) (as text) (vendor branch)
Tue Apr 25 09:00:20 2006 UTC (18 years, 7 months ago) by kusanagi
Branch: MAIN
CVS Tags: dataToXML1_02/01, dataToXML1_02/00, dataToXML1_03/00, dataToXML1_03/01, dataToXML1_00/00, firstRelease, dataToXML1_01/00, dataToXML1_03_02, HEAD
Changes since 1.1: +0 -0 lines
File MIME type: text/xml 
These program extract in an XML format the info contained into the ROOT files generated by YODA from the PAMELA data. To visualize the XML files in a more human readable format a collection of XSL files are given in the Data subfolder.
1
2 <varxml>
3
4 <var>
5 <name>LU_WRITE_ON_UART</name>
6 <idx>0</idx>
7 <comment><![CDATA[enable[1]/disable[0] the UART writing /RO]]></comment>
8 </var>
9
10 <var>
11 <name>VERBOSE_DEBUG</name>
12 <idx>1</idx>
13 <comment><![CDATA[Verbose Debug mode]]></comment>
14 </var>
15
16 <var>
17 <name>DOWNLOAD_HEADER</name>
18 <idx>2</idx>
19 <comment><![CDATA[download counter, to be written in Download header info /RW-E2P]]></comment>
20 </var>
21
22 <var>
23 <name>KHB_ALARM_REG_LOW_LEVEL_MASK</name>
24 <idx>3</idx>
25 <comment><![CDATA[mask of KHB Alarm register to be low-level masked /RO]]></comment>
26 </var>
27
28 <var>
29 <name>KHB_STATUS_REG_LOW_LEVEL_MASK</name>
30 <idx>4</idx>
31 <comment><![CDATA[mask of KHB status register to be low-level masked /RO]]></comment>
32 </var>
33
34 <var>
35 <name>PULSER_ACTION</name>
36 <idx>5</idx>
37 <comment><![CDATA[pulser action at startup; [0=none,1=Reset,2:0.25Hz,3:100Hz] /RO]]></comment>
38 </var>
39
40 <var>
41 <name>N_BOOT</name>
42 <idx>6</idx>
43 <comment><![CDATA[Boot Counter /RW-E2P]]></comment>
44 </var>
45
46 <var>
47 <name>THERMISTORS_CHECK</name>
48 <idx>7</idx>
49 <comment><![CDATA[Check if thermistor are going to be checked /RO]]></comment>
50 </var>
51
52 <var>
53 <name>THERM_MASK</name>
54 <idx>8</idx>
55 <comment><![CDATA[Thermistors mask /RO]]></comment>
56 </var>
57
58 <var>
59 <name>IPM_VOLTAGES_CHECK</name>
60 <idx>9</idx>
61 <comment><![CDATA[Check if ipm are going to be checked /RO]]></comment>
62 </var>
63
64 <var>
65 <name>KHB_IDAQ_CHECK</name>
66 <idx>10</idx>
67 <comment><![CDATA[Check if khb&idaq are going to be checked /RO]]></comment>
68 </var>
69
70 <var>
71 <name>NTRIG</name>
72 <idx>11</idx>
73 <comment><![CDATA[Max Number of Lacks of Triggers /RO]]></comment>
74 </var>
75
76 <var>
77 <name>TRIG</name>
78 <idx>12</idx>
79 <comment><![CDATA[Counter of lacks of triggers /RW]]></comment>
80 </var>
81
82 <var>
83 <name>CONF_SEL</name>
84 <idx>13</idx>
85 <comment><![CDATA[active sensor selector /RW]]></comment>
86 </var>
87
88 <var>
89 <name>CONFOK</name>
90 <idx>14</idx>
91 <comment><![CDATA[whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON /RO]]></comment>
92 </var>
93
94 <var>
95 <name>OFF</name>
96 <idx>15</idx>
97 <comment><![CDATA[Counter of ON/OFF /RW]]></comment>
98 </var>
99
100 <var>
101 <name>NOFF</name>
102 <idx>16</idx>
103 <comment><![CDATA[Max Number of ON/OFF /RO]]></comment>
104 </var>
105
106 <var>
107 <name>NRES</name>
108 <idx>17</idx>
109 <comment><![CDATA[Max number of reset /RO]]></comment>
110 </var>
111
112 <var>
113 <name>RES</name>
114 <idx>18</idx>
115 <comment><![CDATA[Counter of reset /RW]]></comment>
116 </var>
117
118 <var>
119 <name>WATCHDOG_RESET_DISABLE</name>
120 <idx>19</idx>
121 <comment><![CDATA[disable watchdog reset: only for debugging!]]></comment>
122 </var>
123
124 <var>
125 <name>NFAILED_POWER_ON</name>
126 <idx>20</idx>
127 <comment><![CDATA[max number of failed power_on, before STOP&WAIT /RO]]></comment>
128 </var>
129
130 <var>
131 <name>AUTO_RM_MODE</name>
132 <idx>21</idx>
133 <comment><![CDATA[define the Automatic Mode for RM /RO]]></comment>
134 </var>
135
136 <var>
137 <name>AUTO_SCM_MODE</name>
138 <idx>22</idx>
139 <comment><![CDATA[define the Automatic Mode for scm /RO]]></comment>
140 </var>
141
142 <var>
143 <name>MASK_ACQ_ALARM</name>
144 <idx>23</idx>
145 <comment><![CDATA[Alarm mask /RO]]></comment>
146 </var>
147
148 <var>
149 <name>GOM_DURING_ALARM</name>
150 <idx>24</idx>
151 <comment><![CDATA[General operation mode during alarm revelation /RW]]></comment>
152 </var>
153
154 <var>
155 <name>PM_FORCE_RUNNING_TIMEOUT</name>
156 <idx>25</idx>
157 <comment><![CDATA[waiting for start select mode before force go to running]]></comment>
158 </var>
159
160 <var>
161 <name>PAMELA_ON</name>
162 <idx>26</idx>
163 <comment><![CDATA[Pamela status [0=OFF-1:OFF] /RW]]></comment>
164 </var>
165
166 <var>
167 <name>N_CALIB</name>
168 <idx>27</idx>
169 <comment><![CDATA[Counter of calibratrion since start up /RW]]></comment>
170 </var>
171
172 <var>
173 <name>AC_1_ON</name>
174 <idx>28</idx>
175 <comment><![CDATA[AC 1 on from initialization /RW]]></comment>
176 </var>
177
178 <var>
179 <name>AC_2_ON</name>
180 <idx>29</idx>
181 <comment><![CDATA[AC 2 on from initialization /RW]]></comment>
182 </var>
183
184 <var>
185 <name>POWER_MODE</name>
186 <idx>30</idx>
187 <comment><![CDATA[Power mode of PAMELA /RW]]></comment>
188 </var>
189
190 <var>
191 <name>TRIG_II</name>
192 <idx>31</idx>
193 <comment><![CDATA[TRIGGER II level mode on/off /RO]]></comment>
194 </var>
195
196 <var>
197 <name>BUF_LEN_TRIG_II_INIT</name>
198 <idx>32</idx>
199 <comment><![CDATA[TRIG_II init command queue]]></comment>
200 </var>
201
202 <var>
203 <name>BUF_LEN_TRIG_II_ACQ</name>
204 <idx>33</idx>
205 <comment><![CDATA[TRIG_II acq command queue]]></comment>
206 </var>
207
208 <var>
209 <name>EXP64_MODE</name>
210 <idx>34</idx>
211 <comment><![CDATA[if TRUE, working in exp 64 mode /RO]]></comment>
212 </var>
213
214 <var>
215 <name>EXP64_MODE_DELAY</name>
216 <idx>35</idx>
217 <comment><![CDATA[delay for exp 64 mode acquiring /RO]]></comment>
218 </var>
219
220 <var>
221 <name>MH_END_OF_DOWNLOAD_TIMEOUT</name>
222 <idx>36</idx>
223 <comment><![CDATA[time out of the end of download /RO]]></comment>
224 </var>
225
226 <var>
227 <name>PM_STOP_RUNMANAGER_TIMEOUT</name>
228 <idx>37</idx>
229 <comment><![CDATA[the maximu time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager /RO]]></comment>
230 </var>
231
232 <var>
233 <name>PM_STOP_RUNMANAGER_TIMES_RETRY</name>
234 <idx>38</idx>
235 <comment><![CDATA[The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle. /RO]]></comment>
236 </var>
237
238 <var>
239 <name>PM_N_ORBIT_CALIB</name>
240 <idx>39</idx>
241 <comment><![CDATA[Number of orbits per calibration /RO]]></comment>
242 </var>
243
244 <var>
245 <name>WS_TIME_ORBIT</name>
246 <idx>40</idx>
247 <comment><![CDATA[The duration in millisencond of the full orbit in ms /RO]]></comment>
248 </var>
249
250 <var>
251 <name>WS_FAVOURITE_WS</name>
252 <idx>41</idx>
253 <comment><![CDATA[The Favourite Pamela Working Schedule /RO]]></comment>
254 </var>
255
256 <var>
257 <name>RM_N_TRIES_PREPARE_PAGE</name>
258 <idx>42</idx>
259 <comment><![CDATA[Number of attempts to try to exec the prepar page before exit from the run procedure with an error /RO]]></comment>
260 </var>
261
262 <var>
263 <name>RM_TRIES_PREPARE_PAGE_SLEEP</name>
264 <idx>43</idx>
265 <comment><![CDATA[Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure /RO]]></comment>
266 </var>
267
268 <var>
269 <name>RM_WS3_TIMER_FIRE_AFTER</name>
270 <idx>44</idx>
271 <comment><![CDATA[Time to wait for the WS3 timer to fire /RO]]></comment>
272 </var>
273
274 <var>
275 <name>RM_TIME_MAX_RUN</name>
276 <idx>45</idx>
277 <comment><![CDATA[Max duration for an ordinary Run in milliseconds /RO]]></comment>
278 </var>
279
280 <var>
281 <name>RM_TIME_SPECIAL_RUN</name>
282 <idx>46</idx>
283 <comment><![CDATA[duration for the special run in milliseconds /RO]]></comment>
284 </var>
285
286 <var>
287 <name>RM_ACQCHECK_PERIOD</name>
288 <idx>47</idx>
289 <comment><![CDATA[period of acquisition check in milliseconds /RO]]></comment>
290 </var>
291
292 <var>
293 <name>RM_FLUSH_TIMEOUT</name>
294 <idx>48</idx>
295 <comment><![CDATA[timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT /RO]]></comment>
296 </var>
297
298 <var>
299 <name>RM_NO_FLUSH_PARAM_DUMP</name>
300 <idx>49</idx>
301 <comment><![CDATA[Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never. /RO]]></comment>
302 </var>
303
304 <var>
305 <name>RM_DUMP_ALL_PARAMS</name>
306 <idx>50</idx>
307 <comment><![CDATA[dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs /RO]]></comment>
308 </var>
309
310 <var>
311 <name>RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ</name>
312 <idx>51</idx>
313 <comment><![CDATA[number of release busy inserted in the ACQ command queue in After_Calib mode /RO]]></comment>
314 </var>
315
316 <var>
317 <name>PWR_WAIT_BEFORE_SENDTC</name>
318 <idx>52</idx>
319 <comment><![CDATA[time to wait before send 2 successive HL /RO]]></comment>
320 </var>
321
322 <var>
323 <name>PWR_CMD2PSB_DELAY</name>
324 <idx>53</idx>
325 <comment><![CDATA[time to wait before every CMD2PSB]]></comment>
326 </var>
327
328 <var>
329 <name>PWR_TRB_READ_ATTEMPTS</name>
330 <idx>54</idx>
331 <comment><![CDATA[number of attempts to sent a command to the TRB before a timeout /RO]]></comment>
332 </var>
333
334 <var>
335 <name>PWR_KHB_INITBOARD_TWICE_DELAY</name>
336 <idx>55</idx>
337 <comment><![CDATA[milliseconds to wait between two KHB Init Board in PWR_DcdcON /RO]]></comment>
338 </var>
339
340 <var>
341 <name>PWR_IPM_WAIT_OK_N_ATTEMPT</name>
342 <idx>56</idx>
343 <comment><![CDATA[attempts of ipm check ok at power on /RO]]></comment>
344 </var>
345
346 <var>
347 <name>PWR_IPM_WAIT_OK_DELAY_ATTEMPT</name>
348 <idx>57</idx>
349 <comment><![CDATA[attempts of ipm check ok at power on /RO]]></comment>
350 </var>
351
352 <var>
353 <name>PWR_VOLTAGE_N_ATTEMPT</name>
354 <idx>58</idx>
355 <comment><![CDATA[no of millisecond to wait in VOLTAGE IPM procedure /RO]]></comment>
356 </var>
357
358 <var>
359 <name>PWR_VOLTAGE_DELAY_ATTEMPT</name>
360 <idx>59</idx>
361 <comment><![CDATA[no of millisecond to wain in VOLTAGE IPM procedure /RO]]></comment>
362 </var>
363
364 <var>
365 <name>PWR_TRB1_SET</name>
366 <idx>60</idx>
367 <comment><![CDATA[trb 1 setting /RO]]></comment>
368 </var>
369
370 <var>
371 <name>PWR_TRB2_SET</name>
372 <idx>61</idx>
373 <comment><![CDATA[trb 2 setting /RO]]></comment>
374 </var>
375
376 <var>
377 <name>PWR_TRB_SET_DELAY</name>
378 <idx>62</idx>
379 <comment><![CDATA[delay after trb set cmd /RO]]></comment>
380 </var>
381
382 <var>
383 <name>PWR_TRB_READ_DELAY</name>
384 <idx>63</idx>
385 <comment><![CDATA[delay after trb read cmd /RO]]></comment>
386 </var>
387
388 <var>
389 <name>HB_N_ATTEMPT_WRITE2PIF</name>
390 <idx>64</idx>
391 <comment><![CDATA[Number of attempt to write on PIF after return an error /RO]]></comment>
392 </var>
393
394 <var>
395 <name>HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF</name>
396 <idx>65</idx>
397 <comment><![CDATA[Waint time after a failed attempt on PIF write /RO]]></comment>
398 </var>
399
400 <var>
401 <name>HB_WRITE2PIF_TIMEOUT</name>
402 <idx>66</idx>
403 <comment><![CDATA[timeout time time to wait a sketchboard free in Write2PIF /RO]]></comment>
404 </var>
405
406 <var>
407 <name>HB_ALMOST_FULL</name>
408 <idx>67</idx>
409 <comment><![CDATA[says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage. /RM]]></comment>
410 </var>
411
412 <var>
413 <name>TM_VRL_SUSPEND_HCL</name>
414 <idx>68</idx>
415 <comment><![CDATA[wait time between two HCL commands for the VRL /RO]]></comment>
416 </var>
417
418 <var>
419 <name>TM_VRL_SUSPEND_BEFORE_START</name>
420 <idx>69</idx>
421 <comment><![CDATA[wait time before start VRL /RO]]></comment>
422 </var>
423
424 <var>
425 <name>DAQ_EVENT_RECEIVE_TIMEOUT</name>
426 <idx>70</idx>
427 <comment><![CDATA[PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply /RO]]></comment>
428 </var>
429
430 <var>
431 <name>DAQ_WAITFREECMDIF_N</name>
432 <idx>71</idx>
433 <comment><![CDATA[Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched /RO]]></comment>
434 </var>
435
436 <var>
437 <name>TRB_OK</name>
438 <idx>72</idx>
439 <comment><![CDATA[Use ON_OFF tracker in ACQ /RO]]></comment>
440 </var>
441
442 <var>
443 <name>TRIGGER_MODE_A</name>
444 <idx>73</idx>
445 <comment><![CDATA[Trigger type for acq mode A /RO]]></comment>
446 </var>
447
448 <var>
449 <name>TRIGGER_MODE_B</name>
450 <idx>74</idx>
451 <comment><![CDATA[Trigger type for acq mode B /RO]]></comment>
452 </var>
453
454 <var>
455 <name>TRIGGER_BUSY_CONTROL</name>
456 <idx>75</idx>
457 <comment><![CDATA[Select the check mask of the busy alaarm /RO]]></comment>
458 </var>
459
460 <var>
461 <name>TB_LINK</name>
462 <idx>76</idx>
463 <comment><![CDATA[Trigger Board to use 1 or 2 /RO]]></comment>
464 </var>
465
466 <var>
467 <name>TB_LINK_CUSTOM</name>
468 <idx>77</idx>
469 <comment><![CDATA[Trigger Board CUSTOMto use 1 or 2 /RO]]></comment>
470 </var>
471
472 <var>
473 <name>BUF_LEN_TB_SET_ALARM_MASK</name>
474 <idx>78</idx>
475 <comment><![CDATA[TRG queue]]></comment>
476 </var>
477
478 <var>
479 <name>BUF_LEN_TB_SET_PMT_MASK</name>
480 <idx>79</idx>
481 <comment><![CDATA[TRG queue]]></comment>
482 </var>
483
484 <var>
485 <name>BUF_LEN_TB_SET_S4_CAL_MASK</name>
486 <idx>80</idx>
487 <comment><![CDATA[TRG queue]]></comment>
488 </var>
489
490 <var>
491 <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT</name>
492 <idx>81</idx>
493 <comment><![CDATA[ ]]></comment>
494 </var>
495
496 <var>
497 <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD</name>
498 <idx>82</idx>
499 <comment><![CDATA[ ]]></comment>
500 </var>
501
502 <var>
503 <name>TRK_OK</name>
504 <idx>83</idx>
505 <comment><![CDATA[Use ON_OFF tracker in ACQ /RO]]></comment>
506 </var>
507
508 <var>
509 <name>TRK_CALIB_MODE</name>
510 <idx>84</idx>
511 <comment><![CDATA[Tracker calibration mode /RO]]></comment>
512 </var>
513
514 <var>
515 <name>TRK_TIME_SHORT</name>
516 <idx>85</idx>
517 <comment><![CDATA[Tracker wait loop for 128 loop /RO]]></comment>
518 </var>
519
520 <var>
521 <name>TRK_TIME_LONG</name>
522 <idx>86</idx>
523 <comment><![CDATA[Tracker wait loop for 8 loop /RO]]></comment>
524 </var>
525
526 <var>
527 <name>TRK_CALIB_INIT</name>
528 <idx>87</idx>
529 <comment><![CDATA[modality of calibration /RO]]></comment>
530 </var>
531
532 <var>
533 <name>TRK_NLOOP</name>
534 <idx>88</idx>
535 <comment><![CDATA[macro loop number /RO]]></comment>
536 </var>
537
538 <var>
539 <name>BUF_LEN_TRK_PROGRAM</name>
540 <idx>89</idx>
541 <comment><![CDATA[TRK DSP Program /RO]]></comment>
542 </var>
543
544 <var>
545 <name>BUF_LEN_TRK_TRAILER_PRG_0</name>
546 <idx>90</idx>
547 <comment><![CDATA[TRK DSP Program Trailer for DSP 0 /RO]]></comment>
548 </var>
549
550 <var>
551 <name>BUF_LEN_TRK_TRAILER_PRG_1</name>
552 <idx>91</idx>
553 <comment><![CDATA[TRK DSP Program Trailer for DSP 1 /RO]]></comment>
554 </var>
555
556 <var>
557 <name>BUF_LEN_TRK_TRAILER_PRG_2</name>
558 <idx>92</idx>
559 <comment><![CDATA[TRK DSP Program Trailer for DSP 2 /RO]]></comment>
560 </var>
561
562 <var>
563 <name>BUF_LEN_TRK_TRAILER_PRG_3</name>
564 <idx>93</idx>
565 <comment><![CDATA[TRK DSP Program Trailer for DSP 3 /RO]]></comment>
566 </var>
567
568 <var>
569 <name>BUF_LEN_TRK_TRAILER_PRG_4</name>
570 <idx>94</idx>
571 <comment><![CDATA[TRK DSP Program Trailer for DSP 4 /RO]]></comment>
572 </var>
573
574 <var>
575 <name>BUF_LEN_TRK_TRAILER_PRG_5</name>
576 <idx>95</idx>
577 <comment><![CDATA[TRK DSP Program Trailer for DSP 5 /RO]]></comment>
578 </var>
579
580 <var>
581 <name>BUF_LEN_TRK_NUMBER_DSP_1_0</name>
582 <idx>96</idx>
583 <comment><![CDATA[TRK command queue /RO]]></comment>
584 </var>
585
586 <var>
587 <name>BUF_LEN_TRK_NUMBER_DSP_1_1</name>
588 <idx>97</idx>
589 <comment><![CDATA[TRK command queue /RO]]></comment>
590 </var>
591
592 <var>
593 <name>BUF_LEN_TRK_NUMBER_DSP_1_2</name>
594 <idx>98</idx>
595 <comment><![CDATA[TRK command queue /RO]]></comment>
596 </var>
597
598 <var>
599 <name>BUF_LEN_TRK_NUMBER_DSP_1_3</name>
600 <idx>99</idx>
601 <comment><![CDATA[TRK command queue /RO]]></comment>
602 </var>
603
604 <var>
605 <name>BUF_LEN_TRK_NUMBER_DSP_1_4</name>
606 <idx>100</idx>
607 <comment><![CDATA[TRK command queue /RO]]></comment>
608 </var>
609
610 <var>
611 <name>BUF_LEN_TRK_NUMBER_DSP_1_5</name>
612 <idx>101</idx>
613 <comment><![CDATA[TRK command queue /RO]]></comment>
614 </var>
615
616 <var>
617 <name>BUF_LEN_TRK_NUMBER_DSP_2_0</name>
618 <idx>102</idx>
619 <comment><![CDATA[TRK command queue /RO]]></comment>
620 </var>
621
622 <var>
623 <name>BUF_LEN_TRK_NUMBER_DSP_2_1</name>
624 <idx>103</idx>
625 <comment><![CDATA[TRK command queue /RO]]></comment>
626 </var>
627
628 <var>
629 <name>BUF_LEN_TRK_NUMBER_DSP_2_2</name>
630 <idx>104</idx>
631 <comment><![CDATA[TRK command queue /RO]]></comment>
632 </var>
633
634 <var>
635 <name>BUF_LEN_TRK_NUMBER_DSP_2_3</name>
636 <idx>105</idx>
637 <comment><![CDATA[TRK command queue /RO]]></comment>
638 </var>
639
640 <var>
641 <name>BUF_LEN_TRK_NUMBER_DSP_2_4</name>
642 <idx>106</idx>
643 <comment><![CDATA[TRK command queue /RO]]></comment>
644 </var>
645
646 <var>
647 <name>BUF_LEN_TRK_NUMBER_DSP_2_5</name>
648 <idx>107</idx>
649 <comment><![CDATA[TRK command queue /RO]]></comment>
650 </var>
651
652 <var>
653 <name>BUF_LEN_TRK_OPMODE_COMP_0</name>
654 <idx>108</idx>
655 <comment><![CDATA[TRK command queue /RO]]></comment>
656 </var>
657
658 <var>
659 <name>BUF_LEN_TRK_OPMODE_SPEC_0</name>
660 <idx>109</idx>
661 <comment><![CDATA[TRK command queue /RO]]></comment>
662 </var>
663
664 <var>
665 <name>BUF_LEN_TRK_OPMODE_COMP_1</name>
666 <idx>110</idx>
667 <comment><![CDATA[TRK command queue /RO]]></comment>
668 </var>
669
670 <var>
671 <name>BUF_LEN_TRK_OPMODE_SPEC_1</name>
672 <idx>111</idx>
673 <comment><![CDATA[TRK command queue /RO]]></comment>
674 </var>
675
676 <var>
677 <name>BUF_LEN_TRK_OPMODE_COMP_2</name>
678 <idx>112</idx>
679 <comment><![CDATA[TRK command queue /RO]]></comment>
680 </var>
681
682 <var>
683 <name>BUF_LEN_TRK_OPMODE_SPEC_2</name>
684 <idx>113</idx>
685 <comment><![CDATA[TRK command queue /RO]]></comment>
686 </var>
687
688 <var>
689 <name>BUF_LEN_TRK_OPMODE_COMP_3</name>
690 <idx>114</idx>
691 <comment><![CDATA[TRK command queue /RO]]></comment>
692 </var>
693
694 <var>
695 <name>BUF_LEN_TRK_OPMODE_SPEC_3</name>
696 <idx>115</idx>
697 <comment><![CDATA[TRK command queue /RO]]></comment>
698 </var>
699
700 <var>
701 <name>BUF_LEN_TRK_OPMODE_COMP_4</name>
702 <idx>116</idx>
703 <comment><![CDATA[TRK command queue /RO]]></comment>
704 </var>
705
706 <var>
707 <name>BUF_LEN_TRK_OPMODE_SPEC_4</name>
708 <idx>117</idx>
709 <comment><![CDATA[TRK command queue /RO]]></comment>
710 </var>
711
712 <var>
713 <name>BUF_LEN_TRK_OPMODE_COMP_5</name>
714 <idx>118</idx>
715 <comment><![CDATA[TRK command queue /RO]]></comment>
716 </var>
717
718 <var>
719 <name>BUF_LEN_TRK_OPMODE_SPEC_5</name>
720 <idx>119</idx>
721 <comment><![CDATA[TRK command queue /RO]]></comment>
722 </var>
723
724 <var>
725 <name>S4_OK</name>
726 <idx>120</idx>
727 <comment><![CDATA[S4 enable/disable /RO]]></comment>
728 </var>
729
730 <var>
731 <name>S4_TRH</name>
732 <idx>121</idx>
733 <comment><![CDATA[S4 command /RO]]></comment>
734 </var>
735
736 <var>
737 <name>S4_ATTEMPT</name>
738 <idx>122</idx>
739 <comment><![CDATA[S4 force check /RO]]></comment>
740 </var>
741
742 <var>
743 <name>S4_WORKING</name>
744 <idx>123</idx>
745 <comment><![CDATA[check if S4 is working or not /RO]]></comment>
746 </var>
747
748 <var>
749 <name>CAL_UPLOAD_CAL_FE_MASK</name>
750 <idx>124</idx>
751 <comment><![CDATA[Defines the working read-out of calorimeter /RO]]></comment>
752 </var>
753
754 <var>
755 <name>CAL_UPLOAD_CAL_DSP_MASK</name>
756 <idx>125</idx>
757 <comment><![CDATA[Defines the workings dsps of calorimeter /RO]]></comment>
758 </var>
759
760 <var>
761 <name>CAL_VCAL</name>
762 <idx>126</idx>
763 <comment><![CDATA[Variable modified by pulse calibration /RW]]></comment>
764 </var>
765
766 <var>
767 <name>CAL_CH</name>
768 <idx>127</idx>
769 <comment><![CDATA[Variable modified by pulse calibration /RW]]></comment>
770 </var>
771
772 <var>
773 <name>CAL_TEMP</name>
774 <idx>128</idx>
775 <comment><![CDATA[Maximum calorimeter temperature alarms /RO]]></comment>
776 </var>
777
778 <var>
779 <name>CAL_OK</name>
780 <idx>129</idx>
781 <comment><![CDATA[calo ON_OFF in ACQ /RW]]></comment>
782 </var>
783
784 <var>
785 <name>CAL_CHECK_FE</name>
786 <idx>130</idx>
787 <comment><![CDATA[calo check FE /RO]]></comment>
788 </var>
789
790 <var>
791 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I211</name>
792 <idx>131</idx>
793 <comment><![CDATA[write fpga /RO]]></comment>
794 </var>
795
796 <var>
797 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I221</name>
798 <idx>132</idx>
799 <comment><![CDATA[write fpga /RO]]></comment>
800 </var>
801
802 <var>
803 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I231</name>
804 <idx>133</idx>
805 <comment><![CDATA[write fpga /RO]]></comment>
806 </var>
807
808 <var>
809 <name>BUF_LEN_CAL_WRITE_DSP_MEM_I41</name>
810 <idx>134</idx>
811 <comment><![CDATA[dsp prog i41 /R0]]></comment>
812 </var>
813
814 <var>
815 <name>BUF_LEN_CAL_WRITE_DSP_MEM_I42</name>
816 <idx>135</idx>
817 <comment><![CDATA[dsp prog i42 /RO]]></comment>
818 </var>
819
820 <var>
821 <name>BUF_LEN_CAL_WRITE_DSP_MEM_I43</name>
822 <idx>136</idx>
823 <comment><![CDATA[dsp prog i43 /RO]]></comment>
824 </var>
825
826 <var>
827 <name>BUF_LEN_CAL_READ_DSP_MEM_C31</name>
828 <idx>137</idx>
829 <comment><![CDATA[dsp prog c31 /RO]]></comment>
830 </var>
831
832 <var>
833 <name>BUF_LEN_CAL_READ_DSP_MEM_C32</name>
834 <idx>138</idx>
835 <comment><![CDATA[dsp prog c32 /RO]]></comment>
836 </var>
837
838 <var>
839 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_1</name>
840 <idx>139</idx>
841 <comment><![CDATA[write fpga i241_1 /RO]]></comment>
842 </var>
843
844 <var>
845 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_2</name>
846 <idx>140</idx>
847 <comment><![CDATA[write fpga i241_2 /RO]]></comment>
848 </var>
849
850 <var>
851 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_3</name>
852 <idx>141</idx>
853 <comment><![CDATA[write fpga i241_3 /RO]]></comment>
854 </var>
855
856 <var>
857 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_4</name>
858 <idx>142</idx>
859 <comment><![CDATA[write fpga i241_4 /RO]]></comment>
860 </var>
861
862 <var>
863 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_1</name>
864 <idx>143</idx>
865 <comment><![CDATA[write fpga i251_1 /RO]]></comment>
866 </var>
867
868 <var>
869 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_2</name>
870 <idx>144</idx>
871 <comment><![CDATA[write fpga i251_2 /RO]]></comment>
872 </var>
873
874 <var>
875 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_3</name>
876 <idx>145</idx>
877 <comment><![CDATA[write fpga i251_3 /RO]]></comment>
878 </var>
879
880 <var>
881 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_4</name>
882 <idx>146</idx>
883 <comment><![CDATA[write fpga i251_4 /RO]]></comment>
884 </var>
885
886 <var>
887 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_1</name>
888 <idx>147</idx>
889 <comment><![CDATA[write fpga i261_1 /RO]]></comment>
890 </var>
891
892 <var>
893 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_2</name>
894 <idx>148</idx>
895 <comment><![CDATA[write fpga i261_2 /RO]]></comment>
896 </var>
897
898 <var>
899 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_3</name>
900 <idx>149</idx>
901 <comment><![CDATA[write fpga i261_3 /RO]]></comment>
902 </var>
903
904 <var>
905 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_4</name>
906 <idx>150</idx>
907 <comment><![CDATA[write fpga i261_4 /RO]]></comment>
908 </var>
909
910 <var>
911 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_1</name>
912 <idx>151</idx>
913 <comment><![CDATA[write fpga i260_1 /RO]]></comment>
914 </var>
915
916 <var>
917 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_2</name>
918 <idx>152</idx>
919 <comment><![CDATA[write fpga i260_2 /RO]]></comment>
920 </var>
921
922 <var>
923 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_3</name>
924 <idx>153</idx>
925 <comment><![CDATA[write fpga i260_3 /RO]]></comment>
926 </var>
927
928 <var>
929 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_4</name>
930 <idx>154</idx>
931 <comment><![CDATA[write fpga i260_4 /RO]]></comment>
932 </var>
933
934 <var>
935 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_1</name>
936 <idx>155</idx>
937 <comment><![CDATA[write fpga i311_1 /RO]]></comment>
938 </var>
939
940 <var>
941 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_2</name>
942 <idx>156</idx>
943 <comment><![CDATA[write fpga i311_2 /RO]]></comment>
944 </var>
945
946 <var>
947 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_3</name>
948 <idx>157</idx>
949 <comment><![CDATA[write fpga i311_3 /RO]]></comment>
950 </var>
951
952 <var>
953 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_4</name>
954 <idx>158</idx>
955 <comment><![CDATA[write fpga i311_4 /RO]]></comment>
956 </var>
957
958 <var>
959 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_1</name>
960 <idx>159</idx>
961 <comment><![CDATA[write fpga i310_1 /RO]]></comment>
962 </var>
963
964 <var>
965 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_2</name>
966 <idx>160</idx>
967 <comment><![CDATA[write fpga i310_2 /RO]]></comment>
968 </var>
969
970 <var>
971 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_3</name>
972 <idx>161</idx>
973 <comment><![CDATA[write fpga i310_3 /RO]]></comment>
974 </var>
975
976 <var>
977 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_4</name>
978 <idx>162</idx>
979 <comment><![CDATA[write fpga i310_4 /RO]]></comment>
980 </var>
981
982 <var>
983 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I321</name>
984 <idx>163</idx>
985 <comment><![CDATA[write fpga i321 /RO]]></comment>
986 </var>
987
988 <var>
989 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_1</name>
990 <idx>164</idx>
991 <comment><![CDATA[write fpga i331_1 /RO]]></comment>
992 </var>
993
994 <var>
995 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_2</name>
996 <idx>165</idx>
997 <comment><![CDATA[write fpga i331_2 /RO]]></comment>
998 </var>
999
1000 <var>
1001 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_3</name>
1002 <idx>166</idx>
1003 <comment><![CDATA[write fpga i331_3 /RO]]></comment>
1004 </var>
1005
1006 <var>
1007 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_4</name>
1008 <idx>167</idx>
1009 <comment><![CDATA[write fpga i331_4 /RO]]></comment>
1010 </var>
1011
1012 <var>
1013 <name>BUF_LEN_CAL_WRITE_FPGA_REG_OFF</name>
1014 <idx>168</idx>
1015 <comment><![CDATA[write fpga reg off /RO]]></comment>
1016 </var>
1017
1018 <var>
1019 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_1</name>
1020 <idx>169</idx>
1021 <comment><![CDATA[write fpga i341_1 /RO]]></comment>
1022 </var>
1023
1024 <var>
1025 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_2</name>
1026 <idx>170</idx>
1027 <comment><![CDATA[write fpga i341_2 /RO]]></comment>
1028 </var>
1029
1030 <var>
1031 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_3</name>
1032 <idx>171</idx>
1033 <comment><![CDATA[write fpga i341_3 /RO]]></comment>
1034 </var>
1035
1036 <var>
1037 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_4</name>
1038 <idx>172</idx>
1039 <comment><![CDATA[write fpga i341_4 /RO]]></comment>
1040 </var>
1041
1042 <var>
1043 <name>AC_1_OK</name>
1044 <idx>173</idx>
1045 <comment><![CDATA[AC ON_OFF in ACQ /RW]]></comment>
1046 </var>
1047
1048 <var>
1049 <name>AC_2_OK</name>
1050 <idx>174</idx>
1051 <comment><![CDATA[AC ON_OFF in ACQ /RW]]></comment>
1052 </var>
1053
1054 <var>
1055 <name>AC_1_CHECK</name>
1056 <idx>175</idx>
1057 <comment><![CDATA[AC check /RO]]></comment>
1058 </var>
1059
1060 <var>
1061 <name>AC_2_CHECK</name>
1062 <idx>176</idx>
1063 <comment><![CDATA[AC check /RO]]></comment>
1064 </var>
1065
1066 <var>
1067 <name>AC_LOOP</name>
1068 <idx>177</idx>
1069 <comment><![CDATA[AC max loop /RO]]></comment>
1070 </var>
1071
1072 <var>
1073 <name>AC_LOOP2</name>
1074 <idx>178</idx>
1075 <comment><![CDATA[AC max loop 2 /RO]]></comment>
1076 </var>
1077
1078 <var>
1079 <name>BUF_LEN_AC_1_SET_DAQ</name>
1080 <idx>179</idx>
1081 <comment><![CDATA[SET DAQ command /RO]]></comment>
1082 </var>
1083
1084 <var>
1085 <name>BUF_LEN_AC_2_SET_DAQ</name>
1086 <idx>180</idx>
1087 <comment><![CDATA[SET DAQ command /RO]]></comment>
1088 </var>
1089
1090 <var>
1091 <name>BUF_LEN_AC_SEND_DSP_PROG1</name>
1092 <idx>181</idx>
1093 <comment><![CDATA[DSP Program 1 /RO]]></comment>
1094 </var>
1095
1096 <var>
1097 <name>BUF_LEN_AC_1_SEND_DSP_PROG2</name>
1098 <idx>182</idx>
1099 <comment><![CDATA[ /RO]]></comment>
1100 </var>
1101
1102 <var>
1103 <name>BUF_LEN_AC_2_SEND_DSP_PROG2</name>
1104 <idx>183</idx>
1105 <comment><![CDATA[ /RO]]></comment>
1106 </var>
1107
1108 <var>
1109 <name>BUF_LEN_AC_2_WRITE_REG</name>
1110 <idx>184</idx>
1111 <comment><![CDATA[/RO]]></comment>
1112 </var>
1113
1114 <var>
1115 <name>BUF_LEN_AC_1_WRITE_REG</name>
1116 <idx>185</idx>
1117 <comment><![CDATA[/RO]]></comment>
1118 </var>
1119
1120 <var>
1121 <name>BUF_LEN_AC_READ_DSP_MEM</name>
1122 <idx>186</idx>
1123 <comment><![CDATA[ /RO]]></comment>
1124 </var>
1125
1126 <var>
1127 <name>BUF_LEN_TOF_WRITE_PMT_THR_1</name>
1128 <idx>187</idx>
1129 <comment><![CDATA[TOF set THR front end 1 /RO]]></comment>
1130 </var>
1131
1132 <var>
1133 <name>BUF_LEN_TOF_WRITE_PMT_THR_2</name>
1134 <idx>188</idx>
1135 <comment><![CDATA[TOF set THR front end 2 /RO]]></comment>
1136 </var>
1137
1138 <var>
1139 <name>BUF_LEN_TOF_WRITE_PMT_THR_3</name>
1140 <idx>189</idx>
1141 <comment><![CDATA[TOF set THR front end 3 /RO]]></comment>
1142 </var>
1143
1144 <var>
1145 <name>BUF_LEN_TOF_WRITE_PMT_THR_4</name>
1146 <idx>190</idx>
1147 <comment><![CDATA[TOF set THR front end 4 /RO]]></comment>
1148 </var>
1149
1150 <var>
1151 <name>BUF_LEN_TOF_WRITE_PMT_THR_5</name>
1152 <idx>191</idx>
1153 <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
1154 </var>
1155
1156 <var>
1157 <name>BUF_LEN_TOF_WRITE_PMT_THR_6</name>
1158 <idx>192</idx>
1159 <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
1160 </var>
1161
1162 <var>
1163 <name>TOF_OK</name>
1164 <idx>193</idx>
1165 <comment><![CDATA[TOF ON_OFF in ACQ /RW]]></comment>
1166 </var>
1167
1168 <var>
1169 <name>ND_OK</name>
1170 <idx>194</idx>
1171 <comment><![CDATA[ND ON_OFF in ACQ /RW]]></comment>
1172 </var>
1173
1174 <var>
1175 <name>ND_ATTEMPT</name>
1176 <idx>195</idx>
1177 <comment><![CDATA[Force ND in ACQ (1), unless ND_OK is FALSE /RO]]></comment>
1178 </var>
1179
1180 <var>
1181 <name>ND_CMDS</name>
1182 <idx>196</idx>
1183 <comment><![CDATA[Force ND in ACQ, unless ND_OK is FALSE /RO]]></comment>
1184 </var>
1185
1186 <var>
1187 <name>SCM_TM_DO_CHECK_VALUES_FREQ</name>
1188 <idx>197</idx>
1189 <comment><![CDATA[Do a Check on TM values every XXX Number of cyc acq done /RO]]></comment>
1190 </var>
1191
1192 <var>
1193 <name>POWER_KHB</name>
1194 <idx>198</idx>
1195 <comment><![CDATA[Select KHB board 0==>HOT else COLD]]></comment>
1196 </var>
1197
1198 <var>
1199 <name>PSB_TRB_S9004_ALL_ON_DELAY</name>
1200 <idx>199</idx>
1201 <comment><![CDATA[milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on) /RO]]></comment>
1202 </var>
1203
1204 <var>
1205 <name>PSB_TRB_BIAS_WAIT</name>
1206 <idx>200</idx>
1207 <comment><![CDATA[wait between bias TRB switch on/off /RO]]></comment>
1208 </var>
1209
1210 <var>
1211 <name>PSB_CALOFE_DELAY</name>
1212 <idx>201</idx>
1213 <comment><![CDATA[Delay before power on CALO 5.7 /RO]]></comment>
1214 </var>
1215
1216 <var>
1217 <name>HV_OK</name>
1218 <idx>202</idx>
1219 <comment><![CDATA[call HV settings after TRB setting at start-up /RO]]></comment>
1220 </var>
1221
1222 <var>
1223 <name>TSB_T_OK</name>
1224 <idx>203</idx>
1225 <comment><![CDATA[Do TSB Temperature check /RO]]></comment>
1226 </var>
1227
1228 <var>
1229 <name>TSB_B_OK</name>
1230 <idx>204</idx>
1231 <comment><![CDATA[Do B-field TSB check /RO]]></comment>
1232 </var>
1233
1234 <var>
1235 <name>ALLPAGEAVAIL_ATTEMPT</name>
1236 <idx>205</idx>
1237 <comment><![CDATA[ATTEMP TO ALLPAGE AVAILABLE]]></comment>
1238 </var>
1239
1240 </varxml>
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