/[PAMELA software]/quicklook/dataToXML/Data/compilationInfo/PRH_ParamHandler_INFN_auto.mm.xml
ViewVC logotype

Contents of /quicklook/dataToXML/Data/compilationInfo/PRH_ParamHandler_INFN_auto.mm.xml

Parent Directory Parent Directory | Revision Log Revision Log


Revision 1.1.1.1 - (show annotations) (download) (as text) (vendor branch)
Tue Apr 25 09:00:20 2006 UTC (18 years, 7 months ago) by kusanagi
Branch: MAIN
CVS Tags: dataToXML1_02/01, dataToXML1_02/00, dataToXML1_03/00, dataToXML1_03/01, dataToXML1_00/00, firstRelease, dataToXML1_01/00, dataToXML1_03_02, HEAD
Changes since 1.1: +0 -0 lines
File MIME type: text/xml
These program extract in an XML format the info contained into the ROOT files generated by YODA from the PAMELA data. To visualize the XML files in a more human readable format a collection of XSL files are given in the Data subfolder.

1
2 <rootparams>
3
4 <arr>
5 <name>LOG_MASK</name>
6 <n>113</n>
7 <idx>0</idx>
8 <comment><![CDATA[log level mask for each module]]></comment>
9 </arr>
10
11 <var>
12 <name>LU_WRITE_ON_UART</name>
13 <idx>0</idx>
14 <comment><![CDATA[enable/disable the UART writing]]></comment>
15 </var>
16
17 <var>
18 <name>KHB_ALARM_REG_LOW_LEVEL_MASK</name>
19 <idx>1</idx>
20 <comment><![CDATA[mask of KHB Alarm register to be low-level masked]]></comment>
21 </var>
22
23 <var>
24 <name>KHB_STATUS_REG_LOW_LEVEL_MASK</name>
25 <idx>2</idx>
26 <comment><![CDATA[mask of KHB status register to be low-level masked]]></comment>
27 </var>
28
29 <var>
30 <name>N_BOOT</name>
31 <idx>3</idx>
32 <comment><![CDATA[Boot Counter]]></comment>
33 </var>
34
35 <var>
36 <name>THERMISTORS_CHECK</name>
37 <idx>4</idx>
38 <comment><![CDATA[Check if thermistor are going to be checked]]></comment>
39 </var>
40
41 <var>
42 <name>THERM_MASK</name>
43 <idx>5</idx>
44 <comment><![CDATA[Thermistors mask]]></comment>
45 </var>
46
47 <var>
48 <name>THERM_VAL</name>
49 <idx>6</idx>
50 <comment><![CDATA[Maximum number of wrong themperature measures]]></comment>
51 </var>
52
53 <arr>
54 <name>THERM_LOW</name>
55 <n>16</n>
56 <idx>1</idx>
57 <comment><![CDATA[Thermistor low limit]]></comment>
58 </arr>
59
60 <arr>
61 <name>THERM_HIGH</name>
62 <n>16</n>
63 <idx>2</idx>
64 <comment><![CDATA[Thermistor high limit]]></comment>
65 </arr>
66
67 <var>
68 <name>IPM_VOLTAGES_CHECK</name>
69 <idx>7</idx>
70 <comment><![CDATA[Check if ipm are going to be checked]]></comment>
71 </var>
72
73 <var>
74 <name>KHB_IDAQ_CHECK</name>
75 <idx>8</idx>
76 <comment><![CDATA[Check if khb&idaq are going to be checked]]></comment>
77 </var>
78
79 <var>
80 <name>NTRIG</name>
81 <idx>9</idx>
82 <comment><![CDATA[Trig Counter]]></comment>
83 </var>
84
85 <tab>
86 <name>CONF</name>
87 <rows>5</rows>
88 <cols>6</cols>
89 <idx>0</idx>
90 <comment><![CDATA[active sensors - first dimention is the number of the incrementing configuration. second dimention is the number of FE]]></comment>
91 </tab>
92
93 <var>
94 <name>CONF_SEL</name>
95 <idx>10</idx>
96 <comment><![CDATA[active sensor selector]]></comment>
97 </var>
98
99 <var>
100 <name>NOFF</name>
101 <idx>11</idx>
102 <comment><![CDATA[On Off Counter]]></comment>
103 </var>
104
105 <var>
106 <name>CONFOK</name>
107 <idx>12</idx>
108 <comment><![CDATA[whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON]]></comment>
109 </var>
110
111 <var>
112 <name>OFF</name>
113 <idx>13</idx>
114 <comment><![CDATA[Trig Counter]]></comment>
115 </var>
116
117 <var>
118 <name>NFAILED_POWER_ON</name>
119 <idx>14</idx>
120 <comment><![CDATA[max number of failed power_on, before STOP&WAIT]]></comment>
121 </var>
122
123 <var>
124 <name>NRES</name>
125 <idx>15</idx>
126 <comment><![CDATA[Max number of reset]]></comment>
127 </var>
128
129 <var>
130 <name>RES</name>
131 <idx>16</idx>
132 <comment><![CDATA[current number of reset]]></comment>
133 </var>
134
135 <var>
136 <name>AUTO_RM_MODE</name>
137 <idx>17</idx>
138 <comment><![CDATA[define the Automatic Mode]]></comment>
139 </var>
140
141 <var>
142 <name>AUTO_SCM_MODE</name>
143 <idx>18</idx>
144 <comment><![CDATA[define the Automatic Mode for scm]]></comment>
145 </var>
146
147 <var>
148 <name>MASK_ACQ_ALARM</name>
149 <idx>19</idx>
150 <comment><![CDATA[Alarm mask ]]></comment>
151 </var>
152
153 <var>
154 <name>GOM_DURING_ALARM</name>
155 <idx>20</idx>
156 <comment><![CDATA[General operation mode during alarm revelation]]></comment>
157 </var>
158
159 <var>
160 <name>TRIG</name>
161 <idx>21</idx>
162 <comment><![CDATA[Trigger counter]]></comment>
163 </var>
164
165 <var>
166 <name>PAMELA_ON</name>
167 <idx>22</idx>
168 <comment><![CDATA[Pamela status]]></comment>
169 </var>
170
171 <var>
172 <name>N_CALIB</name>
173 <idx>23</idx>
174 <comment><![CDATA[Number of calibratrion since start up]]></comment>
175 </var>
176
177 <var>
178 <name>AC_1_ON</name>
179 <idx>24</idx>
180 <comment><![CDATA[AC on]]></comment>
181 </var>
182
183 <var>
184 <name>AC_2_ON</name>
185 <idx>25</idx>
186 <comment><![CDATA[AC on]]></comment>
187 </var>
188
189 <var>
190 <name>POWER_MODE</name>
191 <idx>26</idx>
192 <comment><![CDATA[Power mode]]></comment>
193 </var>
194
195 <var>
196 <name>VERBOSE_DEBUG</name>
197 <idx>27</idx>
198 <comment><![CDATA[Verbose Debug mode]]></comment>
199 </var>
200
201 <var>
202 <name>EXP64_MODE</name>
203 <idx>28</idx>
204 <comment><![CDATA[if TRUE, working in exp 64 mode]]></comment>
205 </var>
206
207 <var>
208 <name>EXP64_MODE_DELAY</name>
209 <idx>29</idx>
210 <comment><![CDATA[delay for exp 64 mode acquiring...]]></comment>
211 </var>
212
213 <var>
214 <name>PM_STOP_RUNMANAGER_TIMEOUT</name>
215 <idx>30</idx>
216 <comment><![CDATA[the maximult time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager]]></comment>
217 </var>
218
219 <var>
220 <name>PM_STOP_RUNMANAGER_TIMES_RETRY</name>
221 <idx>31</idx>
222 <comment><![CDATA[The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle.]]></comment>
223 </var>
224
225 <var>
226 <name>PM_N_ORBIT_CALIB</name>
227 <idx>32</idx>
228 <comment><![CDATA[Number of orbits per calibration]]></comment>
229 </var>
230
231 <arr>
232 <name>WS_1_SETTING</name>
233 <n>5</n>
234 <idx>3</idx>
235 <comment><![CDATA[Define the Working Schedule #1 values in ms]]></comment>
236 </arr>
237
238 <var>
239 <name>WS_TIME_ORBIT</name>
240 <idx>33</idx>
241 <comment><![CDATA[The duration in millisencond of the full orbit in ms]]></comment>
242 </var>
243
244 <var>
245 <name>WS_FAVOURITE_WS</name>
246 <idx>34</idx>
247 <comment><![CDATA[The Favourite Pamela Working Schedule]]></comment>
248 </var>
249
250 <var>
251 <name>MH_SINTOKTIMEOUT</name>
252 <idx>35</idx>
253 <comment><![CDATA[Timeout for the event receive SINT_OK]]></comment>
254 </var>
255
256 <var>
257 <name>RM_RUNTIMEOUT</name>
258 <idx>40</idx>
259 <comment><![CDATA[The timeout for an event to come (software timeout)]]></comment>
260 </var>
261
262 <var>
263 <name>RM_RUNHEADER_TIMEOUT</name>
264 <idx>41</idx>
265 <comment><![CDATA[The timeout for writing a Run Header pkt]]></comment>
266 </var>
267
268 <var>
269 <name>RM_RUNTRAILER_TIMEOUT</name>
270 <idx>42</idx>
271 <comment><![CDATA[The timeout for writing a Run Trailer pkt]]></comment>
272 </var>
273
274 <var>
275 <name>RM_STOP_FULL_ACQ_SECS</name>
276 <idx>43</idx>
277 <comment><![CDATA[number of seconds after the starting of the first run after an ascending node must stop the full acquisition]]></comment>
278 </var>
279
280 <var>
281 <name>RM_SUSPEND_IN_RUN_LOOP</name>
282 <idx>44</idx>
283 <comment><![CDATA[Suspend time in the ACQ-Run Loop before get a new event]]></comment>
284 </var>
285
286 <var>
287 <name>RM_ETO_COUNTER_IN_RUN_LOOP</name>
288 <idx>45</idx>
289 <comment><![CDATA[Number or Acq attempts in the run loob in case of HW/SW event time out]]></comment>
290 </var>
291
292 <var>
293 <name>RM_N_TRIES_PREPARE_PAGE</name>
294 <idx>46</idx>
295 <comment><![CDATA[Number of attempts to try to exec the prepar page before exit from the run procedure with an error]]></comment>
296 </var>
297
298 <var>
299 <name>RM_TRIES_PREPARE_PAGE_SLEEP</name>
300 <idx>47</idx>
301 <comment><![CDATA[Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure]]></comment>
302 </var>
303
304 <var>
305 <name>RM_WS3_TIMER_FIRE_AFTER</name>
306 <idx>48</idx>
307 <comment><![CDATA[Time to wait for the WS3 timer to fire]]></comment>
308 </var>
309
310 <var>
311 <name>RM_RATE_METER_S1_TRH</name>
312 <idx>49</idx>
313 <comment><![CDATA[Rate meter s1 s1 register TRH]]></comment>
314 </var>
315
316 <var>
317 <name>RM_TIME_MAX_RUN</name>
318 <idx>50</idx>
319 <comment><![CDATA[Max duration for an ordinary Run in milliseconds]]></comment>
320 </var>
321
322 <var>
323 <name>RM_TIME_SPECIAL_RUN</name>
324 <idx>51</idx>
325 <comment><![CDATA[duration for the special run in milliseconds]]></comment>
326 </var>
327
328 <var>
329 <name>RM_ACQCHECK_PERIOD</name>
330 <idx>52</idx>
331 <comment><![CDATA[period of acquisition check in milliseconds]]></comment>
332 </var>
333
334 <var>
335 <name>RM_FLUSH_TIMEOUT</name>
336 <idx>53</idx>
337 <comment><![CDATA[timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT]]></comment>
338 </var>
339
340 <var>
341 <name>RM_NO_FLUSH_PARAM_DUMP</name>
342 <idx>54</idx>
343 <comment><![CDATA[Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never.]]></comment>
344 </var>
345
346 <var>
347 <name>RM_DUMP_ALL_PARAMS</name>
348 <idx>55</idx>
349 <comment><![CDATA[dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs]]></comment>
350 </var>
351
352 <var>
353 <name>RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ</name>
354 <idx>56</idx>
355 <comment><![CDATA[number of release busy inserted in the ACQ command queue in After_Calib mode]]></comment>
356 </var>
357
358 <arr>
359 <name>PWR_IPM_CONF</name>
360 <n>6</n>
361 <idx>4</idx>
362 <comment><![CDATA[IMP desired configuration for initial poweron 6 bitmask]]></comment>
363 </arr>
364
365 <var>
366 <name>PWR_WAIT_BEFORE_SENDTC</name>
367 <idx>57</idx>
368 <comment><![CDATA[time to wait before send 2 successive HL]]></comment>
369 </var>
370
371 <var>
372 <name>PWR_TRB_READ_ATTEMPTS</name>
373 <idx>58</idx>
374 <comment><![CDATA[number of attempts to sent a command to the TRB before a timeout]]></comment>
375 </var>
376
377 <var>
378 <name>PWR_KHB_INITBOARD_TWICE_DELAY</name>
379 <idx>59</idx>
380 <comment><![CDATA[milliseconds to wait between two KHB Init Board in PWR_DcdcON]]></comment>
381 </var>
382
383 <var>
384 <name>PWR_IPM_WAIT_OK_N_ATTEMPT</name>
385 <idx>60</idx>
386 <comment><![CDATA[attempts of ipm check ok at power on]]></comment>
387 </var>
388
389 <var>
390 <name>PWR_IPM_WAIT_OK_DELAY_ATTEMPT</name>
391 <idx>61</idx>
392 <comment><![CDATA[attempts of ipm check ok at power on]]></comment>
393 </var>
394
395 <var>
396 <name>PWR_VOLTAGE_N_ATTEMPT</name>
397 <idx>62</idx>
398 <comment><![CDATA[no of millisecond to wain in VOLTAGE IPM procedure]]></comment>
399 </var>
400
401 <var>
402 <name>PWR_VOLTAGE_DELAY_ATTEMPT</name>
403 <idx>63</idx>
404 <comment><![CDATA[no of millisecond to wain in VOLTAGE IPM procedure]]></comment>
405 </var>
406
407 <arr>
408 <name>PWR_VOLTAGE_IPM_CONF</name>
409 <n>6</n>
410 <idx>5</idx>
411 <comment><![CDATA[ADC desider configuration for inital poweron - OBSOLETE ]]></comment>
412 </arr>
413
414 <arr>
415 <name>PWR_VOLTAGE_IPM_RANGE_ON_MAX</name>
416 <n>6</n>
417 <idx>6</idx>
418 <comment><![CDATA[ADC min voltage values if ON]]></comment>
419 </arr>
420
421 <arr>
422 <name>PWR_VOLTAGE_IPM_RANGE_ON_MIN</name>
423 <n>6</n>
424 <idx>7</idx>
425 <comment><![CDATA[ADC min voltage values if ON]]></comment>
426 </arr>
427
428 <arr>
429 <name>PWR_VOLTAGE_IPM_RANGE_OFF_MAX</name>
430 <n>6</n>
431 <idx>8</idx>
432 <comment><![CDATA[ADC min voltage values if OFF]]></comment>
433 </arr>
434
435 <arr>
436 <name>PWR_VOLTAGE_IPM_RANGE_OFF_MIN</name>
437 <n>6</n>
438 <idx>9</idx>
439 <comment><![CDATA[ADC min voltage values if OFF]]></comment>
440 </arr>
441
442 <var>
443 <name>PWR_TRB1_SET</name>
444 <idx>64</idx>
445 <comment><![CDATA[trb 1 setting]]></comment>
446 </var>
447
448 <var>
449 <name>PWR_TRB2_SET</name>
450 <idx>65</idx>
451 <comment><![CDATA[trb 2 setting]]></comment>
452 </var>
453
454 <var>
455 <name>PWR_TRB_SET_DELAY</name>
456 <idx>66</idx>
457 <comment><![CDATA[delay after trb set cmd]]></comment>
458 </var>
459
460 <var>
461 <name>PWR_TRB_READ_DELAY</name>
462 <idx>67</idx>
463 <comment><![CDATA[delay after trb read cmd]]></comment>
464 </var>
465
466 <tab>
467 <name>PWR_IPM_ACTION</name>
468 <rows>3</rows>
469 <cols>64</cols>
470 <idx>1</idx>
471 <comment><![CDATA[Main Table for actions to be done in IPM Check procedure]]></comment>
472 </tab>
473
474 <var>
475 <name>HB_N_ATTEMPT_WRITE2PIF</name>
476 <idx>68</idx>
477 <comment><![CDATA[Number of attempt to write on PIF after return an error]]></comment>
478 </var>
479
480 <var>
481 <name>HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF</name>
482 <idx>69</idx>
483 <comment><![CDATA[Waint time after a failed attempt on PIF write]]></comment>
484 </var>
485
486 <var>
487 <name>HB_WRITE2PIF_TIMEOUT</name>
488 <idx>70</idx>
489 <comment><![CDATA[timeout time time to wait a sketchboard free in Write2PIF]]></comment>
490 </var>
491
492 <var>
493 <name>HB_ALMOST_FULL</name>
494 <idx>71</idx>
495 <comment><![CDATA[says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage.]]></comment>
496 </var>
497
498 <arr>
499 <name>TM_FILTER_OPERATION</name>
500 <n>78</n>
501 <idx>10</idx>
502 <comment><![CDATA[low level telemetry filter operation: 0->nooperation 1->set value 2->ORed mask 3->ANDed mask]]></comment>
503 </arr>
504
505 <arr>
506 <name>TM_FILTER_VALUE</name>
507 <n>78</n>
508 <idx>11</idx>
509 <comment><![CDATA[low level telemetry filted values]]></comment>
510 </arr>
511
512 <var>
513 <name>TM_VRL_SUSPEND_HCL</name>
514 <idx>72</idx>
515 <comment><![CDATA[wait time between two HCL commands for the VRL]]></comment>
516 </var>
517
518 <var>
519 <name>TM_VRL_SUSPEND_BEFORE_START</name>
520 <idx>73</idx>
521 <comment><![CDATA[wait time before start VRL]]></comment>
522 </var>
523
524 <var>
525 <name>DAQ_EVENT_RECEIVE_TIMEOUT</name>
526 <idx>74</idx>
527 <comment><![CDATA[PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply]]></comment>
528 </var>
529
530 <var>
531 <name>DAQ_WAITFREECMDIF_N</name>
532 <idx>75</idx>
533 <comment><![CDATA[Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched]]></comment>
534 </var>
535
536 <var>
537 <name>BUF_LEN_IDAQ_DSP_SET</name>
538 <idx>76</idx>
539 <comment><![CDATA[IDAQ DSP SET]]></comment>
540 </var>
541
542 <arr>
543 <name>BUF_IDAQ_DSP_SET</name>
544 <n>2</n>
545 <idx>12</idx>
546 <comment><![CDATA[IDAQ DSP SET]]></comment>
547 </arr>
548
549 <var>
550 <name>TRB_OK</name>
551 <idx>77</idx>
552 <comment><![CDATA[Use ON_OFF tracker in ACQ]]></comment>
553 </var>
554
555 <var>
556 <name>TRIGGER_MODE_A</name>
557 <idx>78</idx>
558 <comment><![CDATA[Trigger type for acq mode A]]></comment>
559 </var>
560
561 <var>
562 <name>TRIGGER_MODE_B</name>
563 <idx>79</idx>
564 <comment><![CDATA[Trigger type for acq mode B]]></comment>
565 </var>
566
567 <var>
568 <name>TRIGGER_BUSY_CONTROL</name>
569 <idx>80</idx>
570 <comment><![CDATA[Select the check mask of the busy alaarm]]></comment>
571 </var>
572
573 <var>
574 <name>TB_LINK</name>
575 <idx>81</idx>
576 <comment><![CDATA[Trigger Board to use 1 or 2]]></comment>
577 </var>
578
579 <var>
580 <name>BUF_LEN_TB_SET_ALARM_MASK</name>
581 <idx>82</idx>
582 <comment><![CDATA[TRG queue]]></comment>
583 </var>
584
585 <arr>
586 <name>BUF_TB_SET_ALARM_MASK</name>
587 <n>2</n>
588 <idx>13</idx>
589 <comment><![CDATA[TRG queue]]></comment>
590 </arr>
591
592 <var>
593 <name>BUF_LEN_TB_SET_PMT_MASK</name>
594 <idx>83</idx>
595 <comment><![CDATA[TRG queue]]></comment>
596 </var>
597
598 <arr>
599 <name>BUF_TB_SET_PMT_MASK</name>
600 <n>3</n>
601 <idx>14</idx>
602 <comment><![CDATA[TRG queue]]></comment>
603 </arr>
604
605 <var>
606 <name>BUF_LEN_TB_SET_S4_CAL_MASK</name>
607 <idx>84</idx>
608 <comment><![CDATA[TRG queue]]></comment>
609 </var>
610
611 <arr>
612 <name>BUF_TB_SET_S4_CAL_MASK</name>
613 <n>2</n>
614 <idx>15</idx>
615 <comment><![CDATA[TRG queue]]></comment>
616 </arr>
617
618 <var>
619 <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT</name>
620 <idx>85</idx>
621 <comment><![CDATA[ ]]></comment>
622 </var>
623
624 <arr>
625 <name>BUF_TB_SET_BUSY_MASK_IDAQ_HOT</name>
626 <n>5</n>
627 <idx>16</idx>
628 <comment><![CDATA[ ]]></comment>
629 </arr>
630
631 <var>
632 <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD</name>
633 <idx>86</idx>
634 <comment><![CDATA[ ]]></comment>
635 </var>
636
637 <arr>
638 <name>BUF_TB_SET_BUSY_MASK_IDAQ_COLD</name>
639 <n>5</n>
640 <idx>17</idx>
641 <comment><![CDATA[ ]]></comment>
642 </arr>
643
644 <var>
645 <name>TRK_OK</name>
646 <idx>87</idx>
647 <comment><![CDATA[Use ON_OFF tracker in ACQ]]></comment>
648 </var>
649
650 <tab>
651 <name>TRK_DSP_OK</name>
652 <rows>2</rows>
653 <cols>6</cols>
654 <idx>2</idx>
655 <comment><![CDATA[Tracker dsp ON_OFF in ACQ]]></comment>
656 </tab>
657
658 <var>
659 <name>TRK_CALIB_MODE</name>
660 <idx>88</idx>
661 <comment><![CDATA[Tracker calibration mode]]></comment>
662 </var>
663
664 <var>
665 <name>TRK_TIME_SHORT</name>
666 <idx>89</idx>
667 <comment><![CDATA[Tracker wait loop for 128 loop]]></comment>
668 </var>
669
670 <var>
671 <name>TRK_TIME_LONG</name>
672 <idx>90</idx>
673 <comment><![CDATA[Tracker wait loop for 8 loop]]></comment>
674 </var>
675
676 <tab>
677 <name>TRK_DSP_MASK</name>
678 <rows>2</rows>
679 <cols>6</cols>
680 <idx>3</idx>
681 <comment><![CDATA[Traker dsp mask]]></comment>
682 </tab>
683
684 <arr>
685 <name>TRK_LOAD_PRG</name>
686 <n>2</n>
687 <idx>18</idx>
688 <comment><![CDATA[The way the DSP program is loaded]]></comment>
689 </arr>
690
691 <var>
692 <name>TRK_CALIB_INIT</name>
693 <idx>91</idx>
694 <comment><![CDATA[modality of calibration]]></comment>
695 </var>
696
697 <var>
698 <name>TRK_NLOOP</name>
699 <idx>92</idx>
700 <comment><![CDATA[macro loop number]]></comment>
701 </var>
702
703 <var>
704 <name>MMSU_DMA_DELAY</name>
705 <idx>93</idx>
706 <comment><![CDATA[MMSU DELAY]]></comment>
707 </var>
708
709 <tab>
710 <name>TRK_PED_MIN_0</name>
711 <rows>3</rows>
712 <cols>6</cols>
713 <idx>4</idx>
714 <comment><![CDATA[Tracker 0 ped min value]]></comment>
715 </tab>
716
717 <tab>
718 <name>TRK_PED_MIN_1</name>
719 <rows>3</rows>
720 <cols>6</cols>
721 <idx>5</idx>
722 <comment><![CDATA[Tracker 1 ped min value]]></comment>
723 </tab>
724
725 <tab>
726 <name>TRK_PED_MAX_0</name>
727 <rows>3</rows>
728 <cols>6</cols>
729 <idx>6</idx>
730 <comment><![CDATA[Tracker 0 ped max value]]></comment>
731 </tab>
732
733 <tab>
734 <name>TRK_PED_MAX_1</name>
735 <rows>3</rows>
736 <cols>6</cols>
737 <idx>7</idx>
738 <comment><![CDATA[Tracker 1 ped max value]]></comment>
739 </tab>
740
741 <tab>
742 <name>TRK_SIG_MIN_0</name>
743 <rows>3</rows>
744 <cols>6</cols>
745 <idx>8</idx>
746 <comment><![CDATA[Tracker 0 sig min value]]></comment>
747 </tab>
748
749 <tab>
750 <name>TRK_SIG_MIN_1</name>
751 <rows>3</rows>
752 <cols>6</cols>
753 <idx>9</idx>
754 <comment><![CDATA[Tracker 1 sig min value]]></comment>
755 </tab>
756
757 <tab>
758 <name>TRK_SIG_MAX_0</name>
759 <rows>3</rows>
760 <cols>6</cols>
761 <idx>10</idx>
762 <comment><![CDATA[Tracker 0 sig min value]]></comment>
763 </tab>
764
765 <tab>
766 <name>TRK_SIG_MAX_1</name>
767 <rows>3</rows>
768 <cols>6</cols>
769 <idx>11</idx>
770 <comment><![CDATA[Tracker 1 sig min value]]></comment>
771 </tab>
772
773 <tab>
774 <name>TRK_BAD_MAX_0</name>
775 <rows>3</rows>
776 <cols>6</cols>
777 <idx>12</idx>
778 <comment><![CDATA[Tracker 0 bad max value]]></comment>
779 </tab>
780
781 <tab>
782 <name>TRK_BAD_MAX_1</name>
783 <rows>3</rows>
784 <cols>6</cols>
785 <idx>13</idx>
786 <comment><![CDATA[Tracker 1 bad max value]]></comment>
787 </tab>
788
789 <var>
790 <name>BUF_LEN_TRK_TRAILER_PRG_0</name>
791 <idx>96</idx>
792 <comment><![CDATA[TRK DSP Program Trailer for DSP 0]]></comment>
793 </var>
794
795 <arr>
796 <name>BUF_TRK_TRAILER_PRG_0</name>
797 <n>3</n>
798 <idx>20</idx>
799 <comment><![CDATA[TRK DSP Program Trailer for DSP 0]]></comment>
800 </arr>
801
802 <var>
803 <name>BUF_LEN_TRK_TRAILER_PRG_1</name>
804 <idx>97</idx>
805 <comment><![CDATA[TRK DSP Program Trailer for DSP 1]]></comment>
806 </var>
807
808 <arr>
809 <name>BUF_TRK_TRAILER_PRG_1</name>
810 <n>3</n>
811 <idx>21</idx>
812 <comment><![CDATA[TRK DSP Program Trailer for DSP 1]]></comment>
813 </arr>
814
815 <var>
816 <name>BUF_LEN_TRK_TRAILER_PRG_2</name>
817 <idx>98</idx>
818 <comment><![CDATA[TRK DSP Program Trailer for DSP 2]]></comment>
819 </var>
820
821 <arr>
822 <name>BUF_TRK_TRAILER_PRG_2</name>
823 <n>3</n>
824 <idx>22</idx>
825 <comment><![CDATA[TRK DSP Program Trailer for DSP 2]]></comment>
826 </arr>
827
828 <var>
829 <name>BUF_LEN_TRK_TRAILER_PRG_3</name>
830 <idx>99</idx>
831 <comment><![CDATA[TRK DSP Program Trailer for DSP 3]]></comment>
832 </var>
833
834 <arr>
835 <name>BUF_TRK_TRAILER_PRG_3</name>
836 <n>3</n>
837 <idx>23</idx>
838 <comment><![CDATA[TRK DSP Program Trailer for DSP 3]]></comment>
839 </arr>
840
841 <var>
842 <name>BUF_LEN_TRK_TRAILER_PRG_4</name>
843 <idx>100</idx>
844 <comment><![CDATA[TRK DSP Program Trailer for DSP 4]]></comment>
845 </var>
846
847 <arr>
848 <name>BUF_TRK_TRAILER_PRG_4</name>
849 <n>3</n>
850 <idx>24</idx>
851 <comment><![CDATA[TRK DSP Program Trailer for DSP 4]]></comment>
852 </arr>
853
854 <var>
855 <name>BUF_LEN_TRK_TRAILER_PRG_5</name>
856 <idx>101</idx>
857 <comment><![CDATA[TRK DSP Program Trailer for DSP 5]]></comment>
858 </var>
859
860 <arr>
861 <name>BUF_TRK_TRAILER_PRG_5</name>
862 <n>3</n>
863 <idx>25</idx>
864 <comment><![CDATA[TRK DSP Program Trailer for DSP 5]]></comment>
865 </arr>
866
867 <var>
868 <name>BUF_LEN_TRK_NUMBER_DSP_1_0</name>
869 <idx>102</idx>
870 <comment><![CDATA[TRK command queue]]></comment>
871 </var>
872
873 <arr>
874 <name>BUF_TRK_NUMBER_DSP_1_0</name>
875 <n>8</n>
876 <idx>26</idx>
877 <comment><![CDATA[TRK command queue]]></comment>
878 </arr>
879
880 <var>
881 <name>BUF_LEN_TRK_NUMBER_DSP_1_1</name>
882 <idx>103</idx>
883 <comment><![CDATA[TRK command queue]]></comment>
884 </var>
885
886 <arr>
887 <name>BUF_TRK_NUMBER_DSP_1_1</name>
888 <n>8</n>
889 <idx>27</idx>
890 <comment><![CDATA[TRK command queue]]></comment>
891 </arr>
892
893 <var>
894 <name>BUF_LEN_TRK_NUMBER_DSP_1_2</name>
895 <idx>104</idx>
896 <comment><![CDATA[TRK command queue]]></comment>
897 </var>
898
899 <arr>
900 <name>BUF_TRK_NUMBER_DSP_1_2</name>
901 <n>8</n>
902 <idx>28</idx>
903 <comment><![CDATA[TRK command queue]]></comment>
904 </arr>
905
906 <var>
907 <name>BUF_LEN_TRK_NUMBER_DSP_1_3</name>
908 <idx>105</idx>
909 <comment><![CDATA[TRK command queue]]></comment>
910 </var>
911
912 <arr>
913 <name>BUF_TRK_NUMBER_DSP_1_3</name>
914 <n>8</n>
915 <idx>29</idx>
916 <comment><![CDATA[TRK command queue]]></comment>
917 </arr>
918
919 <var>
920 <name>BUF_LEN_TRK_NUMBER_DSP_1_4</name>
921 <idx>106</idx>
922 <comment><![CDATA[TRK command queue]]></comment>
923 </var>
924
925 <arr>
926 <name>BUF_TRK_NUMBER_DSP_1_4</name>
927 <n>8</n>
928 <idx>30</idx>
929 <comment><![CDATA[TRK command queue]]></comment>
930 </arr>
931
932 <var>
933 <name>BUF_LEN_TRK_NUMBER_DSP_1_5</name>
934 <idx>107</idx>
935 <comment><![CDATA[TRK command queue]]></comment>
936 </var>
937
938 <arr>
939 <name>BUF_TRK_NUMBER_DSP_1_5</name>
940 <n>8</n>
941 <idx>31</idx>
942 <comment><![CDATA[TRK command queue]]></comment>
943 </arr>
944
945 <var>
946 <name>BUF_LEN_TRK_NUMBER_DSP_2_0</name>
947 <idx>108</idx>
948 <comment><![CDATA[TRK command queue]]></comment>
949 </var>
950
951 <arr>
952 <name>BUF_TRK_NUMBER_DSP_2_0</name>
953 <n>8</n>
954 <idx>32</idx>
955 <comment><![CDATA[TRK command queue]]></comment>
956 </arr>
957
958 <var>
959 <name>BUF_LEN_TRK_NUMBER_DSP_2_1</name>
960 <idx>109</idx>
961 <comment><![CDATA[TRK command queue]]></comment>
962 </var>
963
964 <arr>
965 <name>BUF_TRK_NUMBER_DSP_2_1</name>
966 <n>8</n>
967 <idx>33</idx>
968 <comment><![CDATA[TRK command queue]]></comment>
969 </arr>
970
971 <var>
972 <name>BUF_LEN_TRK_NUMBER_DSP_2_2</name>
973 <idx>110</idx>
974 <comment><![CDATA[TRK command queue]]></comment>
975 </var>
976
977 <arr>
978 <name>BUF_TRK_NUMBER_DSP_2_2</name>
979 <n>8</n>
980 <idx>34</idx>
981 <comment><![CDATA[TRK command queue]]></comment>
982 </arr>
983
984 <var>
985 <name>BUF_LEN_TRK_NUMBER_DSP_2_3</name>
986 <idx>111</idx>
987 <comment><![CDATA[TRK command queue]]></comment>
988 </var>
989
990 <arr>
991 <name>BUF_TRK_NUMBER_DSP_2_3</name>
992 <n>8</n>
993 <idx>35</idx>
994 <comment><![CDATA[TRK command queue]]></comment>
995 </arr>
996
997 <var>
998 <name>BUF_LEN_TRK_NUMBER_DSP_2_4</name>
999 <idx>112</idx>
1000 <comment><![CDATA[TRK command queue]]></comment>
1001 </var>
1002
1003 <arr>
1004 <name>BUF_TRK_NUMBER_DSP_2_4</name>
1005 <n>8</n>
1006 <idx>36</idx>
1007 <comment><![CDATA[TRK command queue]]></comment>
1008 </arr>
1009
1010 <var>
1011 <name>BUF_LEN_TRK_NUMBER_DSP_2_5</name>
1012 <idx>113</idx>
1013 <comment><![CDATA[TRK command queue]]></comment>
1014 </var>
1015
1016 <arr>
1017 <name>BUF_TRK_NUMBER_DSP_2_5</name>
1018 <n>8</n>
1019 <idx>37</idx>
1020 <comment><![CDATA[TRK command queue]]></comment>
1021 </arr>
1022
1023 <var>
1024 <name>BUF_LEN_TRK_OPMODE_COMP_0</name>
1025 <idx>114</idx>
1026 <comment><![CDATA[TRK command queue]]></comment>
1027 </var>
1028
1029 <arr>
1030 <name>BUF_TRK_OPMODE_COMP_0</name>
1031 <n>8</n>
1032 <idx>38</idx>
1033 <comment><![CDATA[TRK command queue]]></comment>
1034 </arr>
1035
1036 <var>
1037 <name>BUF_LEN_TRK_OPMODE_SPEC_0</name>
1038 <idx>115</idx>
1039 <comment><![CDATA[TRK command queue]]></comment>
1040 </var>
1041
1042 <arr>
1043 <name>BUF_TRK_OPMODE_SPEC_0</name>
1044 <n>8</n>
1045 <idx>39</idx>
1046 <comment><![CDATA[TRK command queue]]></comment>
1047 </arr>
1048
1049 <var>
1050 <name>BUF_LEN_TRK_OPMODE_COMP_1</name>
1051 <idx>116</idx>
1052 <comment><![CDATA[TRK command queue]]></comment>
1053 </var>
1054
1055 <arr>
1056 <name>BUF_TRK_OPMODE_COMP_1</name>
1057 <n>8</n>
1058 <idx>40</idx>
1059 <comment><![CDATA[TRK command queue]]></comment>
1060 </arr>
1061
1062 <var>
1063 <name>BUF_LEN_TRK_OPMODE_SPEC_1</name>
1064 <idx>117</idx>
1065 <comment><![CDATA[TRK command queue]]></comment>
1066 </var>
1067
1068 <arr>
1069 <name>BUF_TRK_OPMODE_SPEC_1</name>
1070 <n>8</n>
1071 <idx>41</idx>
1072 <comment><![CDATA[TRK command queue]]></comment>
1073 </arr>
1074
1075 <var>
1076 <name>BUF_LEN_TRK_OPMODE_COMP_2</name>
1077 <idx>118</idx>
1078 <comment><![CDATA[TRK command queue]]></comment>
1079 </var>
1080
1081 <arr>
1082 <name>BUF_TRK_OPMODE_COMP_2</name>
1083 <n>8</n>
1084 <idx>42</idx>
1085 <comment><![CDATA[TRK command queue]]></comment>
1086 </arr>
1087
1088 <var>
1089 <name>BUF_LEN_TRK_OPMODE_SPEC_2</name>
1090 <idx>119</idx>
1091 <comment><![CDATA[TRK command queue]]></comment>
1092 </var>
1093
1094 <arr>
1095 <name>BUF_TRK_OPMODE_SPEC_2</name>
1096 <n>8</n>
1097 <idx>43</idx>
1098 <comment><![CDATA[TRK command queue]]></comment>
1099 </arr>
1100
1101 <var>
1102 <name>BUF_LEN_TRK_OPMODE_COMP_3</name>
1103 <idx>120</idx>
1104 <comment><![CDATA[TRK command queue]]></comment>
1105 </var>
1106
1107 <arr>
1108 <name>BUF_TRK_OPMODE_COMP_3</name>
1109 <n>8</n>
1110 <idx>44</idx>
1111 <comment><![CDATA[TRK command queue]]></comment>
1112 </arr>
1113
1114 <var>
1115 <name>BUF_LEN_TRK_OPMODE_SPEC_3</name>
1116 <idx>121</idx>
1117 <comment><![CDATA[TRK command queue]]></comment>
1118 </var>
1119
1120 <arr>
1121 <name>BUF_TRK_OPMODE_SPEC_3</name>
1122 <n>8</n>
1123 <idx>45</idx>
1124 <comment><![CDATA[TRK command queue]]></comment>
1125 </arr>
1126
1127 <var>
1128 <name>BUF_LEN_TRK_OPMODE_COMP_4</name>
1129 <idx>122</idx>
1130 <comment><![CDATA[TRK command queue]]></comment>
1131 </var>
1132
1133 <arr>
1134 <name>BUF_TRK_OPMODE_COMP_4</name>
1135 <n>8</n>
1136 <idx>46</idx>
1137 <comment><![CDATA[TRK command queue]]></comment>
1138 </arr>
1139
1140 <var>
1141 <name>BUF_LEN_TRK_OPMODE_SPEC_4</name>
1142 <idx>123</idx>
1143 <comment><![CDATA[TRK command queue]]></comment>
1144 </var>
1145
1146 <arr>
1147 <name>BUF_TRK_OPMODE_SPEC_4</name>
1148 <n>8</n>
1149 <idx>47</idx>
1150 <comment><![CDATA[TRK command queue]]></comment>
1151 </arr>
1152
1153 <var>
1154 <name>BUF_LEN_TRK_OPMODE_COMP_5</name>
1155 <idx>124</idx>
1156 <comment><![CDATA[TRK command queue]]></comment>
1157 </var>
1158
1159 <arr>
1160 <name>BUF_TRK_OPMODE_COMP_5</name>
1161 <n>8</n>
1162 <idx>48</idx>
1163 <comment><![CDATA[TRK command queue]]></comment>
1164 </arr>
1165
1166 <var>
1167 <name>BUF_LEN_TRK_OPMODE_SPEC_5</name>
1168 <idx>125</idx>
1169 <comment><![CDATA[TRK command queue]]></comment>
1170 </var>
1171
1172 <arr>
1173 <name>BUF_TRK_OPMODE_SPEC_5</name>
1174 <n>8</n>
1175 <idx>49</idx>
1176 <comment><![CDATA[TRK command queue]]></comment>
1177 </arr>
1178
1179 <var>
1180 <name>S4_OK</name>
1181 <idx>126</idx>
1182 <comment><![CDATA[S4 enable/disable]]></comment>
1183 </var>
1184
1185 <var>
1186 <name>S4_TRH</name>
1187 <idx>127</idx>
1188 <comment><![CDATA[S4 command]]></comment>
1189 </var>
1190
1191 <var>
1192 <name>S4_ATTEND</name>
1193 <idx>128</idx>
1194 <comment><![CDATA[S4 force check]]></comment>
1195 </var>
1196
1197 <var>
1198 <name>S4_WORKING</name>
1199 <idx>129</idx>
1200 <comment><![CDATA[check if S4 is working or not]]></comment>
1201 </var>
1202
1203 <arr>
1204 <name>TRK_SENSOR_MASK_Y</name>
1205 <n>6</n>
1206 <idx>50</idx>
1207 <comment><![CDATA[Mask of the power on/off of the sensor of the Y view.One for each plane ]]></comment>
1208 </arr>
1209
1210 <arr>
1211 <name>TRK_SENSOR_TAB_Y_INDEX</name>
1212 <n>6</n>
1213 <idx>51</idx>
1214 <comment><![CDATA[Default raw value of the power on/off of the sensor of the Y view. Each value is in the range 0-7 (the raw index of TRK_SENSOR_TAB_Y)]]></comment>
1215 </arr>
1216
1217 <arr>
1218 <name>TRK_SENSOR_TAB_X</name>
1219 <n>2</n>
1220 <idx>52</idx>
1221 <comment><![CDATA[Table of the power on/off of thesensor in the X view. One for each view]]></comment>
1222 </arr>
1223
1224 <arr>
1225 <name>TRK_SENSOR_TAB_X_INDEX</name>
1226 <n>6</n>
1227 <idx>53</idx>
1228 <comment><![CDATA[Default raw value of the power on/off of thesensor in the X view. Each value is in the range 0-1 (the raw index of TRK_SENSOR_TAB_X). default all "0"]]></comment>
1229 </arr>
1230
1231 <arr>
1232 <name>TRK_BIAS_TAB</name>
1233 <n>2</n>
1234 <idx>54</idx>
1235 <comment><![CDATA[Table of the power on/off of the bias]]></comment>
1236 </arr>
1237
1238 <var>
1239 <name>TRK_BIAS_TAB_INDEX</name>
1240 <idx>130</idx>
1241 <comment><![CDATA[the default value of the BIAS TAB value to use. can be 0 or 1]]></comment>
1242 </var>
1243
1244 <var>
1245 <name>TRK_BIAS_MASK</name>
1246 <idx>131</idx>
1247 <comment><![CDATA[Mask of the linear regulator of the bias. (18 bit) ]]></comment>
1248 </var>
1249
1250 <arr>
1251 <name>TRK_LOAD_DSP_FROM</name>
1252 <n>24</n>
1253 <idx>55</idx>
1254 <comment><![CDATA[Load DSP From: TRK_LOCAL_FLASH(0),TRK_IDAQ_FLASH(1),TRK_PSCU_EPROM(2)
1255 index:
1256 0-5 Hot,X
1257 6-11 Hot,Y
1258 12-17 Cold,X
1259 18-23 Cold,Y
1260 ]]></comment>
1261 </arr>
1262
1263 <var>
1264 <name>TRK_N_TR_FULL</name>
1265 <idx>132</idx>
1266 <comment><![CDATA[number of events to be acquired in FULL+COMPRESSION mode]]></comment>
1267 </var>
1268
1269 <var>
1270 <name>TRK_N_TR_COMP</name>
1271 <idx>133</idx>
1272 <comment><![CDATA[number of events to be acquired in COMPRESSION mode]]></comment>
1273 </var>
1274
1275 <var>
1276 <name>TRK_MAX_COMPR_LENGTH</name>
1277 <idx>134</idx>
1278 <comment><![CDATA[maximum number of word of an event in compression modo (for alarm generation)]]></comment>
1279 </var>
1280
1281 <var>
1282 <name>TRK_MAX_COMPR_TIME</name>
1283 <idx>135</idx>
1284 <comment><![CDATA[maximum time of an event analysis in compression mode (for alarm generation)]]></comment>
1285 </var>
1286
1287 <var>
1288 <name>TRK_TIME_TR_CAL_SHORT</name>
1289 <idx>136</idx>
1290 <comment><![CDATA[time between two triggers during the block of 128 events in calibration phase]]></comment>
1291 </var>
1292
1293 <var>
1294 <name>TRK_TIME_TR_CAL_LONG</name>
1295 <idx>137</idx>
1296 <comment><![CDATA[time between two block of 128 events in calibration phase]]></comment>
1297 </var>
1298
1299 <var>
1300 <name>TRK_TIME_TR_CAL_READY</name>
1301 <idx>138</idx>
1302 <comment><![CDATA[timing check of DSP ready register during calibration phase]]></comment>
1303 </var>
1304
1305 <var>
1306 <name>TRK_MAX_TR_CAL_READY</name>
1307 <idx>139</idx>
1308 <comment><![CDATA[maximum number of reading of the ready register during the calibration phase]]></comment>
1309 </var>
1310
1311 <var>
1312 <name>TRK_N_TR_CAL_FULL</name>
1313 <idx>140</idx>
1314 <comment><![CDATA[number of tracker calibration before a calibration with full acquisition]]></comment>
1315 </var>
1316
1317 <var>
1318 <name>CAL_UPLOAD_CAL_FE_MASK</name>
1319 <idx>141</idx>
1320 <comment><![CDATA[Defines the working read-out of calorimeter]]></comment>
1321 </var>
1322
1323 <var>
1324 <name>CAL_UPLOAD_CAL_DSP_MASK</name>
1325 <idx>142</idx>
1326 <comment><![CDATA[Defines the workings dsps of calorimeter]]></comment>
1327 </var>
1328
1329 <arr>
1330 <name>CAL_STRIP_SKIP</name>
1331 <n>66</n>
1332 <idx>56</idx>
1333 <comment><![CDATA[Preamplifier vector]]></comment>
1334 </arr>
1335
1336 <var>
1337 <name>CAL_VCAL</name>
1338 <idx>143</idx>
1339 <comment><![CDATA[Variable modified by pulse calibration]]></comment>
1340 </var>
1341
1342 <var>
1343 <name>CAL_CH</name>
1344 <idx>144</idx>
1345 <comment><![CDATA[Variable modified by pulse calibration]]></comment>
1346 </var>
1347
1348 <var>
1349 <name>CAL_TEMP</name>
1350 <idx>145</idx>
1351 <comment><![CDATA[Maximum calorimeter temperature alarms]]></comment>
1352 </var>
1353
1354 <arr>
1355 <name>CAL_COUNT</name>
1356 <n>4</n>
1357 <idx>57</idx>
1358 <comment><![CDATA[defines the calorimeter read out repetitions]]></comment>
1359 </arr>
1360
1361 <var>
1362 <name>CAL_LOOP4</name>
1363 <idx>146</idx>
1364 <comment><![CDATA[defines the calorimeter read out repetitions]]></comment>
1365 </var>
1366
1367 <var>
1368 <name>CAL_OK</name>
1369 <idx>147</idx>
1370 <comment><![CDATA[calo ON_OFF in ACQ]]></comment>
1371 </var>
1372
1373 <var>
1374 <name>CAL_CHECK_FE</name>
1375 <idx>148</idx>
1376 <comment><![CDATA[calo check FE]]></comment>
1377 </var>
1378
1379 <var>
1380 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I211</name>
1381 <idx>149</idx>
1382 <comment><![CDATA[write fpga]]></comment>
1383 </var>
1384
1385 <arr>
1386 <name>BUF_CAL_WRITE_FPGA_REG_I211</name>
1387 <n>2</n>
1388 <idx>58</idx>
1389 <comment><![CDATA[write fpga]]></comment>
1390 </arr>
1391
1392 <var>
1393 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I221</name>
1394 <idx>150</idx>
1395 <comment><![CDATA[write fpga]]></comment>
1396 </var>
1397
1398 <arr>
1399 <name>BUF_CAL_WRITE_FPGA_REG_I221</name>
1400 <n>2</n>
1401 <idx>59</idx>
1402 <comment><![CDATA[write fpga]]></comment>
1403 </arr>
1404
1405 <var>
1406 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I231</name>
1407 <idx>151</idx>
1408 <comment><![CDATA[write fpga]]></comment>
1409 </var>
1410
1411 <arr>
1412 <name>BUF_CAL_WRITE_FPGA_REG_I231</name>
1413 <n>2</n>
1414 <idx>60</idx>
1415 <comment><![CDATA[write fpga]]></comment>
1416 </arr>
1417
1418 <var>
1419 <name>BUF_LEN_CAL_WRITE_DSP_MEM_I43</name>
1420 <idx>154</idx>
1421 <comment><![CDATA[dsp prog i43]]></comment>
1422 </var>
1423
1424 <arr>
1425 <name>BUF_CAL_WRITE_DSP_MEM_I43</name>
1426 <n>11</n>
1427 <idx>63</idx>
1428 <comment><![CDATA[dsp prog i43]]></comment>
1429 </arr>
1430
1431 <var>
1432 <name>BUF_LEN_CAL_READ_DSP_MEM_C31</name>
1433 <idx>155</idx>
1434 <comment><![CDATA[dsp prog c31]]></comment>
1435 </var>
1436
1437 <arr>
1438 <name>BUF_CAL_READ_DSP_MEM_C31</name>
1439 <n>8</n>
1440 <idx>64</idx>
1441 <comment><![CDATA[dsp prog c31]]></comment>
1442 </arr>
1443
1444 <var>
1445 <name>BUF_LEN_CAL_READ_DSP_MEM_C32</name>
1446 <idx>156</idx>
1447 <comment><![CDATA[dsp prog c32]]></comment>
1448 </var>
1449
1450 <arr>
1451 <name>BUF_CAL_READ_DSP_MEM_C32</name>
1452 <n>8</n>
1453 <idx>65</idx>
1454 <comment><![CDATA[dsp prog c32]]></comment>
1455 </arr>
1456
1457 <var>
1458 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_1</name>
1459 <idx>157</idx>
1460 <comment><![CDATA[write fpga i241_1]]></comment>
1461 </var>
1462
1463 <arr>
1464 <name>BUF_CAL_WRITE_FPGA_REG_I241_1</name>
1465 <n>2</n>
1466 <idx>66</idx>
1467 <comment><![CDATA[write fpga i241_1]]></comment>
1468 </arr>
1469
1470 <var>
1471 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_2</name>
1472 <idx>158</idx>
1473 <comment><![CDATA[write fpga i241_2]]></comment>
1474 </var>
1475
1476 <arr>
1477 <name>BUF_CAL_WRITE_FPGA_REG_I241_2</name>
1478 <n>2</n>
1479 <idx>67</idx>
1480 <comment><![CDATA[write fpga i241_2]]></comment>
1481 </arr>
1482
1483 <var>
1484 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_3</name>
1485 <idx>159</idx>
1486 <comment><![CDATA[write fpga i241_3]]></comment>
1487 </var>
1488
1489 <arr>
1490 <name>BUF_CAL_WRITE_FPGA_REG_I241_3</name>
1491 <n>2</n>
1492 <idx>68</idx>
1493 <comment><![CDATA[write fpga i241_3]]></comment>
1494 </arr>
1495
1496 <var>
1497 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_4</name>
1498 <idx>160</idx>
1499 <comment><![CDATA[write fpga i241_4]]></comment>
1500 </var>
1501
1502 <arr>
1503 <name>BUF_CAL_WRITE_FPGA_REG_I241_4</name>
1504 <n>2</n>
1505 <idx>69</idx>
1506 <comment><![CDATA[write fpga i241_4]]></comment>
1507 </arr>
1508
1509 <var>
1510 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_1</name>
1511 <idx>161</idx>
1512 <comment><![CDATA[write fpga i251_1]]></comment>
1513 </var>
1514
1515 <arr>
1516 <name>BUF_CAL_WRITE_FPGA_REG_I251_1</name>
1517 <n>2</n>
1518 <idx>70</idx>
1519 <comment><![CDATA[write fpga i251_1]]></comment>
1520 </arr>
1521
1522 <var>
1523 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_2</name>
1524 <idx>162</idx>
1525 <comment><![CDATA[write fpga i251_2]]></comment>
1526 </var>
1527
1528 <arr>
1529 <name>BUF_CAL_WRITE_FPGA_REG_I251_2</name>
1530 <n>2</n>
1531 <idx>71</idx>
1532 <comment><![CDATA[write fpga i251_2]]></comment>
1533 </arr>
1534
1535 <var>
1536 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_3</name>
1537 <idx>163</idx>
1538 <comment><![CDATA[write fpga i251_3]]></comment>
1539 </var>
1540
1541 <arr>
1542 <name>BUF_CAL_WRITE_FPGA_REG_I251_3</name>
1543 <n>2</n>
1544 <idx>72</idx>
1545 <comment><![CDATA[write fpga i251_3]]></comment>
1546 </arr>
1547
1548 <var>
1549 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_4</name>
1550 <idx>164</idx>
1551 <comment><![CDATA[write fpga i251_4]]></comment>
1552 </var>
1553
1554 <arr>
1555 <name>BUF_CAL_WRITE_FPGA_REG_I251_4</name>
1556 <n>2</n>
1557 <idx>73</idx>
1558 <comment><![CDATA[write fpga i251_4]]></comment>
1559 </arr>
1560
1561 <var>
1562 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_1</name>
1563 <idx>165</idx>
1564 <comment><![CDATA[write fpga i261_1]]></comment>
1565 </var>
1566
1567 <arr>
1568 <name>BUF_CAL_WRITE_FPGA_REG_I261_1</name>
1569 <n>2</n>
1570 <idx>74</idx>
1571 <comment><![CDATA[write fpga i261_1]]></comment>
1572 </arr>
1573
1574 <var>
1575 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_2</name>
1576 <idx>166</idx>
1577 <comment><![CDATA[write fpga i261_2]]></comment>
1578 </var>
1579
1580 <arr>
1581 <name>BUF_CAL_WRITE_FPGA_REG_I261_2</name>
1582 <n>2</n>
1583 <idx>75</idx>
1584 <comment><![CDATA[write fpga i261_2]]></comment>
1585 </arr>
1586
1587 <var>
1588 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_3</name>
1589 <idx>167</idx>
1590 <comment><![CDATA[write fpga i261_3]]></comment>
1591 </var>
1592
1593 <arr>
1594 <name>BUF_CAL_WRITE_FPGA_REG_I261_3</name>
1595 <n>2</n>
1596 <idx>76</idx>
1597 <comment><![CDATA[write fpga i261_3]]></comment>
1598 </arr>
1599
1600 <var>
1601 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_4</name>
1602 <idx>168</idx>
1603 <comment><![CDATA[write fpga i261_4]]></comment>
1604 </var>
1605
1606 <arr>
1607 <name>BUF_CAL_WRITE_FPGA_REG_I261_4</name>
1608 <n>2</n>
1609 <idx>77</idx>
1610 <comment><![CDATA[write fpga i261_4]]></comment>
1611 </arr>
1612
1613 <var>
1614 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_1</name>
1615 <idx>169</idx>
1616 <comment><![CDATA[write fpga i260_1]]></comment>
1617 </var>
1618
1619 <arr>
1620 <name>BUF_CAL_WRITE_FPGA_REG_I260_1</name>
1621 <n>2</n>
1622 <idx>78</idx>
1623 <comment><![CDATA[write fpga i260_1]]></comment>
1624 </arr>
1625
1626 <var>
1627 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_2</name>
1628 <idx>170</idx>
1629 <comment><![CDATA[write fpga i260_2]]></comment>
1630 </var>
1631
1632 <arr>
1633 <name>BUF_CAL_WRITE_FPGA_REG_I260_2</name>
1634 <n>2</n>
1635 <idx>79</idx>
1636 <comment><![CDATA[write fpga i260_2]]></comment>
1637 </arr>
1638
1639 <var>
1640 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_3</name>
1641 <idx>171</idx>
1642 <comment><![CDATA[write fpga i260_3]]></comment>
1643 </var>
1644
1645 <arr>
1646 <name>BUF_CAL_WRITE_FPGA_REG_I260_3</name>
1647 <n>2</n>
1648 <idx>80</idx>
1649 <comment><![CDATA[write fpga i260_3]]></comment>
1650 </arr>
1651
1652 <var>
1653 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_4</name>
1654 <idx>172</idx>
1655 <comment><![CDATA[write fpga i260_4]]></comment>
1656 </var>
1657
1658 <arr>
1659 <name>BUF_CAL_WRITE_FPGA_REG_I260_4</name>
1660 <n>2</n>
1661 <idx>81</idx>
1662 <comment><![CDATA[write fpga i260_4]]></comment>
1663 </arr>
1664
1665 <var>
1666 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_1</name>
1667 <idx>173</idx>
1668 <comment><![CDATA[write fpga i311_1]]></comment>
1669 </var>
1670
1671 <arr>
1672 <name>BUF_CAL_WRITE_FPGA_REG_I311_1</name>
1673 <n>2</n>
1674 <idx>82</idx>
1675 <comment><![CDATA[write fpga i311_1]]></comment>
1676 </arr>
1677
1678 <var>
1679 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_2</name>
1680 <idx>174</idx>
1681 <comment><![CDATA[write fpga i311_2]]></comment>
1682 </var>
1683
1684 <arr>
1685 <name>BUF_CAL_WRITE_FPGA_REG_I311_2</name>
1686 <n>2</n>
1687 <idx>83</idx>
1688 <comment><![CDATA[write fpga i311_2]]></comment>
1689 </arr>
1690
1691 <var>
1692 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_3</name>
1693 <idx>175</idx>
1694 <comment><![CDATA[write fpga i311_3]]></comment>
1695 </var>
1696
1697 <arr>
1698 <name>BUF_CAL_WRITE_FPGA_REG_I311_3</name>
1699 <n>2</n>
1700 <idx>84</idx>
1701 <comment><![CDATA[write fpga i311_3]]></comment>
1702 </arr>
1703
1704 <var>
1705 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_4</name>
1706 <idx>176</idx>
1707 <comment><![CDATA[write fpga i311_4]]></comment>
1708 </var>
1709
1710 <arr>
1711 <name>BUF_CAL_WRITE_FPGA_REG_I311_4</name>
1712 <n>2</n>
1713 <idx>85</idx>
1714 <comment><![CDATA[write fpga i311_4]]></comment>
1715 </arr>
1716
1717 <var>
1718 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_1</name>
1719 <idx>177</idx>
1720 <comment><![CDATA[write fpga i310_1]]></comment>
1721 </var>
1722
1723 <arr>
1724 <name>BUF_CAL_WRITE_FPGA_REG_I310_1</name>
1725 <n>2</n>
1726 <idx>86</idx>
1727 <comment><![CDATA[write fpga i310_1]]></comment>
1728 </arr>
1729
1730 <var>
1731 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_2</name>
1732 <idx>178</idx>
1733 <comment><![CDATA[write fpga i310_2]]></comment>
1734 </var>
1735
1736 <arr>
1737 <name>BUF_CAL_WRITE_FPGA_REG_I310_2</name>
1738 <n>2</n>
1739 <idx>87</idx>
1740 <comment><![CDATA[write fpga i310_2]]></comment>
1741 </arr>
1742
1743 <var>
1744 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_3</name>
1745 <idx>179</idx>
1746 <comment><![CDATA[write fpga i310_3]]></comment>
1747 </var>
1748
1749 <arr>
1750 <name>BUF_CAL_WRITE_FPGA_REG_I310_3</name>
1751 <n>2</n>
1752 <idx>88</idx>
1753 <comment><![CDATA[write fpga i310_3]]></comment>
1754 </arr>
1755
1756 <var>
1757 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_4</name>
1758 <idx>180</idx>
1759 <comment><![CDATA[write fpga i310_4]]></comment>
1760 </var>
1761
1762 <arr>
1763 <name>BUF_CAL_WRITE_FPGA_REG_I310_4</name>
1764 <n>2</n>
1765 <idx>89</idx>
1766 <comment><![CDATA[write fpga i310_4]]></comment>
1767 </arr>
1768
1769 <var>
1770 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I321</name>
1771 <idx>181</idx>
1772 <comment><![CDATA[write fpga i321]]></comment>
1773 </var>
1774
1775 <arr>
1776 <name>BUF_CAL_WRITE_FPGA_REG_I321</name>
1777 <n>2</n>
1778 <idx>90</idx>
1779 <comment><![CDATA[write fpga i321]]></comment>
1780 </arr>
1781
1782 <var>
1783 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_1</name>
1784 <idx>182</idx>
1785 <comment><![CDATA[write fpga i331_1]]></comment>
1786 </var>
1787
1788 <arr>
1789 <name>BUF_CAL_WRITE_FPGA_REG_I331_1</name>
1790 <n>2</n>
1791 <idx>91</idx>
1792 <comment><![CDATA[write fpga i331_1]]></comment>
1793 </arr>
1794
1795 <var>
1796 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_2</name>
1797 <idx>183</idx>
1798 <comment><![CDATA[write fpga i331_2]]></comment>
1799 </var>
1800
1801 <arr>
1802 <name>BUF_CAL_WRITE_FPGA_REG_I331_2</name>
1803 <n>2</n>
1804 <idx>92</idx>
1805 <comment><![CDATA[write fpga i331_2]]></comment>
1806 </arr>
1807
1808 <var>
1809 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_3</name>
1810 <idx>184</idx>
1811 <comment><![CDATA[write fpga i331_3]]></comment>
1812 </var>
1813
1814 <arr>
1815 <name>BUF_CAL_WRITE_FPGA_REG_I331_3</name>
1816 <n>2</n>
1817 <idx>93</idx>
1818 <comment><![CDATA[write fpga i331_3]]></comment>
1819 </arr>
1820
1821 <var>
1822 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_4</name>
1823 <idx>185</idx>
1824 <comment><![CDATA[write fpga i331_4]]></comment>
1825 </var>
1826
1827 <arr>
1828 <name>BUF_CAL_WRITE_FPGA_REG_I331_4</name>
1829 <n>2</n>
1830 <idx>94</idx>
1831 <comment><![CDATA[write fpga i331_4]]></comment>
1832 </arr>
1833
1834 <var>
1835 <name>BUF_LEN_CAL_WRITE_FPGA_REG_OFF</name>
1836 <idx>186</idx>
1837 <comment><![CDATA[write fpga reg off]]></comment>
1838 </var>
1839
1840 <arr>
1841 <name>BUF_CAL_WRITE_FPGA_REG_OFF</name>
1842 <n>2</n>
1843 <idx>95</idx>
1844 <comment><![CDATA[write fpga reg off]]></comment>
1845 </arr>
1846
1847 <var>
1848 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_1</name>
1849 <idx>187</idx>
1850 <comment><![CDATA[write fpga i341_1]]></comment>
1851 </var>
1852
1853 <arr>
1854 <name>BUF_CAL_WRITE_FPGA_REG_I341_1</name>
1855 <n>2</n>
1856 <idx>96</idx>
1857 <comment><![CDATA[write fpga i341_1]]></comment>
1858 </arr>
1859
1860 <var>
1861 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_2</name>
1862 <idx>188</idx>
1863 <comment><![CDATA[write fpga i341_2]]></comment>
1864 </var>
1865
1866 <arr>
1867 <name>BUF_CAL_WRITE_FPGA_REG_I341_2</name>
1868 <n>2</n>
1869 <idx>97</idx>
1870 <comment><![CDATA[write fpga i341_2]]></comment>
1871 </arr>
1872
1873 <var>
1874 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_3</name>
1875 <idx>189</idx>
1876 <comment><![CDATA[write fpga i341_3]]></comment>
1877 </var>
1878
1879 <arr>
1880 <name>BUF_CAL_WRITE_FPGA_REG_I341_3</name>
1881 <n>2</n>
1882 <idx>98</idx>
1883 <comment><![CDATA[write fpga i341_3]]></comment>
1884 </arr>
1885
1886 <var>
1887 <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_4</name>
1888 <idx>190</idx>
1889 <comment><![CDATA[write fpga i341_4]]></comment>
1890 </var>
1891
1892 <arr>
1893 <name>BUF_CAL_WRITE_FPGA_REG_I341_4</name>
1894 <n>2</n>
1895 <idx>99</idx>
1896 <comment><![CDATA[write fpga i341_4]]></comment>
1897 </arr>
1898
1899 <var>
1900 <name>AC_1_OK</name>
1901 <idx>191</idx>
1902 <comment><![CDATA[AC ON_OFF in ACQ]]></comment>
1903 </var>
1904
1905 <var>
1906 <name>AC_2_OK</name>
1907 <idx>192</idx>
1908 <comment><![CDATA[AC ON_OFF in ACQ]]></comment>
1909 </var>
1910
1911 <var>
1912 <name>AC_1_CHECK</name>
1913 <idx>193</idx>
1914 <comment><![CDATA[AC check]]></comment>
1915 </var>
1916
1917 <var>
1918 <name>AC_2_CHECK</name>
1919 <idx>194</idx>
1920 <comment><![CDATA[AC check]]></comment>
1921 </var>
1922
1923 <var>
1924 <name>AC_LOOP</name>
1925 <idx>195</idx>
1926 <comment><![CDATA[AC max loop]]></comment>
1927 </var>
1928
1929 <var>
1930 <name>AC_LOOP2</name>
1931 <idx>196</idx>
1932 <comment><![CDATA[AC max loop 2]]></comment>
1933 </var>
1934
1935 <var>
1936 <name>BUF_LEN_AC_1_SET_DAQ</name>
1937 <idx>197</idx>
1938 <comment><![CDATA[SET DAQ command]]></comment>
1939 </var>
1940
1941 <arr>
1942 <name>BUF_AC_1_SET_DAQ</name>
1943 <n>35</n>
1944 <idx>100</idx>
1945 <comment><![CDATA[SET DAQ command]]></comment>
1946 </arr>
1947
1948 <var>
1949 <name>BUF_LEN_AC_2_SET_DAQ</name>
1950 <idx>198</idx>
1951 <comment><![CDATA[SET DAQ command]]></comment>
1952 </var>
1953
1954 <arr>
1955 <name>BUF_AC_2_SET_DAQ</name>
1956 <n>35</n>
1957 <idx>101</idx>
1958 <comment><![CDATA[SET DAQ command]]></comment>
1959 </arr>
1960
1961 <var>
1962 <name>BUF_LEN_AC_2_WRITE_REG</name>
1963 <idx>202</idx>
1964 <comment><![CDATA[]]></comment>
1965 </var>
1966
1967 <arr>
1968 <name>BUF_AC_2_WRITE_REG</name>
1969 <n>15</n>
1970 <idx>105</idx>
1971 <comment><![CDATA[]]></comment>
1972 </arr>
1973
1974 <var>
1975 <name>BUF_LEN_AC_1_WRITE_REG</name>
1976 <idx>203</idx>
1977 <comment><![CDATA[]]></comment>
1978 </var>
1979
1980 <arr>
1981 <name>BUF_AC_1_WRITE_REG</name>
1982 <n>15</n>
1983 <idx>106</idx>
1984 <comment><![CDATA[]]></comment>
1985 </arr>
1986
1987 <var>
1988 <name>BUF_LEN_AC_READ_DSP_MEM</name>
1989 <idx>204</idx>
1990 <comment><![CDATA[]]></comment>
1991 </var>
1992
1993 <arr>
1994 <name>BUF_AC_READ_DSP_MEM</name>
1995 <n>3</n>
1996 <idx>107</idx>
1997 <comment><![CDATA[]]></comment>
1998 </arr>
1999
2000 <var>
2001 <name>BUF_LEN_TOF_WRITE_PMT_THR_1</name>
2002 <idx>205</idx>
2003 <comment><![CDATA[TOF set THR front end 1]]></comment>
2004 </var>
2005
2006 <arr>
2007 <name>BUF_TOF_WRITE_PMT_THR_1</name>
2008 <n>2</n>
2009 <idx>108</idx>
2010 <comment><![CDATA[TOF set THR front end 1]]></comment>
2011 </arr>
2012
2013 <var>
2014 <name>BUF_LEN_TOF_WRITE_PMT_THR_2</name>
2015 <idx>206</idx>
2016 <comment><![CDATA[TOF set THR front end 2]]></comment>
2017 </var>
2018
2019 <arr>
2020 <name>BUF_TOF_WRITE_PMT_THR_2</name>
2021 <n>2</n>
2022 <idx>109</idx>
2023 <comment><![CDATA[TOF set THR front end 2]]></comment>
2024 </arr>
2025
2026 <var>
2027 <name>BUF_LEN_TOF_WRITE_PMT_THR_3</name>
2028 <idx>207</idx>
2029 <comment><![CDATA[TOF set THR front end 3]]></comment>
2030 </var>
2031
2032 <arr>
2033 <name>BUF_TOF_WRITE_PMT_THR_3</name>
2034 <n>2</n>
2035 <idx>110</idx>
2036 <comment><![CDATA[TOF set THR front end 3]]></comment>
2037 </arr>
2038
2039 <var>
2040 <name>BUF_LEN_TOF_WRITE_PMT_THR_4</name>
2041 <idx>208</idx>
2042 <comment><![CDATA[TOF set THR front end 4]]></comment>
2043 </var>
2044
2045 <arr>
2046 <name>BUF_TOF_WRITE_PMT_THR_4</name>
2047 <n>2</n>
2048 <idx>111</idx>
2049 <comment><![CDATA[TOF set THR front end 4]]></comment>
2050 </arr>
2051
2052 <var>
2053 <name>BUF_LEN_TOF_WRITE_PMT_THR_5</name>
2054 <idx>209</idx>
2055 <comment><![CDATA[TOF set THR front end 5]]></comment>
2056 </var>
2057
2058 <arr>
2059 <name>BUF_TOF_WRITE_PMT_THR_5</name>
2060 <n>2</n>
2061 <idx>112</idx>
2062 <comment><![CDATA[TOF set THR front end 5]]></comment>
2063 </arr>
2064
2065 <var>
2066 <name>BUF_LEN_TOF_WRITE_PMT_THR_6</name>
2067 <idx>210</idx>
2068 <comment><![CDATA[TOF set THR front end 5]]></comment>
2069 </var>
2070
2071 <arr>
2072 <name>BUF_TOF_WRITE_PMT_THR_6</name>
2073 <n>2</n>
2074 <idx>113</idx>
2075 <comment><![CDATA[TOF set THR front end 5]]></comment>
2076 </arr>
2077
2078 <var>
2079 <name>TOF_OK</name>
2080 <idx>211</idx>
2081 <comment><![CDATA[TOF ON_OFF in ACQ]]></comment>
2082 </var>
2083
2084 <arr>
2085 <name>TOF_PLAN</name>
2086 <n>6</n>
2087 <idx>114</idx>
2088 <comment><![CDATA[TOF Plans selectors]]></comment>
2089 </arr>
2090
2091 <var>
2092 <name>TOF_ACTION</name>
2093 <idx>212</idx>
2094 <comment><![CDATA[TOF alarm action code]]></comment>
2095 </var>
2096
2097 <var>
2098 <name>ND_OK</name>
2099 <idx>213</idx>
2100 <comment><![CDATA[ND ON_OFF in ACQ]]></comment>
2101 </var>
2102
2103 <var>
2104 <name>ND_ATTEMPT</name>
2105 <idx>214</idx>
2106 <comment><![CDATA[Force ND in ACQ, unless ND_OK is FALSE]]></comment>
2107 </var>
2108
2109 <var>
2110 <name>ND_CMDS</name>
2111 <idx>215</idx>
2112 <comment><![CDATA[Force ND in ACQ, unless ND_OK is FALSE]]></comment>
2113 </var>
2114
2115 <var>
2116 <name>SM_WAIT_TRIG_EVENT</name>
2117 <idx>216</idx>
2118 <comment><![CDATA[Time to wait between DAQ DMA programming and the CMD I/F DMA programming (as Laben suggested)]]></comment>
2119 </var>
2120
2121 <arr>
2122 <name>PM_PERIODIC_DELAY</name>
2123 <n>4</n>
2124 <idx>115</idx>
2125 <comment><![CDATA[Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations,]]></comment>
2126 </arr>
2127
2128 <var>
2129 <name>SCM_TM_DO_CHECK_VALUES_FREQ</name>
2130 <idx>217</idx>
2131 <comment><![CDATA[Do a Check on TM values every XXX Number of cyc acq done]]></comment>
2132 </var>
2133
2134 <var>
2135 <name>POWER_KHB</name>
2136 <idx>218</idx>
2137 <comment><![CDATA[Select KHB board 0==>HOT else COLD]]></comment>
2138 </var>
2139
2140 <var>
2141 <name>PSB_TRB_S9004_ALL_ON_DELAY</name>
2142 <idx>219</idx>
2143 <comment><![CDATA[milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on)]]></comment>
2144 </var>
2145
2146 <var>
2147 <name>PSB_TRB_BIAS_WAIT</name>
2148 <idx>220</idx>
2149 <comment><![CDATA[wait between bias TRB switch on/off]]></comment>
2150 </var>
2151
2152 <arr>
2153 <name>PSB_COMMANDS</name>
2154 <n>28</n>
2155 <idx>116</idx>
2156 <comment><![CDATA[Command for PSB]]></comment>
2157 </arr>
2158
2159 <arr>
2160 <name>PSB_CALO_FE_ON</name>
2161 <n>4</n>
2162 <idx>117</idx>
2163 <comment><![CDATA[Command for PSB]]></comment>
2164 </arr>
2165
2166 <arr>
2167 <name>PSB_CALO_FE_OFF</name>
2168 <n>4</n>
2169 <idx>118</idx>
2170 <comment><![CDATA[Command for PSB]]></comment>
2171 </arr>
2172
2173 <arr>
2174 <name>PSB_CALO_FE</name>
2175 <n>4</n>
2176 <idx>119</idx>
2177 <comment><![CDATA[Command for PSB]]></comment>
2178 </arr>
2179
2180 <var>
2181 <name>PSB_CALOFE_DELAY</name>
2182 <idx>221</idx>
2183 <comment><![CDATA[Delay before power on CALO 5.7]]></comment>
2184 </var>
2185
2186 <var>
2187 <name>HV_OK</name>
2188 <idx>222</idx>
2189 <comment><![CDATA[call HV settings after TRB setting at start-up]]></comment>
2190 </var>
2191
2192 <arr>
2193 <name>HVB_COMMANDS</name>
2194 <n>12</n>
2195 <idx>120</idx>
2196 <comment><![CDATA[Command for HVB]]></comment>
2197 </arr>
2198
2199 <var>
2200 <name>TRB1_HOT</name>
2201 <idx>223</idx>
2202 <comment><![CDATA[Command for TRB]]></comment>
2203 </var>
2204
2205 <var>
2206 <name>TRB1_COLD</name>
2207 <idx>224</idx>
2208 <comment><![CDATA[Command for TRB]]></comment>
2209 </var>
2210
2211 <var>
2212 <name>TRB2_HOT</name>
2213 <idx>225</idx>
2214 <comment><![CDATA[Command for TRB]]></comment>
2215 </var>
2216
2217 <var>
2218 <name>TRB2_COLD</name>
2219 <idx>226</idx>
2220 <comment><![CDATA[Command for TRB]]></comment>
2221 </var>
2222
2223 <arr>
2224 <name>TSB_BOARD_OK</name>
2225 <n>2</n>
2226 <idx>121</idx>
2227 <comment><![CDATA[User TSB Board no 0/1 flags]]></comment>
2228 </arr>
2229
2230 <var>
2231 <name>TSB_T_OK</name>
2232 <idx>227</idx>
2233 <comment><![CDATA[Do TSB Temperature check]]></comment>
2234 </var>
2235
2236 <var>
2237 <name>TSB_B_OK</name>
2238 <idx>228</idx>
2239 <comment><![CDATA[Do B-field TSB check]]></comment>
2240 </var>
2241
2242 <var>
2243 <name>ALLPAGEAVAIL_ATTEMPT</name>
2244 <idx>229</idx>
2245 <comment><![CDATA[ATTEMP TO ALLPAGE AVAILABLE]]></comment>
2246 </var>

  ViewVC Help
Powered by ViewVC 1.1.23