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Revision 1.1.1.1 - (show annotations) (download) (as text) (vendor branch)
Tue Apr 25 09:00:20 2006 UTC (18 years, 7 months ago) by kusanagi
Branch: MAIN
CVS Tags: dataToXML1_02/01, dataToXML1_02/00, dataToXML1_03/00, dataToXML1_03/01, dataToXML1_00/00, firstRelease, dataToXML1_01/00, dataToXML1_03_02, HEAD
Changes since 1.1: +0 -0 lines
File MIME type: text/html 
These program extract in an XML format the info contained into the ROOT files generated by YODA from the PAMELA data. To visualize the XML files in a more human readable format a collection of XSL files are given in the Data subfolder.
1
2
3 <html>
4 <head>
5 <meta http-equiv="content-type"
6 content="text/html; charset=ISO-8859-1">
7 <title></title>
8 </head>
9 <body>
10 <h1>Pamela General Parameters Table</h1>
11 <h3>this file have been generated: Tue May 17 09:26:57 2005 </h3>
12 <table cellpadding=2 cellspacing=2 border=1
13 style="text-align: left; width: 100%;">
14 <tbody>
15 <tr><b>
16 <td style="vertical-align: top;"><h2>NAME</h2><br>
17 </td>
18 <td style="vertical-align: top;"><h2>TYPE</h2><br>
19 </td>
20 <td style="vertical-align: top;"><h2>DEFAULT</h2><br>
21 </td>
22 <td style="vertical-align: top;"><h2>COMMENT</h2><br>
23 </td>
24
25 </tr>
26 <tr>
27 <td style="vertical-align: top;">LOG_MASK<br>
28 </td>
29 <td style="vertical-align: top;">ARR [113]<br>
30 </td>
31 <td style="vertical-align: top;"><br>
32 </td>
33 <td style="vertical-align: top;">log level mask for each module /RO<br>
34 </td>
35 </tr><tr>
36 <td style="vertical-align: top;">LU_WRITE_ON_UART<br>
37 </td>
38 <td style="vertical-align: top;">VAR<br>
39 </td>
40 <td style="vertical-align: top;">1<br>
41 </td>
42 <td style="vertical-align: top;">enable[1]/disable[0] the UART writing /RO<br>
43 </td>
44 </tr><tr>
45 <td style="vertical-align: top;">VERBOSE_DEBUG<br>
46 </td>
47 <td style="vertical-align: top;">VAR<br>
48 </td>
49 <td style="vertical-align: top;">0<br>
50 </td>
51 <td style="vertical-align: top;">Verbose Debug mode<br>
52 </td>
53 </tr><tr>
54 <td style="vertical-align: top;">DOWNLOAD_HEADER<br>
55 </td>
56 <td style="vertical-align: top;">VAR<br>
57 </td>
58 <td style="vertical-align: top;">0<br>
59 </td>
60 <td style="vertical-align: top;">download counter, to be written in Download header info /RW-E2P<br>
61 </td>
62 </tr><tr>
63 <td style="vertical-align: top;">KHB_ALARM_REG_LOW_LEVEL_MASK<br>
64 </td>
65 <td style="vertical-align: top;">VAR<br>
66 </td>
67 <td style="vertical-align: top;">0<br>
68 </td>
69 <td style="vertical-align: top;">mask of KHB Alarm register to be low-level masked /RO<br>
70 </td>
71 </tr><tr>
72 <td style="vertical-align: top;">KHB_STATUS_REG_LOW_LEVEL_MASK<br>
73 </td>
74 <td style="vertical-align: top;">VAR<br>
75 </td>
76 <td style="vertical-align: top;">0<br>
77 </td>
78 <td style="vertical-align: top;">mask of KHB status register to be low-level masked /RO<br>
79 </td>
80 </tr><tr>
81 <td style="vertical-align: top;">PULSER_ACTION<br>
82 </td>
83 <td style="vertical-align: top;">VAR<br>
84 </td>
85 <td style="vertical-align: top;">0<br>
86 </td>
87 <td style="vertical-align: top;">pulser action at startup; [0=none,1=Reset,2:0.25Hz,3:100Hz] /RO<br>
88 </td>
89 </tr><tr>
90 <td style="vertical-align: top;">N_BOOT<br>
91 </td>
92 <td style="vertical-align: top;">VAR<br>
93 </td>
94 <td style="vertical-align: top;">0<br>
95 </td>
96 <td style="vertical-align: top;">Boot Counter /RW-E2P<br>
97 </td>
98 </tr><tr>
99 <td style="vertical-align: top;">THERMISTORS_CHECK<br>
100 </td>
101 <td style="vertical-align: top;">VAR<br>
102 </td>
103 <td style="vertical-align: top;">1<br>
104 </td>
105 <td style="vertical-align: top;">Check if thermistor are going to be checked /RO<br>
106 </td>
107 </tr><tr>
108 <td style="vertical-align: top;">THERM_MASK<br>
109 </td>
110 <td style="vertical-align: top;">VAR<br>
111 </td>
112 <td style="vertical-align: top;">65535<br>
113 </td>
114 <td style="vertical-align: top;">Thermistors mask /RO<br>
115 </td>
116 </tr><tr>
117 <td style="vertical-align: top;">THERM_LOW<br>
118 </td>
119 <td style="vertical-align: top;">ARR [16]<br>
120 </td>
121 <td style="vertical-align: top;"><br>
122 </td>
123 <td style="vertical-align: top;">Thermistor low limit /RO<br>
124 </td>
125 </tr><tr>
126 <td style="vertical-align: top;">THERM_HIGH<br>
127 </td>
128 <td style="vertical-align: top;">ARR [16]<br>
129 </td>
130 <td style="vertical-align: top;"><br>
131 </td>
132 <td style="vertical-align: top;">Thermistor high limit /RO<br>
133 </td>
134 </tr><tr>
135 <td style="vertical-align: top;">IPM_VOLTAGES_CHECK<br>
136 </td>
137 <td style="vertical-align: top;">VAR<br>
138 </td>
139 <td style="vertical-align: top;">1<br>
140 </td>
141 <td style="vertical-align: top;">Check if ipm are going to be checked /RO<br>
142 </td>
143 </tr><tr>
144 <td style="vertical-align: top;">KHB_IDAQ_CHECK<br>
145 </td>
146 <td style="vertical-align: top;">VAR<br>
147 </td>
148 <td style="vertical-align: top;">1<br>
149 </td>
150 <td style="vertical-align: top;">Check if khb&idaq are going to be checked /RO<br>
151 </td>
152 </tr><tr>
153 <td style="vertical-align: top;">NTRIG<br>
154 </td>
155 <td style="vertical-align: top;">VAR<br>
156 </td>
157 <td style="vertical-align: top;">3<br>
158 </td>
159 <td style="vertical-align: top;">Max Number of Lacks of Triggers /RO<br>
160 </td>
161 </tr><tr>
162 <td style="vertical-align: top;">TRIG<br>
163 </td>
164 <td style="vertical-align: top;">VAR<br>
165 </td>
166 <td style="vertical-align: top;">0<br>
167 </td>
168 <td style="vertical-align: top;">Counter of lacks of triggers /RW<br>
169 </td>
170 </tr><tr>
171 <td style="vertical-align: top;">CONF<br>
172 </td>
173 <td style="vertical-align: top;">TAB [5][6]<br>
174 </td>
175 <td style="vertical-align: top;"><br>
176 </td>
177 <td style="vertical-align: top;">active sensors - first dimention is the number of the incrementing configuration. second dimention is the number of FE /RO<br>
178 </td>
179 </tr><tr>
180 <td style="vertical-align: top;">CONF_SEL<br>
181 </td>
182 <td style="vertical-align: top;">VAR<br>
183 </td>
184 <td style="vertical-align: top;">0<br>
185 </td>
186 <td style="vertical-align: top;">active sensor selector /RW<br>
187 </td>
188 </tr><tr>
189 <td style="vertical-align: top;">CONFOK<br>
190 </td>
191 <td style="vertical-align: top;">VAR<br>
192 </td>
193 <td style="vertical-align: top;">1<br>
194 </td>
195 <td style="vertical-align: top;">whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON /RO<br>
196 </td>
197 </tr><tr>
198 <td style="vertical-align: top;">OFF<br>
199 </td>
200 <td style="vertical-align: top;">VAR<br>
201 </td>
202 <td style="vertical-align: top;">0<br>
203 </td>
204 <td style="vertical-align: top;">Counter of ON/OFF /RW<br>
205 </td>
206 </tr><tr>
207 <td style="vertical-align: top;">NOFF<br>
208 </td>
209 <td style="vertical-align: top;">VAR<br>
210 </td>
211 <td style="vertical-align: top;">2<br>
212 </td>
213 <td style="vertical-align: top;">Max Number of ON/OFF /RO<br>
214 </td>
215 </tr><tr>
216 <td style="vertical-align: top;">NRES<br>
217 </td>
218 <td style="vertical-align: top;">VAR<br>
219 </td>
220 <td style="vertical-align: top;">6<br>
221 </td>
222 <td style="vertical-align: top;">Max number of reset /RO<br>
223 </td>
224 </tr><tr>
225 <td style="vertical-align: top;">RES<br>
226 </td>
227 <td style="vertical-align: top;">VAR<br>
228 </td>
229 <td style="vertical-align: top;">0<br>
230 </td>
231 <td style="vertical-align: top;">Counter of reset /RW<br>
232 </td>
233 </tr><tr>
234 <td style="vertical-align: top;">WATCHDOG_RESET_DISABLE<br>
235 </td>
236 <td style="vertical-align: top;">VAR<br>
237 </td>
238 <td style="vertical-align: top;">0<br>
239 </td>
240 <td style="vertical-align: top;">disable watchdog reset: only for debugging!<br>
241 </td>
242 </tr><tr>
243 <td style="vertical-align: top;">NFAILED_POWER_ON<br>
244 </td>
245 <td style="vertical-align: top;">VAR<br>
246 </td>
247 <td style="vertical-align: top;">3<br>
248 </td>
249 <td style="vertical-align: top;">max number of failed power_on, before STOP&WAIT /RO<br>
250 </td>
251 </tr><tr>
252 <td style="vertical-align: top;">AUTO_RM_MODE<br>
253 </td>
254 <td style="vertical-align: top;">VAR<br>
255 </td>
256 <td style="vertical-align: top;">0<br>
257 </td>
258 <td style="vertical-align: top;">define the Automatic Mode for RM /RO<br>
259 </td>
260 </tr><tr>
261 <td style="vertical-align: top;">AUTO_SCM_MODE<br>
262 </td>
263 <td style="vertical-align: top;">VAR<br>
264 </td>
265 <td style="vertical-align: top;">1<br>
266 </td>
267 <td style="vertical-align: top;">define the Automatic Mode for scm /RO<br>
268 </td>
269 </tr><tr>
270 <td style="vertical-align: top;">MASK_ACQ_ALARM<br>
271 </td>
272 <td style="vertical-align: top;">VAR<br>
273 </td>
274 <td style="vertical-align: top;">65535<br>
275 </td>
276 <td style="vertical-align: top;">Alarm mask /RO<br>
277 </td>
278 </tr><tr>
279 <td style="vertical-align: top;">GOM_DURING_ALARM<br>
280 </td>
281 <td style="vertical-align: top;">VAR<br>
282 </td>
283 <td style="vertical-align: top;">0<br>
284 </td>
285 <td style="vertical-align: top;">General operation mode during alarm revelation /RW<br>
286 </td>
287 </tr><tr>
288 <td style="vertical-align: top;">PM_FORCE_RUNNING_TIMEOUT<br>
289 </td>
290 <td style="vertical-align: top;">VAR<br>
291 </td>
292 <td style="vertical-align: top;">3600000<br>
293 </td>
294 <td style="vertical-align: top;">waiting for start select mode before force go to running<br>
295 </td>
296 </tr><tr>
297 <td style="vertical-align: top;">PAMELA_ON<br>
298 </td>
299 <td style="vertical-align: top;">VAR<br>
300 </td>
301 <td style="vertical-align: top;">0<br>
302 </td>
303 <td style="vertical-align: top;">Pamela status [0=OFF-1:OFF] /RW<br>
304 </td>
305 </tr><tr>
306 <td style="vertical-align: top;">N_CALIB<br>
307 </td>
308 <td style="vertical-align: top;">VAR<br>
309 </td>
310 <td style="vertical-align: top;">0<br>
311 </td>
312 <td style="vertical-align: top;">Counter of calibratrion since start up /RW<br>
313 </td>
314 </tr><tr>
315 <td style="vertical-align: top;">AC_1_ON<br>
316 </td>
317 <td style="vertical-align: top;">VAR<br>
318 </td>
319 <td style="vertical-align: top;">0<br>
320 </td>
321 <td style="vertical-align: top;">AC 1 on from initialization /RW<br>
322 </td>
323 </tr><tr>
324 <td style="vertical-align: top;">AC_2_ON<br>
325 </td>
326 <td style="vertical-align: top;">VAR<br>
327 </td>
328 <td style="vertical-align: top;">0<br>
329 </td>
330 <td style="vertical-align: top;">AC 2 on from initialization /RW<br>
331 </td>
332 </tr><tr>
333 <td style="vertical-align: top;">POWER_MODE<br>
334 </td>
335 <td style="vertical-align: top;">VAR<br>
336 </td>
337 <td style="vertical-align: top;">1<br>
338 </td>
339 <td style="vertical-align: top;">Power mode of PAMELA /RW<br>
340 </td>
341 </tr><tr>
342 <td style="vertical-align: top;">TRIG_II<br>
343 </td>
344 <td style="vertical-align: top;">VAR<br>
345 </td>
346 <td style="vertical-align: top;">0<br>
347 </td>
348 <td style="vertical-align: top;">TRIGGER II level mode on/off /RO<br>
349 </td>
350 </tr><tr>
351 <td style="vertical-align: top;">BUF_LEN_TRIG_II_INIT<br>
352 </td>
353 <td style="vertical-align: top;">VAR<br>
354 </td>
355 <td style="vertical-align: top;">199<br>
356 </td>
357 <td style="vertical-align: top;">TRIG_II init command queue<br>
358 </td>
359 </tr><tr>
360 <td style="vertical-align: top;">BUF_TRIG_II_INIT<br>
361 </td>
362 <td style="vertical-align: top;">ARR [3750]<br>
363 </td>
364 <td style="vertical-align: top;"><br>
365 </td>
366 <td style="vertical-align: top;">TRIG_II init command queue<br>
367 </td>
368 </tr><tr>
369 <td style="vertical-align: top;">BUF_LEN_TRIG_II_ACQ<br>
370 </td>
371 <td style="vertical-align: top;">VAR<br>
372 </td>
373 <td style="vertical-align: top;">561<br>
374 </td>
375 <td style="vertical-align: top;">TRIG_II acq command queue<br>
376 </td>
377 </tr><tr>
378 <td style="vertical-align: top;">BUF_TRIG_II_ACQ<br>
379 </td>
380 <td style="vertical-align: top;">ARR [375]<br>
381 </td>
382 <td style="vertical-align: top;"><br>
383 </td>
384 <td style="vertical-align: top;">TRIG_II acq command queue<br>
385 </td>
386 </tr><tr>
387 <td style="vertical-align: top;">EXP64_MODE<br>
388 </td>
389 <td style="vertical-align: top;">VAR<br>
390 </td>
391 <td style="vertical-align: top;">1<br>
392 </td>
393 <td style="vertical-align: top;">if TRUE, working in exp 64 mode /RO<br>
394 </td>
395 </tr><tr>
396 <td style="vertical-align: top;">EXP64_MODE_DELAY<br>
397 </td>
398 <td style="vertical-align: top;">VAR<br>
399 </td>
400 <td style="vertical-align: top;">0<br>
401 </td>
402 <td style="vertical-align: top;">delay for exp 64 mode acquiring /RO<br>
403 </td>
404 </tr><tr>
405 <td style="vertical-align: top;">MH_END_OF_DOWNLOAD_TIMEOUT<br>
406 </td>
407 <td style="vertical-align: top;">VAR<br>
408 </td>
409 <td style="vertical-align: top;">60000<br>
410 </td>
411 <td style="vertical-align: top;">time out of the end of download /RO<br>
412 </td>
413 </tr><tr>
414 <td style="vertical-align: top;">PM_STOP_RUNMANAGER_TIMEOUT<br>
415 </td>
416 <td style="vertical-align: top;">VAR<br>
417 </td>
418 <td style="vertical-align: top;">1000<br>
419 </td>
420 <td style="vertical-align: top;">the maximu time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager /RO<br>
421 </td>
422 </tr><tr>
423 <td style="vertical-align: top;">PM_STOP_RUNMANAGER_TIMES_RETRY<br>
424 </td>
425 <td style="vertical-align: top;">VAR<br>
426 </td>
427 <td style="vertical-align: top;">5<br>
428 </td>
429 <td style="vertical-align: top;">The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle. /RO<br>
430 </td>
431 </tr><tr>
432 <td style="vertical-align: top;">PM_N_ORBIT_CALIB<br>
433 </td>
434 <td style="vertical-align: top;">VAR<br>
435 </td>
436 <td style="vertical-align: top;">1<br>
437 </td>
438 <td style="vertical-align: top;">Number of orbits per calibration /RO<br>
439 </td>
440 </tr><tr>
441 <td style="vertical-align: top;">WS_1_SETTING<br>
442 </td>
443 <td style="vertical-align: top;">ARR [5]<br>
444 </td>
445 <td style="vertical-align: top;"><br>
446 </td>
447 <td style="vertical-align: top;">Define the Working Schedule #1 values in ms /RO<br>
448 </td>
449 </tr><tr>
450 <td style="vertical-align: top;">WS_TIME_ORBIT<br>
451 </td>
452 <td style="vertical-align: top;">VAR<br>
453 </td>
454 <td style="vertical-align: top;">5670000<br>
455 </td>
456 <td style="vertical-align: top;">The duration in millisencond of the full orbit in ms /RO<br>
457 </td>
458 </tr><tr>
459 <td style="vertical-align: top;">WS_FAVOURITE_WS<br>
460 </td>
461 <td style="vertical-align: top;">VAR<br>
462 </td>
463 <td style="vertical-align: top;">0<br>
464 </td>
465 <td style="vertical-align: top;">The Favourite Pamela Working Schedule /RO<br>
466 </td>
467 </tr><tr>
468 <td style="vertical-align: top;">RM_N_TRIES_PREPARE_PAGE<br>
469 </td>
470 <td style="vertical-align: top;">VAR<br>
471 </td>
472 <td style="vertical-align: top;">100<br>
473 </td>
474 <td style="vertical-align: top;">Number of attempts to try to exec the prepar page before exit from the run procedure with an error /RO<br>
475 </td>
476 </tr><tr>
477 <td style="vertical-align: top;">RM_TRIES_PREPARE_PAGE_SLEEP<br>
478 </td>
479 <td style="vertical-align: top;">VAR<br>
480 </td>
481 <td style="vertical-align: top;">2<br>
482 </td>
483 <td style="vertical-align: top;">Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure /RO<br>
484 </td>
485 </tr><tr>
486 <td style="vertical-align: top;">RM_WS3_TIMER_FIRE_AFTER<br>
487 </td>
488 <td style="vertical-align: top;">VAR<br>
489 </td>
490 <td style="vertical-align: top;">8000<br>
491 </td>
492 <td style="vertical-align: top;">Time to wait for the WS3 timer to fire /RO<br>
493 </td>
494 </tr><tr>
495 <td style="vertical-align: top;">RM_RATE_METER_S1_TRH<br>
496 </td>
497 <td style="vertical-align: top;">ARR [2]<br>
498 </td>
499 <td style="vertical-align: top;"><br>
500 </td>
501 <td style="vertical-align: top;">Rate meter s1 register TRH.used to toggle A/B mode in WS3 mode. the index of the array is related to the current ACQ mode (0=A to B,1=B to A) /RO<br>
502 </td>
503 </tr><tr>
504 <td style="vertical-align: top;">RM_TIME_MAX_RUN<br>
505 </td>
506 <td style="vertical-align: top;">VAR<br>
507 </td>
508 <td style="vertical-align: top;">1800000<br>
509 </td>
510 <td style="vertical-align: top;">Max duration for an ordinary Run in milliseconds /RO<br>
511 </td>
512 </tr><tr>
513 <td style="vertical-align: top;">RM_TIME_SPECIAL_RUN<br>
514 </td>
515 <td style="vertical-align: top;">VAR<br>
516 </td>
517 <td style="vertical-align: top;">100000<br>
518 </td>
519 <td style="vertical-align: top;">duration for the special run in milliseconds /RO<br>
520 </td>
521 </tr><tr>
522 <td style="vertical-align: top;">RM_ACQCHECK_PERIOD<br>
523 </td>
524 <td style="vertical-align: top;">VAR<br>
525 </td>
526 <td style="vertical-align: top;">1000<br>
527 </td>
528 <td style="vertical-align: top;">period of acquisition check in milliseconds /RO<br>
529 </td>
530 </tr><tr>
531 <td style="vertical-align: top;">RM_FLUSH_TIMEOUT<br>
532 </td>
533 <td style="vertical-align: top;">VAR<br>
534 </td>
535 <td style="vertical-align: top;">20000<br>
536 </td>
537 <td style="vertical-align: top;">timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT /RO<br>
538 </td>
539 </tr><tr>
540 <td style="vertical-align: top;">RM_NO_FLUSH_PARAM_DUMP<br>
541 </td>
542 <td style="vertical-align: top;">VAR<br>
543 </td>
544 <td style="vertical-align: top;">200<br>
545 </td>
546 <td style="vertical-align: top;">Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never. /RO<br>
547 </td>
548 </tr><tr>
549 <td style="vertical-align: top;">RM_DUMP_ALL_PARAMS<br>
550 </td>
551 <td style="vertical-align: top;">VAR<br>
552 </td>
553 <td style="vertical-align: top;">0<br>
554 </td>
555 <td style="vertical-align: top;">dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs /RO<br>
556 </td>
557 </tr><tr>
558 <td style="vertical-align: top;">RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ<br>
559 </td>
560 <td style="vertical-align: top;">VAR<br>
561 </td>
562 <td style="vertical-align: top;">70<br>
563 </td>
564 <td style="vertical-align: top;">number of release busy inserted in the ACQ command queue in After_Calib mode /RO<br>
565 </td>
566 </tr><tr>
567 <td style="vertical-align: top;">PWR_IPM_CONF<br>
568 </td>
569 <td style="vertical-align: top;">ARR [6]<br>
570 </td>
571 <td style="vertical-align: top;"><br>
572 </td>
573 <td style="vertical-align: top;">IMP desired configuration for initial poweron 6 bitmask /RO<br>
574 </td>
575 </tr><tr>
576 <td style="vertical-align: top;">PWR_WAIT_BEFORE_SENDTC<br>
577 </td>
578 <td style="vertical-align: top;">VAR<br>
579 </td>
580 <td style="vertical-align: top;">110<br>
581 </td>
582 <td style="vertical-align: top;">time to wait before send 2 successive HL /RO<br>
583 </td>
584 </tr><tr>
585 <td style="vertical-align: top;">PWR_CMD2PSB_DELAY<br>
586 </td>
587 <td style="vertical-align: top;">VAR<br>
588 </td>
589 <td style="vertical-align: top;">100<br>
590 </td>
591 <td style="vertical-align: top;">time to wait before every CMD2PSB<br>
592 </td>
593 </tr><tr>
594 <td style="vertical-align: top;">PWR_TRB_READ_ATTEMPTS<br>
595 </td>
596 <td style="vertical-align: top;">VAR<br>
597 </td>
598 <td style="vertical-align: top;">10<br>
599 </td>
600 <td style="vertical-align: top;">number of attempts to sent a command to the TRB before a timeout /RO<br>
601 </td>
602 </tr><tr>
603 <td style="vertical-align: top;">PWR_KHB_INITBOARD_TWICE_DELAY<br>
604 </td>
605 <td style="vertical-align: top;">VAR<br>
606 </td>
607 <td style="vertical-align: top;">500<br>
608 </td>
609 <td style="vertical-align: top;">milliseconds to wait between two KHB Init Board in PWR_DcdcON /RO<br>
610 </td>
611 </tr><tr>
612 <td style="vertical-align: top;">PWR_IPM_WAIT_OK_N_ATTEMPT<br>
613 </td>
614 <td style="vertical-align: top;">VAR<br>
615 </td>
616 <td style="vertical-align: top;">150<br>
617 </td>
618 <td style="vertical-align: top;">attempts of ipm check ok at power on /RO<br>
619 </td>
620 </tr><tr>
621 <td style="vertical-align: top;">PWR_IPM_WAIT_OK_DELAY_ATTEMPT<br>
622 </td>
623 <td style="vertical-align: top;">VAR<br>
624 </td>
625 <td style="vertical-align: top;">1000<br>
626 </td>
627 <td style="vertical-align: top;">attempts of ipm check ok at power on /RO<br>
628 </td>
629 </tr><tr>
630 <td style="vertical-align: top;">PWR_VOLTAGE_N_ATTEMPT<br>
631 </td>
632 <td style="vertical-align: top;">VAR<br>
633 </td>
634 <td style="vertical-align: top;">10<br>
635 </td>
636 <td style="vertical-align: top;">no of millisecond to wait in VOLTAGE IPM procedure /RO<br>
637 </td>
638 </tr><tr>
639 <td style="vertical-align: top;">PWR_VOLTAGE_DELAY_ATTEMPT<br>
640 </td>
641 <td style="vertical-align: top;">VAR<br>
642 </td>
643 <td style="vertical-align: top;">1000<br>
644 </td>
645 <td style="vertical-align: top;">no of millisecond to wain in VOLTAGE IPM procedure /RO<br>
646 </td>
647 </tr><tr>
648 <td style="vertical-align: top;">PWR_VOLTAGE_IPM_RANGE_ON_MAX<br>
649 </td>
650 <td style="vertical-align: top;">ARR [6]<br>
651 </td>
652 <td style="vertical-align: top;"><br>
653 </td>
654 <td style="vertical-align: top;">ADC min voltage values if ON /RO<br>
655 </td>
656 </tr><tr>
657 <td style="vertical-align: top;">PWR_VOLTAGE_IPM_RANGE_ON_MIN<br>
658 </td>
659 <td style="vertical-align: top;">ARR [6]<br>
660 </td>
661 <td style="vertical-align: top;"><br>
662 </td>
663 <td style="vertical-align: top;">ADC min voltage values if ON /RO<br>
664 </td>
665 </tr><tr>
666 <td style="vertical-align: top;">PWR_VOLTAGE_IPM_RANGE_OFF_MAX<br>
667 </td>
668 <td style="vertical-align: top;">ARR [6]<br>
669 </td>
670 <td style="vertical-align: top;"><br>
671 </td>
672 <td style="vertical-align: top;">ADC min voltage values if OFF /RO<br>
673 </td>
674 </tr><tr>
675 <td style="vertical-align: top;">PWR_VOLTAGE_IPM_RANGE_OFF_MIN<br>
676 </td>
677 <td style="vertical-align: top;">ARR [6]<br>
678 </td>
679 <td style="vertical-align: top;"><br>
680 </td>
681 <td style="vertical-align: top;">ADC min voltage values if OFF /RO<br>
682 </td>
683 </tr><tr>
684 <td style="vertical-align: top;">PWR_TRB1_SET<br>
685 </td>
686 <td style="vertical-align: top;">VAR<br>
687 </td>
688 <td style="vertical-align: top;">16383<br>
689 </td>
690 <td style="vertical-align: top;">trb 1 setting /RO<br>
691 </td>
692 </tr><tr>
693 <td style="vertical-align: top;">PWR_TRB2_SET<br>
694 </td>
695 <td style="vertical-align: top;">VAR<br>
696 </td>
697 <td style="vertical-align: top;">16383<br>
698 </td>
699 <td style="vertical-align: top;">trb 2 setting /RO<br>
700 </td>
701 </tr><tr>
702 <td style="vertical-align: top;">PWR_TRB_SET_DELAY<br>
703 </td>
704 <td style="vertical-align: top;">VAR<br>
705 </td>
706 <td style="vertical-align: top;">20<br>
707 </td>
708 <td style="vertical-align: top;">delay after trb set cmd /RO<br>
709 </td>
710 </tr><tr>
711 <td style="vertical-align: top;">PWR_TRB_READ_DELAY<br>
712 </td>
713 <td style="vertical-align: top;">VAR<br>
714 </td>
715 <td style="vertical-align: top;">20<br>
716 </td>
717 <td style="vertical-align: top;">delay after trb read cmd /RO<br>
718 </td>
719 </tr><tr>
720 <td style="vertical-align: top;">PWR_IPM_ACTION<br>
721 </td>
722 <td style="vertical-align: top;">TAB [3][64]<br>
723 </td>
724 <td style="vertical-align: top;"><br>
725 </td>
726 <td style="vertical-align: top;">Main Table for actions to be done in IPM Check procedure<br>
727 </td>
728 </tr><tr>
729 <td style="vertical-align: top;">HB_N_ATTEMPT_WRITE2PIF<br>
730 </td>
731 <td style="vertical-align: top;">VAR<br>
732 </td>
733 <td style="vertical-align: top;">2<br>
734 </td>
735 <td style="vertical-align: top;">Number of attempt to write on PIF after return an error /RO<br>
736 </td>
737 </tr><tr>
738 <td style="vertical-align: top;">HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF<br>
739 </td>
740 <td style="vertical-align: top;">VAR<br>
741 </td>
742 <td style="vertical-align: top;">100<br>
743 </td>
744 <td style="vertical-align: top;">Waint time after a failed attempt on PIF write /RO<br>
745 </td>
746 </tr><tr>
747 <td style="vertical-align: top;">HB_WRITE2PIF_TIMEOUT<br>
748 </td>
749 <td style="vertical-align: top;">VAR<br>
750 </td>
751 <td style="vertical-align: top;">1000<br>
752 </td>
753 <td style="vertical-align: top;">timeout time time to wait a sketchboard free in Write2PIF /RO<br>
754 </td>
755 </tr><tr>
756 <td style="vertical-align: top;">HB_ALMOST_FULL<br>
757 </td>
758 <td style="vertical-align: top;">VAR<br>
759 </td>
760 <td style="vertical-align: top;">80<br>
761 </td>
762 <td style="vertical-align: top;">says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage. /RM<br>
763 </td>
764 </tr><tr>
765 <td style="vertical-align: top;">TM_FILTER_OPERATION<br>
766 </td>
767 <td style="vertical-align: top;">ARR [78]<br>
768 </td>
769 <td style="vertical-align: top;"><br>
770 </td>
771 <td style="vertical-align: top;">low level telemetry filter operation: 0->apply no filter 1->set value 2->ORed mask 3->ANDed mask /RO<br>
772 </td>
773 </tr><tr>
774 <td style="vertical-align: top;">TM_FILTER_VALUE<br>
775 </td>
776 <td style="vertical-align: top;">ARR [78]<br>
777 </td>
778 <td style="vertical-align: top;"><br>
779 </td>
780 <td style="vertical-align: top;">low level telemetry filted values /RO<br>
781 </td>
782 </tr><tr>
783 <td style="vertical-align: top;">TM_VRL_SUSPEND_HCL<br>
784 </td>
785 <td style="vertical-align: top;">VAR<br>
786 </td>
787 <td style="vertical-align: top;">110<br>
788 </td>
789 <td style="vertical-align: top;">wait time between two HCL commands for the VRL /RO<br>
790 </td>
791 </tr><tr>
792 <td style="vertical-align: top;">TM_VRL_SUSPEND_BEFORE_START<br>
793 </td>
794 <td style="vertical-align: top;">VAR<br>
795 </td>
796 <td style="vertical-align: top;">1<br>
797 </td>
798 <td style="vertical-align: top;">wait time before start VRL /RO<br>
799 </td>
800 </tr><tr>
801 <td style="vertical-align: top;">DAQ_EVENT_RECEIVE_TIMEOUT<br>
802 </td>
803 <td style="vertical-align: top;">VAR<br>
804 </td>
805 <td style="vertical-align: top;">20000<br>
806 </td>
807 <td style="vertical-align: top;">PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply /RO<br>
808 </td>
809 </tr><tr>
810 <td style="vertical-align: top;">DAQ_WAITFREECMDIF_N<br>
811 </td>
812 <td style="vertical-align: top;">VAR<br>
813 </td>
814 <td style="vertical-align: top;">4<br>
815 </td>
816 <td style="vertical-align: top;">Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched /RO<br>
817 </td>
818 </tr><tr>
819 <td style="vertical-align: top;">TRB_OK<br>
820 </td>
821 <td style="vertical-align: top;">VAR<br>
822 </td>
823 <td style="vertical-align: top;">1<br>
824 </td>
825 <td style="vertical-align: top;">Use ON_OFF tracker in ACQ /RO<br>
826 </td>
827 </tr><tr>
828 <td style="vertical-align: top;">TRIGGER_MODE_A<br>
829 </td>
830 <td style="vertical-align: top;">VAR<br>
831 </td>
832 <td style="vertical-align: top;">1<br>
833 </td>
834 <td style="vertical-align: top;">Trigger type for acq mode A /RO<br>
835 </td>
836 </tr><tr>
837 <td style="vertical-align: top;">TRIGGER_MODE_B<br>
838 </td>
839 <td style="vertical-align: top;">VAR<br>
840 </td>
841 <td style="vertical-align: top;">3<br>
842 </td>
843 <td style="vertical-align: top;">Trigger type for acq mode B /RO<br>
844 </td>
845 </tr><tr>
846 <td style="vertical-align: top;">TRIGGER_BUSY_CONTROL<br>
847 </td>
848 <td style="vertical-align: top;">VAR<br>
849 </td>
850 <td style="vertical-align: top;">0<br>
851 </td>
852 <td style="vertical-align: top;">Select the check mask of the busy alaarm /RO<br>
853 </td>
854 </tr><tr>
855 <td style="vertical-align: top;">TB_LINK<br>
856 </td>
857 <td style="vertical-align: top;">VAR<br>
858 </td>
859 <td style="vertical-align: top;">1<br>
860 </td>
861 <td style="vertical-align: top;">Trigger Board to use 1 or 2 /RO<br>
862 </td>
863 </tr><tr>
864 <td style="vertical-align: top;">TB_LINK_CUSTOM<br>
865 </td>
866 <td style="vertical-align: top;">VAR<br>
867 </td>
868 <td style="vertical-align: top;">1<br>
869 </td>
870 <td style="vertical-align: top;">Trigger Board CUSTOMto use 1 or 2 /RO<br>
871 </td>
872 </tr><tr>
873 <td style="vertical-align: top;">BUF_LEN_TB_SET_ALARM_MASK<br>
874 </td>
875 <td style="vertical-align: top;">VAR<br>
876 </td>
877 <td style="vertical-align: top;">8<br>
878 </td>
879 <td style="vertical-align: top;">TRG queue<br>
880 </td>
881 </tr><tr>
882 <td style="vertical-align: top;">BUF_TB_SET_ALARM_MASK<br>
883 </td>
884 <td style="vertical-align: top;">ARR [2]<br>
885 </td>
886 <td style="vertical-align: top;"><br>
887 </td>
888 <td style="vertical-align: top;">TRG queue<br>
889 </td>
890 </tr><tr>
891 <td style="vertical-align: top;">BUF_LEN_TB_SET_PMT_MASK<br>
892 </td>
893 <td style="vertical-align: top;">VAR<br>
894 </td>
895 <td style="vertical-align: top;">12<br>
896 </td>
897 <td style="vertical-align: top;">TRG queue<br>
898 </td>
899 </tr><tr>
900 <td style="vertical-align: top;">BUF_TB_SET_PMT_MASK<br>
901 </td>
902 <td style="vertical-align: top;">ARR [3]<br>
903 </td>
904 <td style="vertical-align: top;"><br>
905 </td>
906 <td style="vertical-align: top;">TRG queue<br>
907 </td>
908 </tr><tr>
909 <td style="vertical-align: top;">BUF_LEN_TB_SET_S4_CAL_MASK<br>
910 </td>
911 <td style="vertical-align: top;">VAR<br>
912 </td>
913 <td style="vertical-align: top;">7<br>
914 </td>
915 <td style="vertical-align: top;">TRG queue<br>
916 </td>
917 </tr><tr>
918 <td style="vertical-align: top;">BUF_TB_SET_S4_CAL_MASK<br>
919 </td>
920 <td style="vertical-align: top;">ARR [2]<br>
921 </td>
922 <td style="vertical-align: top;"><br>
923 </td>
924 <td style="vertical-align: top;">TRG queue<br>
925 </td>
926 </tr><tr>
927 <td style="vertical-align: top;">BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT<br>
928 </td>
929 <td style="vertical-align: top;">VAR<br>
930 </td>
931 <td style="vertical-align: top;">9<br>
932 </td>
933 <td style="vertical-align: top;"> <br>
934 </td>
935 </tr><tr>
936 <td style="vertical-align: top;">BUF_TB_SET_BUSY_MASK_IDAQ_HOT<br>
937 </td>
938 <td style="vertical-align: top;">ARR [5]<br>
939 </td>
940 <td style="vertical-align: top;"><br>
941 </td>
942 <td style="vertical-align: top;"> <br>
943 </td>
944 </tr><tr>
945 <td style="vertical-align: top;">BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD<br>
946 </td>
947 <td style="vertical-align: top;">VAR<br>
948 </td>
949 <td style="vertical-align: top;">9<br>
950 </td>
951 <td style="vertical-align: top;"> <br>
952 </td>
953 </tr><tr>
954 <td style="vertical-align: top;">BUF_TB_SET_BUSY_MASK_IDAQ_COLD<br>
955 </td>
956 <td style="vertical-align: top;">ARR [5]<br>
957 </td>
958 <td style="vertical-align: top;"><br>
959 </td>
960 <td style="vertical-align: top;"> <br>
961 </td>
962 </tr><tr>
963 <td style="vertical-align: top;">TRK_OK<br>
964 </td>
965 <td style="vertical-align: top;">VAR<br>
966 </td>
967 <td style="vertical-align: top;">1<br>
968 </td>
969 <td style="vertical-align: top;">Use ON_OFF tracker in ACQ /RO<br>
970 </td>
971 </tr><tr>
972 <td style="vertical-align: top;">TRK_DSP_OK<br>
973 </td>
974 <td style="vertical-align: top;">TAB [2][6]<br>
975 </td>
976 <td style="vertical-align: top;"><br>
977 </td>
978 <td style="vertical-align: top;">Tracker dsp ON_OFF in ACQ /RO<br>
979 </td>
980 </tr><tr>
981 <td style="vertical-align: top;">TRK_CALIB_MODE<br>
982 </td>
983 <td style="vertical-align: top;">VAR<br>
984 </td>
985 <td style="vertical-align: top;">1<br>
986 </td>
987 <td style="vertical-align: top;">Tracker calibration mode /RO<br>
988 </td>
989 </tr><tr>
990 <td style="vertical-align: top;">TRK_TIME_SHORT<br>
991 </td>
992 <td style="vertical-align: top;">VAR<br>
993 </td>
994 <td style="vertical-align: top;">13<br>
995 </td>
996 <td style="vertical-align: top;">Tracker wait loop for 128 loop /RO<br>
997 </td>
998 </tr><tr>
999 <td style="vertical-align: top;">TRK_TIME_LONG<br>
1000 </td>
1001 <td style="vertical-align: top;">VAR<br>
1002 </td>
1003 <td style="vertical-align: top;">0<br>
1004 </td>
1005 <td style="vertical-align: top;">Tracker wait loop for 8 loop /RO<br>
1006 </td>
1007 </tr><tr>
1008 <td style="vertical-align: top;">TRK_DSP_MASK<br>
1009 </td>
1010 <td style="vertical-align: top;">TAB [2][6]<br>
1011 </td>
1012 <td style="vertical-align: top;"><br>
1013 </td>
1014 <td style="vertical-align: top;">Traker dsp mask /RO<br>
1015 </td>
1016 </tr><tr>
1017 <td style="vertical-align: top;">TRK_LOAD_PRG<br>
1018 </td>
1019 <td style="vertical-align: top;">ARR [2]<br>
1020 </td>
1021 <td style="vertical-align: top;"><br>
1022 </td>
1023 <td style="vertical-align: top;">The way the DSP program is loaded /RO<br>
1024 </td>
1025 </tr><tr>
1026 <td style="vertical-align: top;">TRK_CALIB_INIT<br>
1027 </td>
1028 <td style="vertical-align: top;">VAR<br>
1029 </td>
1030 <td style="vertical-align: top;">104<br>
1031 </td>
1032 <td style="vertical-align: top;">modality of calibration /RO<br>
1033 </td>
1034 </tr><tr>
1035 <td style="vertical-align: top;">TRK_NLOOP<br>
1036 </td>
1037 <td style="vertical-align: top;">VAR<br>
1038 </td>
1039 <td style="vertical-align: top;">12<br>
1040 </td>
1041 <td style="vertical-align: top;">macro loop number /RO<br>
1042 </td>
1043 </tr><tr>
1044 <td style="vertical-align: top;">TRK_PED_MIN_0<br>
1045 </td>
1046 <td style="vertical-align: top;">TAB [3][6]<br>
1047 </td>
1048 <td style="vertical-align: top;"><br>
1049 </td>
1050 <td style="vertical-align: top;">Tracker 0 ped min value /RO<br>
1051 </td>
1052 </tr><tr>
1053 <td style="vertical-align: top;">TRK_PED_MIN_1<br>
1054 </td>
1055 <td style="vertical-align: top;">TAB [3][6]<br>
1056 </td>
1057 <td style="vertical-align: top;"><br>
1058 </td>
1059 <td style="vertical-align: top;">Tracker 1 ped min value /RO<br>
1060 </td>
1061 </tr><tr>
1062 <td style="vertical-align: top;">TRK_PED_MAX_0<br>
1063 </td>
1064 <td style="vertical-align: top;">TAB [3][6]<br>
1065 </td>
1066 <td style="vertical-align: top;"><br>
1067 </td>
1068 <td style="vertical-align: top;">Tracker 0 ped max value /RO<br>
1069 </td>
1070 </tr><tr>
1071 <td style="vertical-align: top;">TRK_PED_MAX_1<br>
1072 </td>
1073 <td style="vertical-align: top;">TAB [3][6]<br>
1074 </td>
1075 <td style="vertical-align: top;"><br>
1076 </td>
1077 <td style="vertical-align: top;">Tracker 1 ped max value /RO<br>
1078 </td>
1079 </tr><tr>
1080 <td style="vertical-align: top;">TRK_SIG_MIN_0<br>
1081 </td>
1082 <td style="vertical-align: top;">TAB [3][6]<br>
1083 </td>
1084 <td style="vertical-align: top;"><br>
1085 </td>
1086 <td style="vertical-align: top;">Tracker 0 sig min value /RO<br>
1087 </td>
1088 </tr><tr>
1089 <td style="vertical-align: top;">TRK_SIG_MIN_1<br>
1090 </td>
1091 <td style="vertical-align: top;">TAB [3][6]<br>
1092 </td>
1093 <td style="vertical-align: top;"><br>
1094 </td>
1095 <td style="vertical-align: top;">Tracker 1 sig min value /RO<br>
1096 </td>
1097 </tr><tr>
1098 <td style="vertical-align: top;">TRK_SIG_MAX_0<br>
1099 </td>
1100 <td style="vertical-align: top;">TAB [3][6]<br>
1101 </td>
1102 <td style="vertical-align: top;"><br>
1103 </td>
1104 <td style="vertical-align: top;">Tracker 0 sig min value /RO<br>
1105 </td>
1106 </tr><tr>
1107 <td style="vertical-align: top;">TRK_SIG_MAX_1<br>
1108 </td>
1109 <td style="vertical-align: top;">TAB [3][6]<br>
1110 </td>
1111 <td style="vertical-align: top;"><br>
1112 </td>
1113 <td style="vertical-align: top;">Tracker 1 sig min value /RO<br>
1114 </td>
1115 </tr><tr>
1116 <td style="vertical-align: top;">TRK_BAD_MAX_0<br>
1117 </td>
1118 <td style="vertical-align: top;">TAB [3][6]<br>
1119 </td>
1120 <td style="vertical-align: top;"><br>
1121 </td>
1122 <td style="vertical-align: top;">Tracker 0 bad max value /RO<br>
1123 </td>
1124 </tr><tr>
1125 <td style="vertical-align: top;">TRK_BAD_MAX_1<br>
1126 </td>
1127 <td style="vertical-align: top;">TAB [3][6]<br>
1128 </td>
1129 <td style="vertical-align: top;"><br>
1130 </td>
1131 <td style="vertical-align: top;">Tracker 1 bad max value /RO<br>
1132 </td>
1133 </tr><tr>
1134 <td style="vertical-align: top;">BUF_LEN_TRK_PROGRAM<br>
1135 </td>
1136 <td style="vertical-align: top;">VAR<br>
1137 </td>
1138 <td style="vertical-align: top;">10644<br>
1139 </td>
1140 <td style="vertical-align: top;">TRK DSP Program /RO<br>
1141 </td>
1142 </tr><tr>
1143 <td style="vertical-align: top;">BUF_TRK_PROGRAM<br>
1144 </td>
1145 <td style="vertical-align: top;">ARR [3000]<br>
1146 </td>
1147 <td style="vertical-align: top;"><br>
1148 </td>
1149 <td style="vertical-align: top;">TRK DSP Program /RO<br>
1150 </td>
1151 </tr><tr>
1152 <td style="vertical-align: top;">BUF_LEN_TRK_TRAILER_PRG_0<br>
1153 </td>
1154 <td style="vertical-align: top;">VAR<br>
1155 </td>
1156 <td style="vertical-align: top;">1<br>
1157 </td>
1158 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 0 /RO<br>
1159 </td>
1160 </tr><tr>
1161 <td style="vertical-align: top;">BUF_TRK_TRAILER_PRG_0<br>
1162 </td>
1163 <td style="vertical-align: top;">ARR [3]<br>
1164 </td>
1165 <td style="vertical-align: top;"><br>
1166 </td>
1167 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 0 /RO<br>
1168 </td>
1169 </tr><tr>
1170 <td style="vertical-align: top;">BUF_LEN_TRK_TRAILER_PRG_1<br>
1171 </td>
1172 <td style="vertical-align: top;">VAR<br>
1173 </td>
1174 <td style="vertical-align: top;">1<br>
1175 </td>
1176 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 1 /RO<br>
1177 </td>
1178 </tr><tr>
1179 <td style="vertical-align: top;">BUF_TRK_TRAILER_PRG_1<br>
1180 </td>
1181 <td style="vertical-align: top;">ARR [3]<br>
1182 </td>
1183 <td style="vertical-align: top;"><br>
1184 </td>
1185 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 1 /RO<br>
1186 </td>
1187 </tr><tr>
1188 <td style="vertical-align: top;">BUF_LEN_TRK_TRAILER_PRG_2<br>
1189 </td>
1190 <td style="vertical-align: top;">VAR<br>
1191 </td>
1192 <td style="vertical-align: top;">1<br>
1193 </td>
1194 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 2 /RO<br>
1195 </td>
1196 </tr><tr>
1197 <td style="vertical-align: top;">BUF_TRK_TRAILER_PRG_2<br>
1198 </td>
1199 <td style="vertical-align: top;">ARR [3]<br>
1200 </td>
1201 <td style="vertical-align: top;"><br>
1202 </td>
1203 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 2 /RO<br>
1204 </td>
1205 </tr><tr>
1206 <td style="vertical-align: top;">BUF_LEN_TRK_TRAILER_PRG_3<br>
1207 </td>
1208 <td style="vertical-align: top;">VAR<br>
1209 </td>
1210 <td style="vertical-align: top;">1<br>
1211 </td>
1212 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 3 /RO<br>
1213 </td>
1214 </tr><tr>
1215 <td style="vertical-align: top;">BUF_TRK_TRAILER_PRG_3<br>
1216 </td>
1217 <td style="vertical-align: top;">ARR [3]<br>
1218 </td>
1219 <td style="vertical-align: top;"><br>
1220 </td>
1221 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 3 /RO<br>
1222 </td>
1223 </tr><tr>
1224 <td style="vertical-align: top;">BUF_LEN_TRK_TRAILER_PRG_4<br>
1225 </td>
1226 <td style="vertical-align: top;">VAR<br>
1227 </td>
1228 <td style="vertical-align: top;">1<br>
1229 </td>
1230 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 4 /RO<br>
1231 </td>
1232 </tr><tr>
1233 <td style="vertical-align: top;">BUF_TRK_TRAILER_PRG_4<br>
1234 </td>
1235 <td style="vertical-align: top;">ARR [3]<br>
1236 </td>
1237 <td style="vertical-align: top;"><br>
1238 </td>
1239 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 4 /RO<br>
1240 </td>
1241 </tr><tr>
1242 <td style="vertical-align: top;">BUF_LEN_TRK_TRAILER_PRG_5<br>
1243 </td>
1244 <td style="vertical-align: top;">VAR<br>
1245 </td>
1246 <td style="vertical-align: top;">1<br>
1247 </td>
1248 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 5 /RO<br>
1249 </td>
1250 </tr><tr>
1251 <td style="vertical-align: top;">BUF_TRK_TRAILER_PRG_5<br>
1252 </td>
1253 <td style="vertical-align: top;">ARR [3]<br>
1254 </td>
1255 <td style="vertical-align: top;"><br>
1256 </td>
1257 <td style="vertical-align: top;">TRK DSP Program Trailer for DSP 5 /RO<br>
1258 </td>
1259 </tr><tr>
1260 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_1_0<br>
1261 </td>
1262 <td style="vertical-align: top;">VAR<br>
1263 </td>
1264 <td style="vertical-align: top;">30<br>
1265 </td>
1266 <td style="vertical-align: top;">TRK command queue /RO<br>
1267 </td>
1268 </tr><tr>
1269 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_1_0<br>
1270 </td>
1271 <td style="vertical-align: top;">ARR [10]<br>
1272 </td>
1273 <td style="vertical-align: top;"><br>
1274 </td>
1275 <td style="vertical-align: top;">TRK command queue /RO<br>
1276 </td>
1277 </tr><tr>
1278 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_1_1<br>
1279 </td>
1280 <td style="vertical-align: top;">VAR<br>
1281 </td>
1282 <td style="vertical-align: top;">30<br>
1283 </td>
1284 <td style="vertical-align: top;">TRK command queue /RO<br>
1285 </td>
1286 </tr><tr>
1287 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_1_1<br>
1288 </td>
1289 <td style="vertical-align: top;">ARR [10]<br>
1290 </td>
1291 <td style="vertical-align: top;"><br>
1292 </td>
1293 <td style="vertical-align: top;">TRK command queue /RO<br>
1294 </td>
1295 </tr><tr>
1296 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_1_2<br>
1297 </td>
1298 <td style="vertical-align: top;">VAR<br>
1299 </td>
1300 <td style="vertical-align: top;">30<br>
1301 </td>
1302 <td style="vertical-align: top;">TRK command queue /RO<br>
1303 </td>
1304 </tr><tr>
1305 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_1_2<br>
1306 </td>
1307 <td style="vertical-align: top;">ARR [10]<br>
1308 </td>
1309 <td style="vertical-align: top;"><br>
1310 </td>
1311 <td style="vertical-align: top;">TRK command queue /RO<br>
1312 </td>
1313 </tr><tr>
1314 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_1_3<br>
1315 </td>
1316 <td style="vertical-align: top;">VAR<br>
1317 </td>
1318 <td style="vertical-align: top;">30<br>
1319 </td>
1320 <td style="vertical-align: top;">TRK command queue /RO<br>
1321 </td>
1322 </tr><tr>
1323 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_1_3<br>
1324 </td>
1325 <td style="vertical-align: top;">ARR [10]<br>
1326 </td>
1327 <td style="vertical-align: top;"><br>
1328 </td>
1329 <td style="vertical-align: top;">TRK command queue /RO<br>
1330 </td>
1331 </tr><tr>
1332 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_1_4<br>
1333 </td>
1334 <td style="vertical-align: top;">VAR<br>
1335 </td>
1336 <td style="vertical-align: top;">30<br>
1337 </td>
1338 <td style="vertical-align: top;">TRK command queue /RO<br>
1339 </td>
1340 </tr><tr>
1341 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_1_4<br>
1342 </td>
1343 <td style="vertical-align: top;">ARR [10]<br>
1344 </td>
1345 <td style="vertical-align: top;"><br>
1346 </td>
1347 <td style="vertical-align: top;">TRK command queue /RO<br>
1348 </td>
1349 </tr><tr>
1350 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_1_5<br>
1351 </td>
1352 <td style="vertical-align: top;">VAR<br>
1353 </td>
1354 <td style="vertical-align: top;">30<br>
1355 </td>
1356 <td style="vertical-align: top;">TRK command queue /RO<br>
1357 </td>
1358 </tr><tr>
1359 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_1_5<br>
1360 </td>
1361 <td style="vertical-align: top;">ARR [10]<br>
1362 </td>
1363 <td style="vertical-align: top;"><br>
1364 </td>
1365 <td style="vertical-align: top;">TRK command queue /RO<br>
1366 </td>
1367 </tr><tr>
1368 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_2_0<br>
1369 </td>
1370 <td style="vertical-align: top;">VAR<br>
1371 </td>
1372 <td style="vertical-align: top;">30<br>
1373 </td>
1374 <td style="vertical-align: top;">TRK command queue /RO<br>
1375 </td>
1376 </tr><tr>
1377 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_2_0<br>
1378 </td>
1379 <td style="vertical-align: top;">ARR [10]<br>
1380 </td>
1381 <td style="vertical-align: top;"><br>
1382 </td>
1383 <td style="vertical-align: top;">TRK command queue /RO<br>
1384 </td>
1385 </tr><tr>
1386 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_2_1<br>
1387 </td>
1388 <td style="vertical-align: top;">VAR<br>
1389 </td>
1390 <td style="vertical-align: top;">30<br>
1391 </td>
1392 <td style="vertical-align: top;">TRK command queue /RO<br>
1393 </td>
1394 </tr><tr>
1395 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_2_1<br>
1396 </td>
1397 <td style="vertical-align: top;">ARR [10]<br>
1398 </td>
1399 <td style="vertical-align: top;"><br>
1400 </td>
1401 <td style="vertical-align: top;">TRK command queue /RO<br>
1402 </td>
1403 </tr><tr>
1404 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_2_2<br>
1405 </td>
1406 <td style="vertical-align: top;">VAR<br>
1407 </td>
1408 <td style="vertical-align: top;">30<br>
1409 </td>
1410 <td style="vertical-align: top;">TRK command queue /RO<br>
1411 </td>
1412 </tr><tr>
1413 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_2_2<br>
1414 </td>
1415 <td style="vertical-align: top;">ARR [10]<br>
1416 </td>
1417 <td style="vertical-align: top;"><br>
1418 </td>
1419 <td style="vertical-align: top;">TRK command queue /RO<br>
1420 </td>
1421 </tr><tr>
1422 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_2_3<br>
1423 </td>
1424 <td style="vertical-align: top;">VAR<br>
1425 </td>
1426 <td style="vertical-align: top;">30<br>
1427 </td>
1428 <td style="vertical-align: top;">TRK command queue /RO<br>
1429 </td>
1430 </tr><tr>
1431 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_2_3<br>
1432 </td>
1433 <td style="vertical-align: top;">ARR [10]<br>
1434 </td>
1435 <td style="vertical-align: top;"><br>
1436 </td>
1437 <td style="vertical-align: top;">TRK command queue /RO<br>
1438 </td>
1439 </tr><tr>
1440 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_2_4<br>
1441 </td>
1442 <td style="vertical-align: top;">VAR<br>
1443 </td>
1444 <td style="vertical-align: top;">30<br>
1445 </td>
1446 <td style="vertical-align: top;">TRK command queue /RO<br>
1447 </td>
1448 </tr><tr>
1449 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_2_4<br>
1450 </td>
1451 <td style="vertical-align: top;">ARR [10]<br>
1452 </td>
1453 <td style="vertical-align: top;"><br>
1454 </td>
1455 <td style="vertical-align: top;">TRK command queue /RO<br>
1456 </td>
1457 </tr><tr>
1458 <td style="vertical-align: top;">BUF_LEN_TRK_NUMBER_DSP_2_5<br>
1459 </td>
1460 <td style="vertical-align: top;">VAR<br>
1461 </td>
1462 <td style="vertical-align: top;">30<br>
1463 </td>
1464 <td style="vertical-align: top;">TRK command queue /RO<br>
1465 </td>
1466 </tr><tr>
1467 <td style="vertical-align: top;">BUF_TRK_NUMBER_DSP_2_5<br>
1468 </td>
1469 <td style="vertical-align: top;">ARR [10]<br>
1470 </td>
1471 <td style="vertical-align: top;"><br>
1472 </td>
1473 <td style="vertical-align: top;">TRK command queue /RO<br>
1474 </td>
1475 </tr><tr>
1476 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_COMP_0<br>
1477 </td>
1478 <td style="vertical-align: top;">VAR<br>
1479 </td>
1480 <td style="vertical-align: top;">10<br>
1481 </td>
1482 <td style="vertical-align: top;">TRK command queue /RO<br>
1483 </td>
1484 </tr><tr>
1485 <td style="vertical-align: top;">BUF_TRK_OPMODE_COMP_0<br>
1486 </td>
1487 <td style="vertical-align: top;">ARR [3]<br>
1488 </td>
1489 <td style="vertical-align: top;"><br>
1490 </td>
1491 <td style="vertical-align: top;">TRK command queue /RO<br>
1492 </td>
1493 </tr><tr>
1494 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_SPEC_0<br>
1495 </td>
1496 <td style="vertical-align: top;">VAR<br>
1497 </td>
1498 <td style="vertical-align: top;">10<br>
1499 </td>
1500 <td style="vertical-align: top;">TRK command queue /RO<br>
1501 </td>
1502 </tr><tr>
1503 <td style="vertical-align: top;">BUF_TRK_OPMODE_SPEC_0<br>
1504 </td>
1505 <td style="vertical-align: top;">ARR [3]<br>
1506 </td>
1507 <td style="vertical-align: top;"><br>
1508 </td>
1509 <td style="vertical-align: top;">TRK command queue /RO<br>
1510 </td>
1511 </tr><tr>
1512 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_COMP_1<br>
1513 </td>
1514 <td style="vertical-align: top;">VAR<br>
1515 </td>
1516 <td style="vertical-align: top;">10<br>
1517 </td>
1518 <td style="vertical-align: top;">TRK command queue /RO<br>
1519 </td>
1520 </tr><tr>
1521 <td style="vertical-align: top;">BUF_TRK_OPMODE_COMP_1<br>
1522 </td>
1523 <td style="vertical-align: top;">ARR [3]<br>
1524 </td>
1525 <td style="vertical-align: top;"><br>
1526 </td>
1527 <td style="vertical-align: top;">TRK command queue /RO<br>
1528 </td>
1529 </tr><tr>
1530 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_SPEC_1<br>
1531 </td>
1532 <td style="vertical-align: top;">VAR<br>
1533 </td>
1534 <td style="vertical-align: top;">10<br>
1535 </td>
1536 <td style="vertical-align: top;">TRK command queue /RO<br>
1537 </td>
1538 </tr><tr>
1539 <td style="vertical-align: top;">BUF_TRK_OPMODE_SPEC_1<br>
1540 </td>
1541 <td style="vertical-align: top;">ARR [3]<br>
1542 </td>
1543 <td style="vertical-align: top;"><br>
1544 </td>
1545 <td style="vertical-align: top;">TRK command queue /RO<br>
1546 </td>
1547 </tr><tr>
1548 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_COMP_2<br>
1549 </td>
1550 <td style="vertical-align: top;">VAR<br>
1551 </td>
1552 <td style="vertical-align: top;">10<br>
1553 </td>
1554 <td style="vertical-align: top;">TRK command queue /RO<br>
1555 </td>
1556 </tr><tr>
1557 <td style="vertical-align: top;">BUF_TRK_OPMODE_COMP_2<br>
1558 </td>
1559 <td style="vertical-align: top;">ARR [3]<br>
1560 </td>
1561 <td style="vertical-align: top;"><br>
1562 </td>
1563 <td style="vertical-align: top;">TRK command queue /RO<br>
1564 </td>
1565 </tr><tr>
1566 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_SPEC_2<br>
1567 </td>
1568 <td style="vertical-align: top;">VAR<br>
1569 </td>
1570 <td style="vertical-align: top;">10<br>
1571 </td>
1572 <td style="vertical-align: top;">TRK command queue /RO<br>
1573 </td>
1574 </tr><tr>
1575 <td style="vertical-align: top;">BUF_TRK_OPMODE_SPEC_2<br>
1576 </td>
1577 <td style="vertical-align: top;">ARR [3]<br>
1578 </td>
1579 <td style="vertical-align: top;"><br>
1580 </td>
1581 <td style="vertical-align: top;">TRK command queue /RO<br>
1582 </td>
1583 </tr><tr>
1584 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_COMP_3<br>
1585 </td>
1586 <td style="vertical-align: top;">VAR<br>
1587 </td>
1588 <td style="vertical-align: top;">10<br>
1589 </td>
1590 <td style="vertical-align: top;">TRK command queue /RO<br>
1591 </td>
1592 </tr><tr>
1593 <td style="vertical-align: top;">BUF_TRK_OPMODE_COMP_3<br>
1594 </td>
1595 <td style="vertical-align: top;">ARR [3]<br>
1596 </td>
1597 <td style="vertical-align: top;"><br>
1598 </td>
1599 <td style="vertical-align: top;">TRK command queue /RO<br>
1600 </td>
1601 </tr><tr>
1602 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_SPEC_3<br>
1603 </td>
1604 <td style="vertical-align: top;">VAR<br>
1605 </td>
1606 <td style="vertical-align: top;">10<br>
1607 </td>
1608 <td style="vertical-align: top;">TRK command queue /RO<br>
1609 </td>
1610 </tr><tr>
1611 <td style="vertical-align: top;">BUF_TRK_OPMODE_SPEC_3<br>
1612 </td>
1613 <td style="vertical-align: top;">ARR [3]<br>
1614 </td>
1615 <td style="vertical-align: top;"><br>
1616 </td>
1617 <td style="vertical-align: top;">TRK command queue /RO<br>
1618 </td>
1619 </tr><tr>
1620 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_COMP_4<br>
1621 </td>
1622 <td style="vertical-align: top;">VAR<br>
1623 </td>
1624 <td style="vertical-align: top;">10<br>
1625 </td>
1626 <td style="vertical-align: top;">TRK command queue /RO<br>
1627 </td>
1628 </tr><tr>
1629 <td style="vertical-align: top;">BUF_TRK_OPMODE_COMP_4<br>
1630 </td>
1631 <td style="vertical-align: top;">ARR [3]<br>
1632 </td>
1633 <td style="vertical-align: top;"><br>
1634 </td>
1635 <td style="vertical-align: top;">TRK command queue /RO<br>
1636 </td>
1637 </tr><tr>
1638 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_SPEC_4<br>
1639 </td>
1640 <td style="vertical-align: top;">VAR<br>
1641 </td>
1642 <td style="vertical-align: top;">10<br>
1643 </td>
1644 <td style="vertical-align: top;">TRK command queue /RO<br>
1645 </td>
1646 </tr><tr>
1647 <td style="vertical-align: top;">BUF_TRK_OPMODE_SPEC_4<br>
1648 </td>
1649 <td style="vertical-align: top;">ARR [3]<br>
1650 </td>
1651 <td style="vertical-align: top;"><br>
1652 </td>
1653 <td style="vertical-align: top;">TRK command queue /RO<br>
1654 </td>
1655 </tr><tr>
1656 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_COMP_5<br>
1657 </td>
1658 <td style="vertical-align: top;">VAR<br>
1659 </td>
1660 <td style="vertical-align: top;">10<br>
1661 </td>
1662 <td style="vertical-align: top;">TRK command queue /RO<br>
1663 </td>
1664 </tr><tr>
1665 <td style="vertical-align: top;">BUF_TRK_OPMODE_COMP_5<br>
1666 </td>
1667 <td style="vertical-align: top;">ARR [3]<br>
1668 </td>
1669 <td style="vertical-align: top;"><br>
1670 </td>
1671 <td style="vertical-align: top;">TRK command queue /RO<br>
1672 </td>
1673 </tr><tr>
1674 <td style="vertical-align: top;">BUF_LEN_TRK_OPMODE_SPEC_5<br>
1675 </td>
1676 <td style="vertical-align: top;">VAR<br>
1677 </td>
1678 <td style="vertical-align: top;">10<br>
1679 </td>
1680 <td style="vertical-align: top;">TRK command queue /RO<br>
1681 </td>
1682 </tr><tr>
1683 <td style="vertical-align: top;">BUF_TRK_OPMODE_SPEC_5<br>
1684 </td>
1685 <td style="vertical-align: top;">ARR [3]<br>
1686 </td>
1687 <td style="vertical-align: top;"><br>
1688 </td>
1689 <td style="vertical-align: top;">TRK command queue /RO<br>
1690 </td>
1691 </tr><tr>
1692 <td style="vertical-align: top;">S4_OK<br>
1693 </td>
1694 <td style="vertical-align: top;">VAR<br>
1695 </td>
1696 <td style="vertical-align: top;">1<br>
1697 </td>
1698 <td style="vertical-align: top;">S4 enable/disable /RO<br>
1699 </td>
1700 </tr><tr>
1701 <td style="vertical-align: top;">S4_TRH<br>
1702 </td>
1703 <td style="vertical-align: top;">VAR<br>
1704 </td>
1705 <td style="vertical-align: top;">16384<br>
1706 </td>
1707 <td style="vertical-align: top;">S4 command /RO<br>
1708 </td>
1709 </tr><tr>
1710 <td style="vertical-align: top;">S4_ATTEMPT<br>
1711 </td>
1712 <td style="vertical-align: top;">VAR<br>
1713 </td>
1714 <td style="vertical-align: top;">0<br>
1715 </td>
1716 <td style="vertical-align: top;">S4 force check /RO<br>
1717 </td>
1718 </tr><tr>
1719 <td style="vertical-align: top;">S4_WORKING<br>
1720 </td>
1721 <td style="vertical-align: top;">VAR<br>
1722 </td>
1723 <td style="vertical-align: top;">1<br>
1724 </td>
1725 <td style="vertical-align: top;">check if S4 is working or not /RO<br>
1726 </td>
1727 </tr><tr>
1728 <td style="vertical-align: top;">CAL_UPLOAD_CAL_FE_MASK<br>
1729 </td>
1730 <td style="vertical-align: top;">VAR<br>
1731 </td>
1732 <td style="vertical-align: top;">15<br>
1733 </td>
1734 <td style="vertical-align: top;">Defines the working read-out of calorimeter /RO<br>
1735 </td>
1736 </tr><tr>
1737 <td style="vertical-align: top;">CAL_UPLOAD_CAL_DSP_MASK<br>
1738 </td>
1739 <td style="vertical-align: top;">VAR<br>
1740 </td>
1741 <td style="vertical-align: top;">15<br>
1742 </td>
1743 <td style="vertical-align: top;">Defines the workings dsps of calorimeter /RO<br>
1744 </td>
1745 </tr><tr>
1746 <td style="vertical-align: top;">CAL_VCAL<br>
1747 </td>
1748 <td style="vertical-align: top;">VAR<br>
1749 </td>
1750 <td style="vertical-align: top;">32773<br>
1751 </td>
1752 <td style="vertical-align: top;">Variable modified by pulse calibration /RW<br>
1753 </td>
1754 </tr><tr>
1755 <td style="vertical-align: top;">CAL_CH<br>
1756 </td>
1757 <td style="vertical-align: top;">VAR<br>
1758 </td>
1759 <td style="vertical-align: top;">1<br>
1760 </td>
1761 <td style="vertical-align: top;">Variable modified by pulse calibration /RW<br>
1762 </td>
1763 </tr><tr>
1764 <td style="vertical-align: top;">CAL_TEMP<br>
1765 </td>
1766 <td style="vertical-align: top;">VAR<br>
1767 </td>
1768 <td style="vertical-align: top;">5<br>
1769 </td>
1770 <td style="vertical-align: top;">Maximum calorimeter temperature alarms /RO<br>
1771 </td>
1772 </tr><tr>
1773 <td style="vertical-align: top;">CAL_COUNT<br>
1774 </td>
1775 <td style="vertical-align: top;">ARR [4]<br>
1776 </td>
1777 <td style="vertical-align: top;"><br>
1778 </td>
1779 <td style="vertical-align: top;">defines the calorimeter read out repetitions /RO<br>
1780 </td>
1781 </tr><tr>
1782 <td style="vertical-align: top;">CAL_OK<br>
1783 </td>
1784 <td style="vertical-align: top;">VAR<br>
1785 </td>
1786 <td style="vertical-align: top;">1<br>
1787 </td>
1788 <td style="vertical-align: top;">calo ON_OFF in ACQ /RW<br>
1789 </td>
1790 </tr><tr>
1791 <td style="vertical-align: top;">CAL_CHECK_FE<br>
1792 </td>
1793 <td style="vertical-align: top;">VAR<br>
1794 </td>
1795 <td style="vertical-align: top;">0<br>
1796 </td>
1797 <td style="vertical-align: top;">calo check FE /RO<br>
1798 </td>
1799 </tr><tr>
1800 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I211<br>
1801 </td>
1802 <td style="vertical-align: top;">VAR<br>
1803 </td>
1804 <td style="vertical-align: top;">8<br>
1805 </td>
1806 <td style="vertical-align: top;">write fpga /RO<br>
1807 </td>
1808 </tr><tr>
1809 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I211<br>
1810 </td>
1811 <td style="vertical-align: top;">ARR [2]<br>
1812 </td>
1813 <td style="vertical-align: top;"><br>
1814 </td>
1815 <td style="vertical-align: top;">write fpga /RO<br>
1816 </td>
1817 </tr><tr>
1818 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I221<br>
1819 </td>
1820 <td style="vertical-align: top;">VAR<br>
1821 </td>
1822 <td style="vertical-align: top;">8<br>
1823 </td>
1824 <td style="vertical-align: top;">write fpga /RO<br>
1825 </td>
1826 </tr><tr>
1827 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I221<br>
1828 </td>
1829 <td style="vertical-align: top;">ARR [2]<br>
1830 </td>
1831 <td style="vertical-align: top;"><br>
1832 </td>
1833 <td style="vertical-align: top;">write fpga /RO<br>
1834 </td>
1835 </tr><tr>
1836 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I231<br>
1837 </td>
1838 <td style="vertical-align: top;">VAR<br>
1839 </td>
1840 <td style="vertical-align: top;">8<br>
1841 </td>
1842 <td style="vertical-align: top;">write fpga /RO<br>
1843 </td>
1844 </tr><tr>
1845 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I231<br>
1846 </td>
1847 <td style="vertical-align: top;">ARR [2]<br>
1848 </td>
1849 <td style="vertical-align: top;"><br>
1850 </td>
1851 <td style="vertical-align: top;">write fpga /RO<br>
1852 </td>
1853 </tr><tr>
1854 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_DSP_MEM_I41<br>
1855 </td>
1856 <td style="vertical-align: top;">VAR<br>
1857 </td>
1858 <td style="vertical-align: top;">4234<br>
1859 </td>
1860 <td style="vertical-align: top;">dsp prog i41 /R0<br>
1861 </td>
1862 </tr><tr>
1863 <td style="vertical-align: top;">BUF_CAL_WRITE_DSP_MEM_I41<br>
1864 </td>
1865 <td style="vertical-align: top;">ARR [3176]<br>
1866 </td>
1867 <td style="vertical-align: top;"><br>
1868 </td>
1869 <td style="vertical-align: top;">dsp prog i41 /R0<br>
1870 </td>
1871 </tr><tr>
1872 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_DSP_MEM_I42<br>
1873 </td>
1874 <td style="vertical-align: top;">VAR<br>
1875 </td>
1876 <td style="vertical-align: top;">3646<br>
1877 </td>
1878 <td style="vertical-align: top;">dsp prog i42 /RO<br>
1879 </td>
1880 </tr><tr>
1881 <td style="vertical-align: top;">BUF_CAL_WRITE_DSP_MEM_I42<br>
1882 </td>
1883 <td style="vertical-align: top;">ARR [2723]<br>
1884 </td>
1885 <td style="vertical-align: top;"><br>
1886 </td>
1887 <td style="vertical-align: top;">dsp prog i42 /RO<br>
1888 </td>
1889 </tr><tr>
1890 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_DSP_MEM_I43<br>
1891 </td>
1892 <td style="vertical-align: top;">VAR<br>
1893 </td>
1894 <td style="vertical-align: top;">14<br>
1895 </td>
1896 <td style="vertical-align: top;">dsp prog i43 /RO<br>
1897 </td>
1898 </tr><tr>
1899 <td style="vertical-align: top;">BUF_CAL_WRITE_DSP_MEM_I43<br>
1900 </td>
1901 <td style="vertical-align: top;">ARR [11]<br>
1902 </td>
1903 <td style="vertical-align: top;"><br>
1904 </td>
1905 <td style="vertical-align: top;">dsp prog i43 /RO<br>
1906 </td>
1907 </tr><tr>
1908 <td style="vertical-align: top;">BUF_LEN_CAL_READ_DSP_MEM_C31<br>
1909 </td>
1910 <td style="vertical-align: top;">VAR<br>
1911 </td>
1912 <td style="vertical-align: top;">10<br>
1913 </td>
1914 <td style="vertical-align: top;">dsp prog c31 /RO<br>
1915 </td>
1916 </tr><tr>
1917 <td style="vertical-align: top;">BUF_CAL_READ_DSP_MEM_C31<br>
1918 </td>
1919 <td style="vertical-align: top;">ARR [8]<br>
1920 </td>
1921 <td style="vertical-align: top;"><br>
1922 </td>
1923 <td style="vertical-align: top;">dsp prog c31 /RO<br>
1924 </td>
1925 </tr><tr>
1926 <td style="vertical-align: top;">BUF_LEN_CAL_READ_DSP_MEM_C32<br>
1927 </td>
1928 <td style="vertical-align: top;">VAR<br>
1929 </td>
1930 <td style="vertical-align: top;">10<br>
1931 </td>
1932 <td style="vertical-align: top;">dsp prog c32 /RO<br>
1933 </td>
1934 </tr><tr>
1935 <td style="vertical-align: top;">BUF_CAL_READ_DSP_MEM_C32<br>
1936 </td>
1937 <td style="vertical-align: top;">ARR [8]<br>
1938 </td>
1939 <td style="vertical-align: top;"><br>
1940 </td>
1941 <td style="vertical-align: top;">dsp prog c32 /RO<br>
1942 </td>
1943 </tr><tr>
1944 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I241_1<br>
1945 </td>
1946 <td style="vertical-align: top;">VAR<br>
1947 </td>
1948 <td style="vertical-align: top;">8<br>
1949 </td>
1950 <td style="vertical-align: top;">write fpga i241_1 /RO<br>
1951 </td>
1952 </tr><tr>
1953 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I241_1<br>
1954 </td>
1955 <td style="vertical-align: top;">ARR [2]<br>
1956 </td>
1957 <td style="vertical-align: top;"><br>
1958 </td>
1959 <td style="vertical-align: top;">write fpga i241_1 /RO<br>
1960 </td>
1961 </tr><tr>
1962 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I241_2<br>
1963 </td>
1964 <td style="vertical-align: top;">VAR<br>
1965 </td>
1966 <td style="vertical-align: top;">8<br>
1967 </td>
1968 <td style="vertical-align: top;">write fpga i241_2 /RO<br>
1969 </td>
1970 </tr><tr>
1971 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I241_2<br>
1972 </td>
1973 <td style="vertical-align: top;">ARR [2]<br>
1974 </td>
1975 <td style="vertical-align: top;"><br>
1976 </td>
1977 <td style="vertical-align: top;">write fpga i241_2 /RO<br>
1978 </td>
1979 </tr><tr>
1980 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I241_3<br>
1981 </td>
1982 <td style="vertical-align: top;">VAR<br>
1983 </td>
1984 <td style="vertical-align: top;">8<br>
1985 </td>
1986 <td style="vertical-align: top;">write fpga i241_3 /RO<br>
1987 </td>
1988 </tr><tr>
1989 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I241_3<br>
1990 </td>
1991 <td style="vertical-align: top;">ARR [2]<br>
1992 </td>
1993 <td style="vertical-align: top;"><br>
1994 </td>
1995 <td style="vertical-align: top;">write fpga i241_3 /RO<br>
1996 </td>
1997 </tr><tr>
1998 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I241_4<br>
1999 </td>
2000 <td style="vertical-align: top;">VAR<br>
2001 </td>
2002 <td style="vertical-align: top;">8<br>
2003 </td>
2004 <td style="vertical-align: top;">write fpga i241_4 /RO<br>
2005 </td>
2006 </tr><tr>
2007 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I241_4<br>
2008 </td>
2009 <td style="vertical-align: top;">ARR [2]<br>
2010 </td>
2011 <td style="vertical-align: top;"><br>
2012 </td>
2013 <td style="vertical-align: top;">write fpga i241_4 /RO<br>
2014 </td>
2015 </tr><tr>
2016 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I251_1<br>
2017 </td>
2018 <td style="vertical-align: top;">VAR<br>
2019 </td>
2020 <td style="vertical-align: top;">8<br>
2021 </td>
2022 <td style="vertical-align: top;">write fpga i251_1 /RO<br>
2023 </td>
2024 </tr><tr>
2025 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I251_1<br>
2026 </td>
2027 <td style="vertical-align: top;">ARR [2]<br>
2028 </td>
2029 <td style="vertical-align: top;"><br>
2030 </td>
2031 <td style="vertical-align: top;">write fpga i251_1 /RO<br>
2032 </td>
2033 </tr><tr>
2034 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I251_2<br>
2035 </td>
2036 <td style="vertical-align: top;">VAR<br>
2037 </td>
2038 <td style="vertical-align: top;">8<br>
2039 </td>
2040 <td style="vertical-align: top;">write fpga i251_2 /RO<br>
2041 </td>
2042 </tr><tr>
2043 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I251_2<br>
2044 </td>
2045 <td style="vertical-align: top;">ARR [2]<br>
2046 </td>
2047 <td style="vertical-align: top;"><br>
2048 </td>
2049 <td style="vertical-align: top;">write fpga i251_2 /RO<br>
2050 </td>
2051 </tr><tr>
2052 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I251_3<br>
2053 </td>
2054 <td style="vertical-align: top;">VAR<br>
2055 </td>
2056 <td style="vertical-align: top;">8<br>
2057 </td>
2058 <td style="vertical-align: top;">write fpga i251_3 /RO<br>
2059 </td>
2060 </tr><tr>
2061 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I251_3<br>
2062 </td>
2063 <td style="vertical-align: top;">ARR [2]<br>
2064 </td>
2065 <td style="vertical-align: top;"><br>
2066 </td>
2067 <td style="vertical-align: top;">write fpga i251_3 /RO<br>
2068 </td>
2069 </tr><tr>
2070 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I251_4<br>
2071 </td>
2072 <td style="vertical-align: top;">VAR<br>
2073 </td>
2074 <td style="vertical-align: top;">8<br>
2075 </td>
2076 <td style="vertical-align: top;">write fpga i251_4 /RO<br>
2077 </td>
2078 </tr><tr>
2079 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I251_4<br>
2080 </td>
2081 <td style="vertical-align: top;">ARR [2]<br>
2082 </td>
2083 <td style="vertical-align: top;"><br>
2084 </td>
2085 <td style="vertical-align: top;">write fpga i251_4 /RO<br>
2086 </td>
2087 </tr><tr>
2088 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I261_1<br>
2089 </td>
2090 <td style="vertical-align: top;">VAR<br>
2091 </td>
2092 <td style="vertical-align: top;">8<br>
2093 </td>
2094 <td style="vertical-align: top;">write fpga i261_1 /RO<br>
2095 </td>
2096 </tr><tr>
2097 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I261_1<br>
2098 </td>
2099 <td style="vertical-align: top;">ARR [2]<br>
2100 </td>
2101 <td style="vertical-align: top;"><br>
2102 </td>
2103 <td style="vertical-align: top;">write fpga i261_1 /RO<br>
2104 </td>
2105 </tr><tr>
2106 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I261_2<br>
2107 </td>
2108 <td style="vertical-align: top;">VAR<br>
2109 </td>
2110 <td style="vertical-align: top;">8<br>
2111 </td>
2112 <td style="vertical-align: top;">write fpga i261_2 /RO<br>
2113 </td>
2114 </tr><tr>
2115 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I261_2<br>
2116 </td>
2117 <td style="vertical-align: top;">ARR [2]<br>
2118 </td>
2119 <td style="vertical-align: top;"><br>
2120 </td>
2121 <td style="vertical-align: top;">write fpga i261_2 /RO<br>
2122 </td>
2123 </tr><tr>
2124 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I261_3<br>
2125 </td>
2126 <td style="vertical-align: top;">VAR<br>
2127 </td>
2128 <td style="vertical-align: top;">8<br>
2129 </td>
2130 <td style="vertical-align: top;">write fpga i261_3 /RO<br>
2131 </td>
2132 </tr><tr>
2133 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I261_3<br>
2134 </td>
2135 <td style="vertical-align: top;">ARR [2]<br>
2136 </td>
2137 <td style="vertical-align: top;"><br>
2138 </td>
2139 <td style="vertical-align: top;">write fpga i261_3 /RO<br>
2140 </td>
2141 </tr><tr>
2142 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I261_4<br>
2143 </td>
2144 <td style="vertical-align: top;">VAR<br>
2145 </td>
2146 <td style="vertical-align: top;">8<br>
2147 </td>
2148 <td style="vertical-align: top;">write fpga i261_4 /RO<br>
2149 </td>
2150 </tr><tr>
2151 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I261_4<br>
2152 </td>
2153 <td style="vertical-align: top;">ARR [2]<br>
2154 </td>
2155 <td style="vertical-align: top;"><br>
2156 </td>
2157 <td style="vertical-align: top;">write fpga i261_4 /RO<br>
2158 </td>
2159 </tr><tr>
2160 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I260_1<br>
2161 </td>
2162 <td style="vertical-align: top;">VAR<br>
2163 </td>
2164 <td style="vertical-align: top;">8<br>
2165 </td>
2166 <td style="vertical-align: top;">write fpga i260_1 /RO<br>
2167 </td>
2168 </tr><tr>
2169 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I260_1<br>
2170 </td>
2171 <td style="vertical-align: top;">ARR [2]<br>
2172 </td>
2173 <td style="vertical-align: top;"><br>
2174 </td>
2175 <td style="vertical-align: top;">write fpga i260_1 /RO<br>
2176 </td>
2177 </tr><tr>
2178 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I260_2<br>
2179 </td>
2180 <td style="vertical-align: top;">VAR<br>
2181 </td>
2182 <td style="vertical-align: top;">8<br>
2183 </td>
2184 <td style="vertical-align: top;">write fpga i260_2 /RO<br>
2185 </td>
2186 </tr><tr>
2187 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I260_2<br>
2188 </td>
2189 <td style="vertical-align: top;">ARR [2]<br>
2190 </td>
2191 <td style="vertical-align: top;"><br>
2192 </td>
2193 <td style="vertical-align: top;">write fpga i260_2 /RO<br>
2194 </td>
2195 </tr><tr>
2196 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I260_3<br>
2197 </td>
2198 <td style="vertical-align: top;">VAR<br>
2199 </td>
2200 <td style="vertical-align: top;">8<br>
2201 </td>
2202 <td style="vertical-align: top;">write fpga i260_3 /RO<br>
2203 </td>
2204 </tr><tr>
2205 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I260_3<br>
2206 </td>
2207 <td style="vertical-align: top;">ARR [2]<br>
2208 </td>
2209 <td style="vertical-align: top;"><br>
2210 </td>
2211 <td style="vertical-align: top;">write fpga i260_3 /RO<br>
2212 </td>
2213 </tr><tr>
2214 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I260_4<br>
2215 </td>
2216 <td style="vertical-align: top;">VAR<br>
2217 </td>
2218 <td style="vertical-align: top;">8<br>
2219 </td>
2220 <td style="vertical-align: top;">write fpga i260_4 /RO<br>
2221 </td>
2222 </tr><tr>
2223 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I260_4<br>
2224 </td>
2225 <td style="vertical-align: top;">ARR [2]<br>
2226 </td>
2227 <td style="vertical-align: top;"><br>
2228 </td>
2229 <td style="vertical-align: top;">write fpga i260_4 /RO<br>
2230 </td>
2231 </tr><tr>
2232 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I311_1<br>
2233 </td>
2234 <td style="vertical-align: top;">VAR<br>
2235 </td>
2236 <td style="vertical-align: top;">8<br>
2237 </td>
2238 <td style="vertical-align: top;">write fpga i311_1 /RO<br>
2239 </td>
2240 </tr><tr>
2241 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I311_1<br>
2242 </td>
2243 <td style="vertical-align: top;">ARR [2]<br>
2244 </td>
2245 <td style="vertical-align: top;"><br>
2246 </td>
2247 <td style="vertical-align: top;">write fpga i311_1 /RO<br>
2248 </td>
2249 </tr><tr>
2250 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I311_2<br>
2251 </td>
2252 <td style="vertical-align: top;">VAR<br>
2253 </td>
2254 <td style="vertical-align: top;">8<br>
2255 </td>
2256 <td style="vertical-align: top;">write fpga i311_2 /RO<br>
2257 </td>
2258 </tr><tr>
2259 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I311_2<br>
2260 </td>
2261 <td style="vertical-align: top;">ARR [2]<br>
2262 </td>
2263 <td style="vertical-align: top;"><br>
2264 </td>
2265 <td style="vertical-align: top;">write fpga i311_2 /RO<br>
2266 </td>
2267 </tr><tr>
2268 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I311_3<br>
2269 </td>
2270 <td style="vertical-align: top;">VAR<br>
2271 </td>
2272 <td style="vertical-align: top;">8<br>
2273 </td>
2274 <td style="vertical-align: top;">write fpga i311_3 /RO<br>
2275 </td>
2276 </tr><tr>
2277 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I311_3<br>
2278 </td>
2279 <td style="vertical-align: top;">ARR [2]<br>
2280 </td>
2281 <td style="vertical-align: top;"><br>
2282 </td>
2283 <td style="vertical-align: top;">write fpga i311_3 /RO<br>
2284 </td>
2285 </tr><tr>
2286 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I311_4<br>
2287 </td>
2288 <td style="vertical-align: top;">VAR<br>
2289 </td>
2290 <td style="vertical-align: top;">8<br>
2291 </td>
2292 <td style="vertical-align: top;">write fpga i311_4 /RO<br>
2293 </td>
2294 </tr><tr>
2295 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I311_4<br>
2296 </td>
2297 <td style="vertical-align: top;">ARR [2]<br>
2298 </td>
2299 <td style="vertical-align: top;"><br>
2300 </td>
2301 <td style="vertical-align: top;">write fpga i311_4 /RO<br>
2302 </td>
2303 </tr><tr>
2304 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I310_1<br>
2305 </td>
2306 <td style="vertical-align: top;">VAR<br>
2307 </td>
2308 <td style="vertical-align: top;">8<br>
2309 </td>
2310 <td style="vertical-align: top;">write fpga i310_1 /RO<br>
2311 </td>
2312 </tr><tr>
2313 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I310_1<br>
2314 </td>
2315 <td style="vertical-align: top;">ARR [2]<br>
2316 </td>
2317 <td style="vertical-align: top;"><br>
2318 </td>
2319 <td style="vertical-align: top;">write fpga i310_1 /RO<br>
2320 </td>
2321 </tr><tr>
2322 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I310_2<br>
2323 </td>
2324 <td style="vertical-align: top;">VAR<br>
2325 </td>
2326 <td style="vertical-align: top;">8<br>
2327 </td>
2328 <td style="vertical-align: top;">write fpga i310_2 /RO<br>
2329 </td>
2330 </tr><tr>
2331 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I310_2<br>
2332 </td>
2333 <td style="vertical-align: top;">ARR [2]<br>
2334 </td>
2335 <td style="vertical-align: top;"><br>
2336 </td>
2337 <td style="vertical-align: top;">write fpga i310_2 /RO<br>
2338 </td>
2339 </tr><tr>
2340 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I310_3<br>
2341 </td>
2342 <td style="vertical-align: top;">VAR<br>
2343 </td>
2344 <td style="vertical-align: top;">8<br>
2345 </td>
2346 <td style="vertical-align: top;">write fpga i310_3 /RO<br>
2347 </td>
2348 </tr><tr>
2349 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I310_3<br>
2350 </td>
2351 <td style="vertical-align: top;">ARR [2]<br>
2352 </td>
2353 <td style="vertical-align: top;"><br>
2354 </td>
2355 <td style="vertical-align: top;">write fpga i310_3 /RO<br>
2356 </td>
2357 </tr><tr>
2358 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I310_4<br>
2359 </td>
2360 <td style="vertical-align: top;">VAR<br>
2361 </td>
2362 <td style="vertical-align: top;">8<br>
2363 </td>
2364 <td style="vertical-align: top;">write fpga i310_4 /RO<br>
2365 </td>
2366 </tr><tr>
2367 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I310_4<br>
2368 </td>
2369 <td style="vertical-align: top;">ARR [2]<br>
2370 </td>
2371 <td style="vertical-align: top;"><br>
2372 </td>
2373 <td style="vertical-align: top;">write fpga i310_4 /RO<br>
2374 </td>
2375 </tr><tr>
2376 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I321<br>
2377 </td>
2378 <td style="vertical-align: top;">VAR<br>
2379 </td>
2380 <td style="vertical-align: top;">8<br>
2381 </td>
2382 <td style="vertical-align: top;">write fpga i321 /RO<br>
2383 </td>
2384 </tr><tr>
2385 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I321<br>
2386 </td>
2387 <td style="vertical-align: top;">ARR [2]<br>
2388 </td>
2389 <td style="vertical-align: top;"><br>
2390 </td>
2391 <td style="vertical-align: top;">write fpga i321 /RO<br>
2392 </td>
2393 </tr><tr>
2394 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I331_1<br>
2395 </td>
2396 <td style="vertical-align: top;">VAR<br>
2397 </td>
2398 <td style="vertical-align: top;">8<br>
2399 </td>
2400 <td style="vertical-align: top;">write fpga i331_1 /RO<br>
2401 </td>
2402 </tr><tr>
2403 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I331_1<br>
2404 </td>
2405 <td style="vertical-align: top;">ARR [2]<br>
2406 </td>
2407 <td style="vertical-align: top;"><br>
2408 </td>
2409 <td style="vertical-align: top;">write fpga i331_1 /RO<br>
2410 </td>
2411 </tr><tr>
2412 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I331_2<br>
2413 </td>
2414 <td style="vertical-align: top;">VAR<br>
2415 </td>
2416 <td style="vertical-align: top;">8<br>
2417 </td>
2418 <td style="vertical-align: top;">write fpga i331_2 /RO<br>
2419 </td>
2420 </tr><tr>
2421 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I331_2<br>
2422 </td>
2423 <td style="vertical-align: top;">ARR [2]<br>
2424 </td>
2425 <td style="vertical-align: top;"><br>
2426 </td>
2427 <td style="vertical-align: top;">write fpga i331_2 /RO<br>
2428 </td>
2429 </tr><tr>
2430 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I331_3<br>
2431 </td>
2432 <td style="vertical-align: top;">VAR<br>
2433 </td>
2434 <td style="vertical-align: top;">8<br>
2435 </td>
2436 <td style="vertical-align: top;">write fpga i331_3 /RO<br>
2437 </td>
2438 </tr><tr>
2439 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I331_3<br>
2440 </td>
2441 <td style="vertical-align: top;">ARR [2]<br>
2442 </td>
2443 <td style="vertical-align: top;"><br>
2444 </td>
2445 <td style="vertical-align: top;">write fpga i331_3 /RO<br>
2446 </td>
2447 </tr><tr>
2448 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I331_4<br>
2449 </td>
2450 <td style="vertical-align: top;">VAR<br>
2451 </td>
2452 <td style="vertical-align: top;">8<br>
2453 </td>
2454 <td style="vertical-align: top;">write fpga i331_4 /RO<br>
2455 </td>
2456 </tr><tr>
2457 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I331_4<br>
2458 </td>
2459 <td style="vertical-align: top;">ARR [2]<br>
2460 </td>
2461 <td style="vertical-align: top;"><br>
2462 </td>
2463 <td style="vertical-align: top;">write fpga i331_4 /RO<br>
2464 </td>
2465 </tr><tr>
2466 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_OFF<br>
2467 </td>
2468 <td style="vertical-align: top;">VAR<br>
2469 </td>
2470 <td style="vertical-align: top;">8<br>
2471 </td>
2472 <td style="vertical-align: top;">write fpga reg off /RO<br>
2473 </td>
2474 </tr><tr>
2475 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_OFF<br>
2476 </td>
2477 <td style="vertical-align: top;">ARR [2]<br>
2478 </td>
2479 <td style="vertical-align: top;"><br>
2480 </td>
2481 <td style="vertical-align: top;">write fpga reg off /RO<br>
2482 </td>
2483 </tr><tr>
2484 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I341_1<br>
2485 </td>
2486 <td style="vertical-align: top;">VAR<br>
2487 </td>
2488 <td style="vertical-align: top;">8<br>
2489 </td>
2490 <td style="vertical-align: top;">write fpga i341_1 /RO<br>
2491 </td>
2492 </tr><tr>
2493 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I341_1<br>
2494 </td>
2495 <td style="vertical-align: top;">ARR [2]<br>
2496 </td>
2497 <td style="vertical-align: top;"><br>
2498 </td>
2499 <td style="vertical-align: top;">write fpga i341_1 /RO<br>
2500 </td>
2501 </tr><tr>
2502 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I341_2<br>
2503 </td>
2504 <td style="vertical-align: top;">VAR<br>
2505 </td>
2506 <td style="vertical-align: top;">8<br>
2507 </td>
2508 <td style="vertical-align: top;">write fpga i341_2 /RO<br>
2509 </td>
2510 </tr><tr>
2511 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I341_2<br>
2512 </td>
2513 <td style="vertical-align: top;">ARR [2]<br>
2514 </td>
2515 <td style="vertical-align: top;"><br>
2516 </td>
2517 <td style="vertical-align: top;">write fpga i341_2 /RO<br>
2518 </td>
2519 </tr><tr>
2520 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I341_3<br>
2521 </td>
2522 <td style="vertical-align: top;">VAR<br>
2523 </td>
2524 <td style="vertical-align: top;">8<br>
2525 </td>
2526 <td style="vertical-align: top;">write fpga i341_3 /RO<br>
2527 </td>
2528 </tr><tr>
2529 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I341_3<br>
2530 </td>
2531 <td style="vertical-align: top;">ARR [2]<br>
2532 </td>
2533 <td style="vertical-align: top;"><br>
2534 </td>
2535 <td style="vertical-align: top;">write fpga i341_3 /RO<br>
2536 </td>
2537 </tr><tr>
2538 <td style="vertical-align: top;">BUF_LEN_CAL_WRITE_FPGA_REG_I341_4<br>
2539 </td>
2540 <td style="vertical-align: top;">VAR<br>
2541 </td>
2542 <td style="vertical-align: top;">8<br>
2543 </td>
2544 <td style="vertical-align: top;">write fpga i341_4 /RO<br>
2545 </td>
2546 </tr><tr>
2547 <td style="vertical-align: top;">BUF_CAL_WRITE_FPGA_REG_I341_4<br>
2548 </td>
2549 <td style="vertical-align: top;">ARR [2]<br>
2550 </td>
2551 <td style="vertical-align: top;"><br>
2552 </td>
2553 <td style="vertical-align: top;">write fpga i341_4 /RO<br>
2554 </td>
2555 </tr><tr>
2556 <td style="vertical-align: top;">AC_1_OK<br>
2557 </td>
2558 <td style="vertical-align: top;">VAR<br>
2559 </td>
2560 <td style="vertical-align: top;">1<br>
2561 </td>
2562 <td style="vertical-align: top;">AC ON_OFF in ACQ /RW<br>
2563 </td>
2564 </tr><tr>
2565 <td style="vertical-align: top;">AC_2_OK<br>
2566 </td>
2567 <td style="vertical-align: top;">VAR<br>
2568 </td>
2569 <td style="vertical-align: top;">1<br>
2570 </td>
2571 <td style="vertical-align: top;">AC ON_OFF in ACQ /RW<br>
2572 </td>
2573 </tr><tr>
2574 <td style="vertical-align: top;">AC_1_CHECK<br>
2575 </td>
2576 <td style="vertical-align: top;">VAR<br>
2577 </td>
2578 <td style="vertical-align: top;">0<br>
2579 </td>
2580 <td style="vertical-align: top;">AC check /RO<br>
2581 </td>
2582 </tr><tr>
2583 <td style="vertical-align: top;">AC_2_CHECK<br>
2584 </td>
2585 <td style="vertical-align: top;">VAR<br>
2586 </td>
2587 <td style="vertical-align: top;">0<br>
2588 </td>
2589 <td style="vertical-align: top;">AC check /RO<br>
2590 </td>
2591 </tr><tr>
2592 <td style="vertical-align: top;">AC_LOOP<br>
2593 </td>
2594 <td style="vertical-align: top;">VAR<br>
2595 </td>
2596 <td style="vertical-align: top;">3<br>
2597 </td>
2598 <td style="vertical-align: top;">AC max loop /RO<br>
2599 </td>
2600 </tr><tr>
2601 <td style="vertical-align: top;">AC_LOOP2<br>
2602 </td>
2603 <td style="vertical-align: top;">VAR<br>
2604 </td>
2605 <td style="vertical-align: top;">3<br>
2606 </td>
2607 <td style="vertical-align: top;">AC max loop 2 /RO<br>
2608 </td>
2609 </tr><tr>
2610 <td style="vertical-align: top;">BUF_LEN_AC_1_SET_DAQ<br>
2611 </td>
2612 <td style="vertical-align: top;">VAR<br>
2613 </td>
2614 <td style="vertical-align: top;">132<br>
2615 </td>
2616 <td style="vertical-align: top;">SET DAQ command /RO<br>
2617 </td>
2618 </tr><tr>
2619 <td style="vertical-align: top;">BUF_AC_1_SET_DAQ<br>
2620 </td>
2621 <td style="vertical-align: top;">ARR [35]<br>
2622 </td>
2623 <td style="vertical-align: top;"><br>
2624 </td>
2625 <td style="vertical-align: top;">SET DAQ command /RO<br>
2626 </td>
2627 </tr><tr>
2628 <td style="vertical-align: top;">BUF_LEN_AC_2_SET_DAQ<br>
2629 </td>
2630 <td style="vertical-align: top;">VAR<br>
2631 </td>
2632 <td style="vertical-align: top;">132<br>
2633 </td>
2634 <td style="vertical-align: top;">SET DAQ command /RO<br>
2635 </td>
2636 </tr><tr>
2637 <td style="vertical-align: top;">BUF_AC_2_SET_DAQ<br>
2638 </td>
2639 <td style="vertical-align: top;">ARR [35]<br>
2640 </td>
2641 <td style="vertical-align: top;"><br>
2642 </td>
2643 <td style="vertical-align: top;">SET DAQ command /RO<br>
2644 </td>
2645 </tr><tr>
2646 <td style="vertical-align: top;">BUF_LEN_AC_SEND_DSP_PROG1<br>
2647 </td>
2648 <td style="vertical-align: top;">VAR<br>
2649 </td>
2650 <td style="vertical-align: top;">17034<br>
2651 </td>
2652 <td style="vertical-align: top;">DSP Program 1 /RO<br>
2653 </td>
2654 </tr><tr>
2655 <td style="vertical-align: top;">BUF_AC_SEND_DSP_PROG1<br>
2656 </td>
2657 <td style="vertical-align: top;">ARR [5010]<br>
2658 </td>
2659 <td style="vertical-align: top;"><br>
2660 </td>
2661 <td style="vertical-align: top;">DSP Program 1 /RO<br>
2662 </td>
2663 </tr><tr>
2664 <td style="vertical-align: top;">BUF_LEN_AC_1_SEND_DSP_PROG2<br>
2665 </td>
2666 <td style="vertical-align: top;">VAR<br>
2667 </td>
2668 <td style="vertical-align: top;">11156<br>
2669 </td>
2670 <td style="vertical-align: top;"> /RO<br>
2671 </td>
2672 </tr><tr>
2673 <td style="vertical-align: top;">BUF_AC_1_SEND_DSP_PROG2<br>
2674 </td>
2675 <td style="vertical-align: top;">ARR [3800]<br>
2676 </td>
2677 <td style="vertical-align: top;"><br>
2678 </td>
2679 <td style="vertical-align: top;"> /RO<br>
2680 </td>
2681 </tr><tr>
2682 <td style="vertical-align: top;">BUF_LEN_AC_2_SEND_DSP_PROG2<br>
2683 </td>
2684 <td style="vertical-align: top;">VAR<br>
2685 </td>
2686 <td style="vertical-align: top;">11156<br>
2687 </td>
2688 <td style="vertical-align: top;"> /RO<br>
2689 </td>
2690 </tr><tr>
2691 <td style="vertical-align: top;">BUF_AC_2_SEND_DSP_PROG2<br>
2692 </td>
2693 <td style="vertical-align: top;">ARR [3800]<br>
2694 </td>
2695 <td style="vertical-align: top;"><br>
2696 </td>
2697 <td style="vertical-align: top;"> /RO<br>
2698 </td>
2699 </tr><tr>
2700 <td style="vertical-align: top;">BUF_LEN_AC_2_WRITE_REG<br>
2701 </td>
2702 <td style="vertical-align: top;">VAR<br>
2703 </td>
2704 <td style="vertical-align: top;">54<br>
2705 </td>
2706 <td style="vertical-align: top;">/RO<br>
2707 </td>
2708 </tr><tr>
2709 <td style="vertical-align: top;">BUF_AC_2_WRITE_REG<br>
2710 </td>
2711 <td style="vertical-align: top;">ARR [15]<br>
2712 </td>
2713 <td style="vertical-align: top;"><br>
2714 </td>
2715 <td style="vertical-align: top;">/RO<br>
2716 </td>
2717 </tr><tr>
2718 <td style="vertical-align: top;">BUF_LEN_AC_1_WRITE_REG<br>
2719 </td>
2720 <td style="vertical-align: top;">VAR<br>
2721 </td>
2722 <td style="vertical-align: top;">54<br>
2723 </td>
2724 <td style="vertical-align: top;">/RO<br>
2725 </td>
2726 </tr><tr>
2727 <td style="vertical-align: top;">BUF_AC_1_WRITE_REG<br>
2728 </td>
2729 <td style="vertical-align: top;">ARR [15]<br>
2730 </td>
2731 <td style="vertical-align: top;"><br>
2732 </td>
2733 <td style="vertical-align: top;">/RO<br>
2734 </td>
2735 </tr><tr>
2736 <td style="vertical-align: top;">BUF_LEN_AC_READ_DSP_MEM<br>
2737 </td>
2738 <td style="vertical-align: top;">VAR<br>
2739 </td>
2740 <td style="vertical-align: top;">10<br>
2741 </td>
2742 <td style="vertical-align: top;"> /RO<br>
2743 </td>
2744 </tr><tr>
2745 <td style="vertical-align: top;">BUF_AC_READ_DSP_MEM<br>
2746 </td>
2747 <td style="vertical-align: top;">ARR [3]<br>
2748 </td>
2749 <td style="vertical-align: top;"><br>
2750 </td>
2751 <td style="vertical-align: top;"> /RO<br>
2752 </td>
2753 </tr><tr>
2754 <td style="vertical-align: top;">BUF_LEN_TOF_WRITE_PMT_THR_1<br>
2755 </td>
2756 <td style="vertical-align: top;">VAR<br>
2757 </td>
2758 <td style="vertical-align: top;">7<br>
2759 </td>
2760 <td style="vertical-align: top;">TOF set THR front end 1 /RO<br>
2761 </td>
2762 </tr><tr>
2763 <td style="vertical-align: top;">BUF_TOF_WRITE_PMT_THR_1<br>
2764 </td>
2765 <td style="vertical-align: top;">ARR [2]<br>
2766 </td>
2767 <td style="vertical-align: top;"><br>
2768 </td>
2769 <td style="vertical-align: top;">TOF set THR front end 1 /RO<br>
2770 </td>
2771 </tr><tr>
2772 <td style="vertical-align: top;">BUF_LEN_TOF_WRITE_PMT_THR_2<br>
2773 </td>
2774 <td style="vertical-align: top;">VAR<br>
2775 </td>
2776 <td style="vertical-align: top;">7<br>
2777 </td>
2778 <td style="vertical-align: top;">TOF set THR front end 2 /RO<br>
2779 </td>
2780 </tr><tr>
2781 <td style="vertical-align: top;">BUF_TOF_WRITE_PMT_THR_2<br>
2782 </td>
2783 <td style="vertical-align: top;">ARR [2]<br>
2784 </td>
2785 <td style="vertical-align: top;"><br>
2786 </td>
2787 <td style="vertical-align: top;">TOF set THR front end 2 /RO<br>
2788 </td>
2789 </tr><tr>
2790 <td style="vertical-align: top;">BUF_LEN_TOF_WRITE_PMT_THR_3<br>
2791 </td>
2792 <td style="vertical-align: top;">VAR<br>
2793 </td>
2794 <td style="vertical-align: top;">7<br>
2795 </td>
2796 <td style="vertical-align: top;">TOF set THR front end 3 /RO<br>
2797 </td>
2798 </tr><tr>
2799 <td style="vertical-align: top;">BUF_TOF_WRITE_PMT_THR_3<br>
2800 </td>
2801 <td style="vertical-align: top;">ARR [2]<br>
2802 </td>
2803 <td style="vertical-align: top;"><br>
2804 </td>
2805 <td style="vertical-align: top;">TOF set THR front end 3 /RO<br>
2806 </td>
2807 </tr><tr>
2808 <td style="vertical-align: top;">BUF_LEN_TOF_WRITE_PMT_THR_4<br>
2809 </td>
2810 <td style="vertical-align: top;">VAR<br>
2811 </td>
2812 <td style="vertical-align: top;">7<br>
2813 </td>
2814 <td style="vertical-align: top;">TOF set THR front end 4 /RO<br>
2815 </td>
2816 </tr><tr>
2817 <td style="vertical-align: top;">BUF_TOF_WRITE_PMT_THR_4<br>
2818 </td>
2819 <td style="vertical-align: top;">ARR [2]<br>
2820 </td>
2821 <td style="vertical-align: top;"><br>
2822 </td>
2823 <td style="vertical-align: top;">TOF set THR front end 4 /RO<br>
2824 </td>
2825 </tr><tr>
2826 <td style="vertical-align: top;">BUF_LEN_TOF_WRITE_PMT_THR_5<br>
2827 </td>
2828 <td style="vertical-align: top;">VAR<br>
2829 </td>
2830 <td style="vertical-align: top;">7<br>
2831 </td>
2832 <td style="vertical-align: top;">TOF set THR front end 5 /RO<br>
2833 </td>
2834 </tr><tr>
2835 <td style="vertical-align: top;">BUF_TOF_WRITE_PMT_THR_5<br>
2836 </td>
2837 <td style="vertical-align: top;">ARR [2]<br>
2838 </td>
2839 <td style="vertical-align: top;"><br>
2840 </td>
2841 <td style="vertical-align: top;">TOF set THR front end 5 /RO<br>
2842 </td>
2843 </tr><tr>
2844 <td style="vertical-align: top;">BUF_LEN_TOF_WRITE_PMT_THR_6<br>
2845 </td>
2846 <td style="vertical-align: top;">VAR<br>
2847 </td>
2848 <td style="vertical-align: top;">7<br>
2849 </td>
2850 <td style="vertical-align: top;">TOF set THR front end 5 /RO<br>
2851 </td>
2852 </tr><tr>
2853 <td style="vertical-align: top;">BUF_TOF_WRITE_PMT_THR_6<br>
2854 </td>
2855 <td style="vertical-align: top;">ARR [2]<br>
2856 </td>
2857 <td style="vertical-align: top;"><br>
2858 </td>
2859 <td style="vertical-align: top;">TOF set THR front end 5 /RO<br>
2860 </td>
2861 </tr><tr>
2862 <td style="vertical-align: top;">TOF_OK<br>
2863 </td>
2864 <td style="vertical-align: top;">VAR<br>
2865 </td>
2866 <td style="vertical-align: top;">1<br>
2867 </td>
2868 <td style="vertical-align: top;">TOF ON_OFF in ACQ /RW<br>
2869 </td>
2870 </tr><tr>
2871 <td style="vertical-align: top;">TOF_PLAN<br>
2872 </td>
2873 <td style="vertical-align: top;">ARR [6]<br>
2874 </td>
2875 <td style="vertical-align: top;"><br>
2876 </td>
2877 <td style="vertical-align: top;">TOF Plans selectors /RO<br>
2878 </td>
2879 </tr><tr>
2880 <td style="vertical-align: top;">ND_OK<br>
2881 </td>
2882 <td style="vertical-align: top;">VAR<br>
2883 </td>
2884 <td style="vertical-align: top;">1<br>
2885 </td>
2886 <td style="vertical-align: top;">ND ON_OFF in ACQ /RW<br>
2887 </td>
2888 </tr><tr>
2889 <td style="vertical-align: top;">ND_ATTEMPT<br>
2890 </td>
2891 <td style="vertical-align: top;">VAR<br>
2892 </td>
2893 <td style="vertical-align: top;">0<br>
2894 </td>
2895 <td style="vertical-align: top;">Force ND in ACQ (1), unless ND_OK is FALSE /RO<br>
2896 </td>
2897 </tr><tr>
2898 <td style="vertical-align: top;">ND_CMDS<br>
2899 </td>
2900 <td style="vertical-align: top;">VAR<br>
2901 </td>
2902 <td style="vertical-align: top;">3<br>
2903 </td>
2904 <td style="vertical-align: top;">Force ND in ACQ, unless ND_OK is FALSE /RO<br>
2905 </td>
2906 </tr><tr>
2907 <td style="vertical-align: top;">PM_PERIODIC_DELAY<br>
2908 </td>
2909 <td style="vertical-align: top;">ARR [4]<br>
2910 </td>
2911 <td style="vertical-align: top;"><br>
2912 </td>
2913 <td style="vertical-align: top;">Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations, /RO<br>
2914 </td>
2915 </tr><tr>
2916 <td style="vertical-align: top;">SCM_TM_DO_CHECK_VALUES_FREQ<br>
2917 </td>
2918 <td style="vertical-align: top;">VAR<br>
2919 </td>
2920 <td style="vertical-align: top;">1<br>
2921 </td>
2922 <td style="vertical-align: top;">Do a Check on TM values every XXX Number of cyc acq done /RO<br>
2923 </td>
2924 </tr><tr>
2925 <td style="vertical-align: top;">POWER_KHB<br>
2926 </td>
2927 <td style="vertical-align: top;">VAR<br>
2928 </td>
2929 <td style="vertical-align: top;">0<br>
2930 </td>
2931 <td style="vertical-align: top;">Select KHB board 0==>HOT else COLD<br>
2932 </td>
2933 </tr><tr>
2934 <td style="vertical-align: top;">PSB_TRB_S9004_ALL_ON_DELAY<br>
2935 </td>
2936 <td style="vertical-align: top;">VAR<br>
2937 </td>
2938 <td style="vertical-align: top;">1000<br>
2939 </td>
2940 <td style="vertical-align: top;">milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on) /RO<br>
2941 </td>
2942 </tr><tr>
2943 <td style="vertical-align: top;">PSB_TRB_BIAS_WAIT<br>
2944 </td>
2945 <td style="vertical-align: top;">VAR<br>
2946 </td>
2947 <td style="vertical-align: top;">3000<br>
2948 </td>
2949 <td style="vertical-align: top;">wait between bias TRB switch on/off /RO<br>
2950 </td>
2951 </tr><tr>
2952 <td style="vertical-align: top;">PSB_COMMANDS<br>
2953 </td>
2954 <td style="vertical-align: top;">ARR [29]<br>
2955 </td>
2956 <td style="vertical-align: top;"><br>
2957 </td>
2958 <td style="vertical-align: top;">Command for PSB /RO<br>
2959 </td>
2960 </tr><tr>
2961 <td style="vertical-align: top;">PSB_CALO_FE_ON<br>
2962 </td>
2963 <td style="vertical-align: top;">ARR [4]<br>
2964 </td>
2965 <td style="vertical-align: top;"><br>
2966 </td>
2967 <td style="vertical-align: top;">Command for PSB /RO<br>
2968 </td>
2969 </tr><tr>
2970 <td style="vertical-align: top;">PSB_CALO_FE_OFF<br>
2971 </td>
2972 <td style="vertical-align: top;">ARR [4]<br>
2973 </td>
2974 <td style="vertical-align: top;"><br>
2975 </td>
2976 <td style="vertical-align: top;">Command for PSB /RO<br>
2977 </td>
2978 </tr><tr>
2979 <td style="vertical-align: top;">PSB_CALO_FE<br>
2980 </td>
2981 <td style="vertical-align: top;">ARR [4]<br>
2982 </td>
2983 <td style="vertical-align: top;"><br>
2984 </td>
2985 <td style="vertical-align: top;">Command for PSB /RO<br>
2986 </td>
2987 </tr><tr>
2988 <td style="vertical-align: top;">PSB_CALOFE_DELAY<br>
2989 </td>
2990 <td style="vertical-align: top;">VAR<br>
2991 </td>
2992 <td style="vertical-align: top;">1000<br>
2993 </td>
2994 <td style="vertical-align: top;">Delay before power on CALO 5.7 /RO<br>
2995 </td>
2996 </tr><tr>
2997 <td style="vertical-align: top;">HV_OK<br>
2998 </td>
2999 <td style="vertical-align: top;">VAR<br>
3000 </td>
3001 <td style="vertical-align: top;">1<br>
3002 </td>
3003 <td style="vertical-align: top;">call HV settings after TRB setting at start-up /RO<br>
3004 </td>
3005 </tr><tr>
3006 <td style="vertical-align: top;">HVB_COMMANDS<br>
3007 </td>
3008 <td style="vertical-align: top;">ARR [12]<br>
3009 </td>
3010 <td style="vertical-align: top;"><br>
3011 </td>
3012 <td style="vertical-align: top;">Command for HVB /RO<br>
3013 </td>
3014 </tr><tr>
3015 <td style="vertical-align: top;">TSB_BOARD_OK<br>
3016 </td>
3017 <td style="vertical-align: top;">ARR [2]<br>
3018 </td>
3019 <td style="vertical-align: top;"><br>
3020 </td>
3021 <td style="vertical-align: top;">User TSB Board no 0/1 flags /RO<br>
3022 </td>
3023 </tr><tr>
3024 <td style="vertical-align: top;">TSB_T_OK<br>
3025 </td>
3026 <td style="vertical-align: top;">VAR<br>
3027 </td>
3028 <td style="vertical-align: top;">1<br>
3029 </td>
3030 <td style="vertical-align: top;">Do TSB Temperature check /RO<br>
3031 </td>
3032 </tr><tr>
3033 <td style="vertical-align: top;">TSB_B_OK<br>
3034 </td>
3035 <td style="vertical-align: top;">VAR<br>
3036 </td>
3037 <td style="vertical-align: top;">1<br>
3038 </td>
3039 <td style="vertical-align: top;">Do B-field TSB check /RO<br>
3040 </td>
3041 </tr><tr>
3042 <td style="vertical-align: top;">ALLPAGEAVAIL_ATTEMPT<br>
3043 </td>
3044 <td style="vertical-align: top;">VAR<br>
3045 </td>
3046 <td style="vertical-align: top;">50<br>
3047 </td>
3048 <td style="vertical-align: top;">ATTEMP TO ALLPAGE AVAILABLE<br>
3049 </td>
3050 </tr> </tbody>
3051 </table>
3052 <br>
3053 </body>
3054 </html>
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