Data/compilationInfo/PRH_ParamHandler_INFN_auto.arr_mm.info

0 LOG_MASK 113 {LU_DEFAULT_MASK} "log level mask for each module /RO"
1 THERM_LOW 16 {93,93,93,93,93,93,93,93,93,93,93,93,84,84,93,93} "Thermistor low limit /RO"
2 THERM_HIGH 16 {123,123,123,123,123,123,123,123,123,123,123,123,123,123,123,123} "Thermistor high limit /RO"
5 WS_1_SETTING 5 {720000,2160000,2700000,5490000,6390000} "Define the Working Schedule #1 values in ms /RO"
6 RM_RATE_METER_S1_TRH 2 {2000,1600} "Rate meter s1  register TRH.used to toggle A/B mode in WS3 mode. the index of the array is related to the current ACQ mode (0=A to B,1=B to A) /RO"
7 PWR_IPM_CONF 6 {1,1,1,1,1,1} "IMP desired configuration for initial poweron 6 bitmask /RO"
8 PWR_VOLTAGE_IPM_RANGE_ON_MAX 6 {0xd4,0xd4,0xd4,0xd4,0xd4,0xd4} "ADC min voltage values if ON /RO"
9 PWR_VOLTAGE_IPM_RANGE_ON_MIN 6 {0x9e,0x9e,0x9e,0x9e,0x9e,0x9e} "ADC min voltage values if ON /RO"
10 PWR_VOLTAGE_IPM_RANGE_OFF_MAX 6 {0x20,0x20,0x20,0x20,0x20,0x20} "ADC min voltage values if OFF /RO"
11 PWR_VOLTAGE_IPM_RANGE_OFF_MIN 6 {   0,   0,   0,   0,   0,   0} "ADC min voltage values if OFF /RO"
12 TM_FILTER_OPERATION 78 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} "low level telemetry filter operation: 0->apply no filter 1->set value 2->ORed mask 3->ANDed mask /RO"
13 TM_FILTER_VALUE 78 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} "low level telemetry filted values /RO"
14 BUF_TB_SET_ALARM_MASK 2 {0x20000283,0x64FFFF24} "TRG queue"
15 BUF_TB_SET_PMT_MASK 3 {0x30000601,0xD0FFFFFF,0xFFFFFF48} "TRG queue"
16 BUF_TB_SET_S4_CAL_MASK 2 {0x20000181,0x55FFF300} "TRG queue"
17 BUF_TB_SET_BUSY_MASK_IDAQ_HOT 5 {0x20000382,0x76800000,0x0B000000} " "
18 BUF_TB_SET_BUSY_MASK_IDAQ_COLD 5 {0x20000382,0x76400000,0x86000000} " "
19 TRK_LOAD_PRG 2 {3,3} "The way the DSP program is loaded /RO"
21 BUF_TRK_TRAILER_PRG_0 3 {0x79000000} "TRK DSP Program Trailer for DSP 0 /RO"
22 BUF_TRK_TRAILER_PRG_1 3 {0x9A000000} "TRK DSP Program Trailer for DSP 1 /RO"
23 BUF_TRK_TRAILER_PRG_2 3 {0xB8000000} "TRK DSP Program Trailer for DSP 2 /RO"
24 BUF_TRK_TRAILER_PRG_3 3 {0x5B000000} "TRK DSP Program Trailer for DSP 3 /RO"
25 BUF_TRK_TRAILER_PRG_4 3 {0xFC000000} "TRK DSP Program Trailer for DSP 4 /RO"
26 BUF_TRK_TRAILER_PRG_5 3 {0x1F000000} "TRK DSP Program Trailer for DSP 5 /RO"
27 BUF_TRK_NUMBER_DSP_1_0 10 {0x001B01C7,0x00730200,0x0C000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07940000} "TRK command queue /RO"
28 BUF_TRK_NUMBER_DSP_1_1 10 {0x001B11B7,0x00730200,0x0A000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07210000} "TRK command queue /RO"
29 BUF_TRK_NUMBER_DSP_1_2 10 {0x001B2127,0x00730200,0x08000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07CB0000} "TRK command queue /RO"
30 BUF_TRK_NUMBER_DSP_1_3 10 {0x001B3157,0x00730200,0x04000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07C30000} "TRK command queue /RO"
31 BUF_TRK_NUMBER_DSP_1_4 10 {0x001B4100,0x00730200,0x06000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07A50000} "TRK command queue /RO"
32 BUF_TRK_NUMBER_DSP_1_5 10 {0x001B5170,0x00730200,0x02000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x079F0000} "TRK command queue /RO"
33 BUF_TRK_NUMBER_DSP_2_0 10 {0x001B01C7,0x00730200,0x0B000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07C60000} "TRK command queue /RO"
34 BUF_TRK_NUMBER_DSP_2_1 10 {0x001B11B7,0x00730200,0x09000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x076A0000} "TRK command queue /RO"
35 BUF_TRK_NUMBER_DSP_2_2 10 {0x001B2127,0x00730200,0x07000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07AB0000} "TRK command queue /RO"
36 BUF_TRK_NUMBER_DSP_2_3 10 {0x001B3157,0x00730200,0x03000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07910000} "TRK command queue /RO"
37 BUF_TRK_NUMBER_DSP_2_4 10 {0x001B4100,0x00730200,0x05000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07EE0000} "TRK command queue /RO"
38 BUF_TRK_NUMBER_DSP_2_5 10 {0x001B5170,0x00730200,0x01000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07D40000} "TRK command queue /RO"
39 BUF_TRK_OPMODE_COMP_0 3 {0x0007016C,0x00730100,0x0A6F0000} "TRK command queue /RO"
40 BUF_TRK_OPMODE_SPEC_0 3 {0x0007016C,0x00730100,0x08610000} "TRK command queue /RO"
41 BUF_TRK_OPMODE_COMP_1 3 {0x0007111C,0x00730100,0x0AF10000} "TRK command queue /RO"
42 BUF_TRK_OPMODE_SPEC_1 3 {0x0007111C,0x00730100,0x08FF0000} "TRK command queue /RO"
43 BUF_TRK_OPMODE_COMP_2 3 {0x0007218C,0x00730100,0x0A540000} "TRK command queue /RO"
44 BUF_TRK_OPMODE_SPEC_2 3 {0x0007218C,0x00730100,0x085A0000} "TRK command queue /RO"
45 BUF_TRK_OPMODE_COMP_3 3 {0x000731FC,0x00730100,0x0ACA0000} "TRK command queue /RO"
46 BUF_TRK_OPMODE_SPEC_3 3 {0x000731FC,0x00730100,0x08C40000} "TRK command queue /RO"
47 BUF_TRK_OPMODE_COMP_4 3 {0x000741AB,0x00730100,0x0A190000} "TRK command queue /RO"
48 BUF_TRK_OPMODE_SPEC_4 3 {0x000741AB,0x00730100,0x08170000} "TRK command queue /RO"
49 BUF_TRK_OPMODE_COMP_5 3 {0x000751DB,0x00730100,0x0A870000} "TRK command queue /RO"
50 BUF_TRK_OPMODE_SPEC_5 3 {0x000751DB,0x00730100,0x08890000} "TRK command queue /RO"
51 CAL_COUNT 4 {
0x0003,
0x0003,
0x0003,
0x0003
} "defines the calorimeter read out repetitions /RO"
52 BUF_CAL_WRITE_FPGA_REG_I211 2 {0x4D230000,0x0001D214} "write fpga /RO"
53 BUF_CAL_WRITE_FPGA_REG_I221 2 {0x4D230001,0x0000F505} "write fpga /RO"
54 BUF_CAL_WRITE_FPGA_REG_I231 2 {0x4D230003,0xFFFF866A} "write fpga /RO"
57 BUF_CAL_WRITE_DSP_MEM_I43 11 {0x8E638000,0x00000002,0x1803000F,0xBA0E0000} "dsp prog i43 /RO"
58 BUF_CAL_READ_DSP_MEM_C31 8 {0xA7C80000,0x14001214,0x42BB0000} "dsp prog c31 /RO"
59 BUF_CAL_READ_DSP_MEM_C32 8 {0xA7C80000,0x400B0420,0xD2820000} "dsp prog c32 /RO"
60 BUF_CAL_WRITE_FPGA_REG_I241_1 2 {0x4D230004,0x0FFF103B} "write fpga i241_1 /RO"
61 BUF_CAL_WRITE_FPGA_REG_I241_2 2 {0x4D230004,0x0FFF103B} "write fpga i241_2 /RO"
62 BUF_CAL_WRITE_FPGA_REG_I241_3 2 {0x4D230004,0x0FEE122B} "write fpga i241_3 /RO"
63 BUF_CAL_WRITE_FPGA_REG_I241_4 2 {0x4D230004,0x0BFFDCFF} "write fpga i241_4 /RO"
64 BUF_CAL_WRITE_FPGA_REG_I251_1 2 {0x4D230005,0x007FA6BD} "write fpga i251_1 /RO"
65 BUF_CAL_WRITE_FPGA_REG_I251_2 2 {0x4D230005,0x007FA6BD} "write fpga i251_2 /RO"
66 BUF_CAL_WRITE_FPGA_REG_I251_3 2 {0x4D230005,0x007FA6BD} "write fpga i251_3 /RO"
67 BUF_CAL_WRITE_FPGA_REG_I251_4 2 {0x4D230005,0x007FA6BD} "write fpga i251_4 /RO"
68 BUF_CAL_WRITE_FPGA_REG_I261_1 2 {0x4D230002,0x0D55D059} "write fpga i261_1 /RO"
69 BUF_CAL_WRITE_FPGA_REG_I261_2 2 {0x4D230002,0x0D55D059} "write fpga i261_2 /RO"
70 BUF_CAL_WRITE_FPGA_REG_I261_3 2 {0x4D230002,0x0D55D059} "write fpga i261_3 /RO"
71 BUF_CAL_WRITE_FPGA_REG_I261_4 2 {0x4D230002,0x0D55D059} "write fpga i261_4 /RO"
72 BUF_CAL_WRITE_FPGA_REG_I260_1 2 {0x4D230002,0x055559F0} "write fpga i260_1 /RO"
73 BUF_CAL_WRITE_FPGA_REG_I260_2 2 {0x4D230002,0x055559F0} "write fpga i260_2 /RO"
74 BUF_CAL_WRITE_FPGA_REG_I260_3 2 {0x4D230002,0x055559F0} "write fpga i260_3 /RO"
75 BUF_CAL_WRITE_FPGA_REG_I260_4 2 {0x4D230002,0x055559F0} "write fpga i260_4 /RO"
76 BUF_CAL_WRITE_FPGA_REG_I311_1 2 {0x4D230002,0x0FFFA29B} "write fpga i311_1 /RO"
77 BUF_CAL_WRITE_FPGA_REG_I311_2 2 {0x4D230002,0x0FFFA29B} "write fpga i311_2 /RO"
78 BUF_CAL_WRITE_FPGA_REG_I311_3 2 {0x4D230002,0x0FFFA29B} "write fpga i311_3 /RO"
79 BUF_CAL_WRITE_FPGA_REG_I311_4 2 {0x4D230002,0x0FFFA29B} "write fpga i311_4 /RO"
80 BUF_CAL_WRITE_FPGA_REG_I310_1 2 {0x4D230002,0x07FF2B32} "write fpga i310_1 /RO"
81 BUF_CAL_WRITE_FPGA_REG_I310_2 2 {0x4D230002,0x07FF2B32} "write fpga i310_2 /RO"
82 BUF_CAL_WRITE_FPGA_REG_I310_3 2 {0x4D230002,0x07FF2B32} "write fpga i310_3 /RO"
83 BUF_CAL_WRITE_FPGA_REG_I310_4 2 {0x4D230002,0x07FF2B32} "write fpga i310_4 /RO"
84 BUF_CAL_WRITE_FPGA_REG_I321 2 {0x4D230000,0x8001C98C} "write fpga i321 /RO"
85 BUF_CAL_WRITE_FPGA_REG_I331_1 2 {0x4D230006,0x07FFF7F2} "write fpga i331_1 /RO"
86 BUF_CAL_WRITE_FPGA_REG_I331_2 2 {0x4D230006,0x07FFF7F2} "write fpga i331_2 /RO"
87 BUF_CAL_WRITE_FPGA_REG_I331_3 2 {0x4D230006,0x07FFF7F2} "write fpga i331_3 /RO"
88 BUF_CAL_WRITE_FPGA_REG_I331_4 2 {0x4D230006,0x07FFF7F2} "write fpga i331_4 /RO"
89 BUF_CAL_WRITE_FPGA_REG_OFF 2 {0x4D230002,0x0000AC55} "write fpga reg off /RO"
90 BUF_CAL_WRITE_FPGA_REG_I341_1 2 {0x4D230004,0x0FFF103B} "write fpga i341_1 /RO"
91 BUF_CAL_WRITE_FPGA_REG_I341_2 2 {0x4D230004,0x0FFF103B} "write fpga i341_2 /RO"
92 BUF_CAL_WRITE_FPGA_REG_I341_3 2 {0x4D230004,0x0FEE122B} "write fpga i341_3 /RO"
93 BUF_CAL_WRITE_FPGA_REG_I341_4 2 {0x4D230004,0x0BFFDCFF} "write fpga i341_4 /RO"
94 BUF_AC_1_SET_DAQ 35 {0x008A0000,0x000EFFFF,0xFFFF0001,0x0023FFFF,0xFFFF0002,0x0021FFFF,0xFFFF0003,0x0021FFFF,0xFFFF0004,0x0018FFFF,0xFFFF0005,0x002DFFFF,0xFFFF0006,0x0020FFFF,0xFFFF0007,0x0020FFFF,0xFFFF0008,0x0012FFFF,0xFFFF0009,0x0019FFFF,0xFFFF000A,0x001BFFFF,0xFFFF000B,0x001BFFFF,0xFFFF000C,0x0014FFFF,0xFFFF000D,0x0043FFFF,0xFFFF000E,0x0023FFFF,0xFFFF000F,0x0023FFFF,0xFFFF0D95} "SET DAQ command /RO"
95 BUF_AC_2_SET_DAQ 35 {0x008A0000,0x0020FFFF,0xFFFF0001,0x001BFFFF,0xFFFF0002,0x003AFFFF,0xFFFF0003,0x003AFFFF,0xFFFF0004,0x0015FFFF,0xFFFF0005,0x001CFFFF,0xFFFF0006,0x0014FFFF,0xFFFF0007,0x0014FFFF,0xFFFF0008,0x001CFFFF,0xFFFF0009,0x0039FFFF,0xFFFF000A,0x0010FFFF,0xFFFF000B,0x0010FFFF,0xFFFF000C,0x0019FFFF,0xFFFF000D,0x0012FFFF,0xFFFF000E,0x001AFFFF,0xFFFF000F,0x001AFFFF,0xFFFFAE20} "SET DAQ command /RO"
99 BUF_AC_2_WRITE_REG 15 {0x00890008,0xFFFF0040,0xACACFFFF,0x0041AC22,0xFFFF0044,0xFE00FFFF,0x00450000,0xFFFF0046,0xFFFFFFFF,0x00470040,0xFFFF0048,0xFFFFFFFF,0x0049FFFF,0x442B0000} "/RO"
100 BUF_AC_1_WRITE_REG 15 {0x00890008,0xFFFF0040,0xACACFFFF,0x0041AC11,0xFFFF0044,0xFE00FFFF,0x0045000F,0xFFFF0046,0xFFFFFFFF,0x00470040,0xFFFF0048,0xFFFFFFFF,0x0049FFFF,0x42D80000} "/RO"
101 BUF_AC_READ_DSP_MEM 3 {0x00804100,0x80002040,0x17530000} " /RO"
102 BUF_TOF_WRITE_PMT_THR_1 2 {0xB0C40A0A,0x0707FC00} "TOF set THR front end 1 /RO"
103 BUF_TOF_WRITE_PMT_THR_2 2 {0xB1C40707,0x0707BA00} "TOF set THR front end 2 /RO"
104 BUF_TOF_WRITE_PMT_THR_3 2 {0xB2C40707,0x0707C100} "TOF set THR front end 3 /RO"
105 BUF_TOF_WRITE_PMT_THR_4 2 {0xB3C40707,0x0707E800} "TOF set THR front end 4 /RO"
106 BUF_TOF_WRITE_PMT_THR_5 2 {0xB4C40707,0x07073700} "TOF set THR front end 5 /RO"
107 BUF_TOF_WRITE_PMT_THR_6 2 {0xB5C40707,0x07071E00} "TOF set THR front end 5 /RO"
108 TOF_PLAN 6 {1,1,1,1,1,1} "TOF Plans selectors /RO"
109 PM_PERIODIC_DELAY 4 
{
1000, 
10000,
10000,
1000*24*60*60
} "Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations, /RO"
110 PSB_COMMANDS 29 {
0x00C5,
0x01B6,
0x02D0,
0x05C5,
0x05A5,
0x0500,
0x0500,
0x06C3,
0x07D0,
0x08EC,
0x09FF,
0x0AF9,
0x0B8A,
0x0C9F,
0x0E8A,
0x0F99,
0x10AE,
0x121E,
0x12DB,
0x121E,
0x14DD,
0x15CE,
0x17DB,
0x18E7,
0x19F4,
0x03c3,
0x04d6,
0x0dec,
0x0F3C
} "Command for PSB /RO"
111 PSB_CALO_FE_ON 4 {
0x1AF2,
0x1BE1,
0x1CF4,
0x1DE7
} "Command for PSB /RO"
112 PSB_CALO_FE_OFF 4 {
0x1A37,
0x1B24,
0x1C31,
0x1D22
} "Command for PSB /RO"
113 PSB_CALO_FE 4 {
0x1AF2,
0x1BE1,
0x1CF4,
0x1DE7
} "Command for PSB /RO"
114 HVB_COMMANDS 12 {
0xC387,
0xC78F,
0xCB16,
0xCF9F,
0xD2A5,
0xD7AF,
0xDBB7,
0xDFBF,
0xE3C7,
0xE6CD,
0xEBD7,
0xEEDD
} "Command for HVB /RO"
115 TSB_BOARD_OK 2 {1,0} "User TSB Board no 0/1 flags /RO"
1	kusanagi	1.1	0 LOG_MASK 113 {LU_DEFAULT_MASK} "log level mask for each module /RO"
2			1 THERM_LOW 16 {93,93,93,93,93,93,93,93,93,93,93,93,84,84,93,93} "Thermistor low limit /RO"
3			2 THERM_HIGH 16 {123,123,123,123,123,123,123,123,123,123,123,123,123,123,123,123} "Thermistor high limit /RO"
4			5 WS_1_SETTING 5 {720000,2160000,2700000,5490000,6390000} "Define the Working Schedule #1 values in ms /RO"
5			6 RM_RATE_METER_S1_TRH 2 {2000,1600} "Rate meter s1 register TRH.used to toggle A/B mode in WS3 mode. the index of the array is related to the current ACQ mode (0=A to B,1=B to A) /RO"
6			7 PWR_IPM_CONF 6 {1,1,1,1,1,1} "IMP desired configuration for initial poweron 6 bitmask /RO"
7			8 PWR_VOLTAGE_IPM_RANGE_ON_MAX 6 {0xd4,0xd4,0xd4,0xd4,0xd4,0xd4} "ADC min voltage values if ON /RO"
8			9 PWR_VOLTAGE_IPM_RANGE_ON_MIN 6 {0x9e,0x9e,0x9e,0x9e,0x9e,0x9e} "ADC min voltage values if ON /RO"
9			10 PWR_VOLTAGE_IPM_RANGE_OFF_MAX 6 {0x20,0x20,0x20,0x20,0x20,0x20} "ADC min voltage values if OFF /RO"
10			11 PWR_VOLTAGE_IPM_RANGE_OFF_MIN 6 { 0, 0, 0, 0, 0, 0} "ADC min voltage values if OFF /RO"
11			12 TM_FILTER_OPERATION 78 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} "low level telemetry filter operation: 0->apply no filter 1->set value 2->ORed mask 3->ANDed mask /RO"
12			13 TM_FILTER_VALUE 78 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} "low level telemetry filted values /RO"
13			14 BUF_TB_SET_ALARM_MASK 2 {0x20000283,0x64FFFF24} "TRG queue"
14			15 BUF_TB_SET_PMT_MASK 3 {0x30000601,0xD0FFFFFF,0xFFFFFF48} "TRG queue"
15			16 BUF_TB_SET_S4_CAL_MASK 2 {0x20000181,0x55FFF300} "TRG queue"
16			17 BUF_TB_SET_BUSY_MASK_IDAQ_HOT 5 {0x20000382,0x76800000,0x0B000000} " "
17			18 BUF_TB_SET_BUSY_MASK_IDAQ_COLD 5 {0x20000382,0x76400000,0x86000000} " "
18			19 TRK_LOAD_PRG 2 {3,3} "The way the DSP program is loaded /RO"
19			21 BUF_TRK_TRAILER_PRG_0 3 {0x79000000} "TRK DSP Program Trailer for DSP 0 /RO"
20			22 BUF_TRK_TRAILER_PRG_1 3 {0x9A000000} "TRK DSP Program Trailer for DSP 1 /RO"
21			23 BUF_TRK_TRAILER_PRG_2 3 {0xB8000000} "TRK DSP Program Trailer for DSP 2 /RO"
22			24 BUF_TRK_TRAILER_PRG_3 3 {0x5B000000} "TRK DSP Program Trailer for DSP 3 /RO"
23			25 BUF_TRK_TRAILER_PRG_4 3 {0xFC000000} "TRK DSP Program Trailer for DSP 4 /RO"
24			26 BUF_TRK_TRAILER_PRG_5 3 {0x1F000000} "TRK DSP Program Trailer for DSP 5 /RO"
25			27 BUF_TRK_NUMBER_DSP_1_0 10 {0x001B01C7,0x00730200,0x0C000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07940000} "TRK command queue /RO"
26			28 BUF_TRK_NUMBER_DSP_1_1 10 {0x001B11B7,0x00730200,0x0A000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07210000} "TRK command queue /RO"
27			29 BUF_TRK_NUMBER_DSP_1_2 10 {0x001B2127,0x00730200,0x08000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07CB0000} "TRK command queue /RO"
28			30 BUF_TRK_NUMBER_DSP_1_3 10 {0x001B3157,0x00730200,0x04000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07C30000} "TRK command queue /RO"
29			31 BUF_TRK_NUMBER_DSP_1_4 10 {0x001B4100,0x00730200,0x06000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07A50000} "TRK command queue /RO"
30			32 BUF_TRK_NUMBER_DSP_1_5 10 {0x001B5170,0x00730200,0x02000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x079F0000} "TRK command queue /RO"
31			33 BUF_TRK_NUMBER_DSP_2_0 10 {0x001B01C7,0x00730200,0x0B000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07C60000} "TRK command queue /RO"
32			34 BUF_TRK_NUMBER_DSP_2_1 10 {0x001B11B7,0x00730200,0x09000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x076A0000} "TRK command queue /RO"
33			35 BUF_TRK_NUMBER_DSP_2_2 10 {0x001B2127,0x00730200,0x07000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07AB0000} "TRK command queue /RO"
34			36 BUF_TRK_NUMBER_DSP_2_3 10 {0x001B3157,0x00730200,0x03000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07910000} "TRK command queue /RO"
35			37 BUF_TRK_NUMBER_DSP_2_4 10 {0x001B4100,0x00730200,0x05000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07EE0000} "TRK command queue /RO"
36			38 BUF_TRK_NUMBER_DSP_2_5 10 {0x001B5170,0x00730200,0x01000400,0x07000200,0x01007F0C,0x0409607F,0xFF000500,0x07D40000} "TRK command queue /RO"
37			39 BUF_TRK_OPMODE_COMP_0 3 {0x0007016C,0x00730100,0x0A6F0000} "TRK command queue /RO"
38			40 BUF_TRK_OPMODE_SPEC_0 3 {0x0007016C,0x00730100,0x08610000} "TRK command queue /RO"
39			41 BUF_TRK_OPMODE_COMP_1 3 {0x0007111C,0x00730100,0x0AF10000} "TRK command queue /RO"
40			42 BUF_TRK_OPMODE_SPEC_1 3 {0x0007111C,0x00730100,0x08FF0000} "TRK command queue /RO"
41			43 BUF_TRK_OPMODE_COMP_2 3 {0x0007218C,0x00730100,0x0A540000} "TRK command queue /RO"
42			44 BUF_TRK_OPMODE_SPEC_2 3 {0x0007218C,0x00730100,0x085A0000} "TRK command queue /RO"
43			45 BUF_TRK_OPMODE_COMP_3 3 {0x000731FC,0x00730100,0x0ACA0000} "TRK command queue /RO"
44			46 BUF_TRK_OPMODE_SPEC_3 3 {0x000731FC,0x00730100,0x08C40000} "TRK command queue /RO"
45			47 BUF_TRK_OPMODE_COMP_4 3 {0x000741AB,0x00730100,0x0A190000} "TRK command queue /RO"
46			48 BUF_TRK_OPMODE_SPEC_4 3 {0x000741AB,0x00730100,0x08170000} "TRK command queue /RO"
47			49 BUF_TRK_OPMODE_COMP_5 3 {0x000751DB,0x00730100,0x0A870000} "TRK command queue /RO"
48			50 BUF_TRK_OPMODE_SPEC_5 3 {0x000751DB,0x00730100,0x08890000} "TRK command queue /RO"
49			51 CAL_COUNT 4 {
50			0x0003,
51			0x0003,
52			0x0003,
53			0x0003
54			} "defines the calorimeter read out repetitions /RO"
55			52 BUF_CAL_WRITE_FPGA_REG_I211 2 {0x4D230000,0x0001D214} "write fpga /RO"
56			53 BUF_CAL_WRITE_FPGA_REG_I221 2 {0x4D230001,0x0000F505} "write fpga /RO"
57			54 BUF_CAL_WRITE_FPGA_REG_I231 2 {0x4D230003,0xFFFF866A} "write fpga /RO"
58			57 BUF_CAL_WRITE_DSP_MEM_I43 11 {0x8E638000,0x00000002,0x1803000F,0xBA0E0000} "dsp prog i43 /RO"
59			58 BUF_CAL_READ_DSP_MEM_C31 8 {0xA7C80000,0x14001214,0x42BB0000} "dsp prog c31 /RO"
60			59 BUF_CAL_READ_DSP_MEM_C32 8 {0xA7C80000,0x400B0420,0xD2820000} "dsp prog c32 /RO"
61			60 BUF_CAL_WRITE_FPGA_REG_I241_1 2 {0x4D230004,0x0FFF103B} "write fpga i241_1 /RO"
62			61 BUF_CAL_WRITE_FPGA_REG_I241_2 2 {0x4D230004,0x0FFF103B} "write fpga i241_2 /RO"
63			62 BUF_CAL_WRITE_FPGA_REG_I241_3 2 {0x4D230004,0x0FEE122B} "write fpga i241_3 /RO"
64			63 BUF_CAL_WRITE_FPGA_REG_I241_4 2 {0x4D230004,0x0BFFDCFF} "write fpga i241_4 /RO"
65			64 BUF_CAL_WRITE_FPGA_REG_I251_1 2 {0x4D230005,0x007FA6BD} "write fpga i251_1 /RO"
66			65 BUF_CAL_WRITE_FPGA_REG_I251_2 2 {0x4D230005,0x007FA6BD} "write fpga i251_2 /RO"
67			66 BUF_CAL_WRITE_FPGA_REG_I251_3 2 {0x4D230005,0x007FA6BD} "write fpga i251_3 /RO"
68			67 BUF_CAL_WRITE_FPGA_REG_I251_4 2 {0x4D230005,0x007FA6BD} "write fpga i251_4 /RO"
69			68 BUF_CAL_WRITE_FPGA_REG_I261_1 2 {0x4D230002,0x0D55D059} "write fpga i261_1 /RO"
70			69 BUF_CAL_WRITE_FPGA_REG_I261_2 2 {0x4D230002,0x0D55D059} "write fpga i261_2 /RO"
71			70 BUF_CAL_WRITE_FPGA_REG_I261_3 2 {0x4D230002,0x0D55D059} "write fpga i261_3 /RO"
72			71 BUF_CAL_WRITE_FPGA_REG_I261_4 2 {0x4D230002,0x0D55D059} "write fpga i261_4 /RO"
73			72 BUF_CAL_WRITE_FPGA_REG_I260_1 2 {0x4D230002,0x055559F0} "write fpga i260_1 /RO"
74			73 BUF_CAL_WRITE_FPGA_REG_I260_2 2 {0x4D230002,0x055559F0} "write fpga i260_2 /RO"
75			74 BUF_CAL_WRITE_FPGA_REG_I260_3 2 {0x4D230002,0x055559F0} "write fpga i260_3 /RO"
76			75 BUF_CAL_WRITE_FPGA_REG_I260_4 2 {0x4D230002,0x055559F0} "write fpga i260_4 /RO"
77			76 BUF_CAL_WRITE_FPGA_REG_I311_1 2 {0x4D230002,0x0FFFA29B} "write fpga i311_1 /RO"
78			77 BUF_CAL_WRITE_FPGA_REG_I311_2 2 {0x4D230002,0x0FFFA29B} "write fpga i311_2 /RO"
79			78 BUF_CAL_WRITE_FPGA_REG_I311_3 2 {0x4D230002,0x0FFFA29B} "write fpga i311_3 /RO"
80			79 BUF_CAL_WRITE_FPGA_REG_I311_4 2 {0x4D230002,0x0FFFA29B} "write fpga i311_4 /RO"
81			80 BUF_CAL_WRITE_FPGA_REG_I310_1 2 {0x4D230002,0x07FF2B32} "write fpga i310_1 /RO"
82			81 BUF_CAL_WRITE_FPGA_REG_I310_2 2 {0x4D230002,0x07FF2B32} "write fpga i310_2 /RO"
83			82 BUF_CAL_WRITE_FPGA_REG_I310_3 2 {0x4D230002,0x07FF2B32} "write fpga i310_3 /RO"
84			83 BUF_CAL_WRITE_FPGA_REG_I310_4 2 {0x4D230002,0x07FF2B32} "write fpga i310_4 /RO"
85			84 BUF_CAL_WRITE_FPGA_REG_I321 2 {0x4D230000,0x8001C98C} "write fpga i321 /RO"
86			85 BUF_CAL_WRITE_FPGA_REG_I331_1 2 {0x4D230006,0x07FFF7F2} "write fpga i331_1 /RO"
87			86 BUF_CAL_WRITE_FPGA_REG_I331_2 2 {0x4D230006,0x07FFF7F2} "write fpga i331_2 /RO"
88			87 BUF_CAL_WRITE_FPGA_REG_I331_3 2 {0x4D230006,0x07FFF7F2} "write fpga i331_3 /RO"
89			88 BUF_CAL_WRITE_FPGA_REG_I331_4 2 {0x4D230006,0x07FFF7F2} "write fpga i331_4 /RO"
90			89 BUF_CAL_WRITE_FPGA_REG_OFF 2 {0x4D230002,0x0000AC55} "write fpga reg off /RO"
91			90 BUF_CAL_WRITE_FPGA_REG_I341_1 2 {0x4D230004,0x0FFF103B} "write fpga i341_1 /RO"
92			91 BUF_CAL_WRITE_FPGA_REG_I341_2 2 {0x4D230004,0x0FFF103B} "write fpga i341_2 /RO"
93			92 BUF_CAL_WRITE_FPGA_REG_I341_3 2 {0x4D230004,0x0FEE122B} "write fpga i341_3 /RO"
94			93 BUF_CAL_WRITE_FPGA_REG_I341_4 2 {0x4D230004,0x0BFFDCFF} "write fpga i341_4 /RO"
95			94 BUF_AC_1_SET_DAQ 35 {0x008A0000,0x000EFFFF,0xFFFF0001,0x0023FFFF,0xFFFF0002,0x0021FFFF,0xFFFF0003,0x0021FFFF,0xFFFF0004,0x0018FFFF,0xFFFF0005,0x002DFFFF,0xFFFF0006,0x0020FFFF,0xFFFF0007,0x0020FFFF,0xFFFF0008,0x0012FFFF,0xFFFF0009,0x0019FFFF,0xFFFF000A,0x001BFFFF,0xFFFF000B,0x001BFFFF,0xFFFF000C,0x0014FFFF,0xFFFF000D,0x0043FFFF,0xFFFF000E,0x0023FFFF,0xFFFF000F,0x0023FFFF,0xFFFF0D95} "SET DAQ command /RO"
96			95 BUF_AC_2_SET_DAQ 35 {0x008A0000,0x0020FFFF,0xFFFF0001,0x001BFFFF,0xFFFF0002,0x003AFFFF,0xFFFF0003,0x003AFFFF,0xFFFF0004,0x0015FFFF,0xFFFF0005,0x001CFFFF,0xFFFF0006,0x0014FFFF,0xFFFF0007,0x0014FFFF,0xFFFF0008,0x001CFFFF,0xFFFF0009,0x0039FFFF,0xFFFF000A,0x0010FFFF,0xFFFF000B,0x0010FFFF,0xFFFF000C,0x0019FFFF,0xFFFF000D,0x0012FFFF,0xFFFF000E,0x001AFFFF,0xFFFF000F,0x001AFFFF,0xFFFFAE20} "SET DAQ command /RO"
97			99 BUF_AC_2_WRITE_REG 15 {0x00890008,0xFFFF0040,0xACACFFFF,0x0041AC22,0xFFFF0044,0xFE00FFFF,0x00450000,0xFFFF0046,0xFFFFFFFF,0x00470040,0xFFFF0048,0xFFFFFFFF,0x0049FFFF,0x442B0000} "/RO"
98			100 BUF_AC_1_WRITE_REG 15 {0x00890008,0xFFFF0040,0xACACFFFF,0x0041AC11,0xFFFF0044,0xFE00FFFF,0x0045000F,0xFFFF0046,0xFFFFFFFF,0x00470040,0xFFFF0048,0xFFFFFFFF,0x0049FFFF,0x42D80000} "/RO"
99			101 BUF_AC_READ_DSP_MEM 3 {0x00804100,0x80002040,0x17530000} " /RO"
100			102 BUF_TOF_WRITE_PMT_THR_1 2 {0xB0C40A0A,0x0707FC00} "TOF set THR front end 1 /RO"
101			103 BUF_TOF_WRITE_PMT_THR_2 2 {0xB1C40707,0x0707BA00} "TOF set THR front end 2 /RO"
102			104 BUF_TOF_WRITE_PMT_THR_3 2 {0xB2C40707,0x0707C100} "TOF set THR front end 3 /RO"
103			105 BUF_TOF_WRITE_PMT_THR_4 2 {0xB3C40707,0x0707E800} "TOF set THR front end 4 /RO"
104			106 BUF_TOF_WRITE_PMT_THR_5 2 {0xB4C40707,0x07073700} "TOF set THR front end 5 /RO"
105			107 BUF_TOF_WRITE_PMT_THR_6 2 {0xB5C40707,0x07071E00} "TOF set THR front end 5 /RO"
106			108 TOF_PLAN 6 {1,1,1,1,1,1} "TOF Plans selectors /RO"
107			109 PM_PERIODIC_DELAY 4
108			{
109			1000,
110			10000,
111			10000,
112			10002460*60
113			} "Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations, /RO"
114			110 PSB_COMMANDS 29 {
115			0x00C5,
116			0x01B6,
117			0x02D0,
118			0x05C5,
119			0x05A5,
120			0x0500,
121			0x0500,
122			0x06C3,
123			0x07D0,
124			0x08EC,
125			0x09FF,
126			0x0AF9,
127			0x0B8A,
128			0x0C9F,
129			0x0E8A,
130			0x0F99,
131			0x10AE,
132			0x121E,
133			0x12DB,
134			0x121E,
135			0x14DD,
136			0x15CE,
137			0x17DB,
138			0x18E7,
139			0x19F4,
140			0x03c3,
141			0x04d6,
142			0x0dec,
143			0x0F3C
144			} "Command for PSB /RO"
145			111 PSB_CALO_FE_ON 4 {
146			0x1AF2,
147			0x1BE1,
148			0x1CF4,
149			0x1DE7
150			} "Command for PSB /RO"
151			112 PSB_CALO_FE_OFF 4 {
152			0x1A37,
153			0x1B24,
154			0x1C31,
155			0x1D22
156			} "Command for PSB /RO"
157			113 PSB_CALO_FE 4 {
158			0x1AF2,
159			0x1BE1,
160			0x1CF4,
161			0x1DE7
162			} "Command for PSB /RO"
163			114 HVB_COMMANDS 12 {
164			0xC387,
165			0xC78F,
166			0xCB16,
167			0xCF9F,
168			0xD2A5,
169			0xD7AF,
170			0xDBB7,
171			0xDFBF,
172			0xE3C7,
173			0xE6CD,
174			0xEBD7,
175			0xEEDD
176			} "Command for HVB /RO"
177			115 TSB_BOARD_OK 2 {1,0} "User TSB Board no 0/1 flags /RO"