/[PAMELA software]/quicklook/dataToXML/Data/compilationInfo/PRH_ParamHandler_INFN_auto.arr.xml
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Contents of /quicklook/dataToXML/Data/compilationInfo/PRH_ParamHandler_INFN_auto.arr.xml

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Revision 1.1.1.1 - (show annotations) (download) (as text) (vendor branch)
Tue Apr 25 09:00:20 2006 UTC (18 years, 7 months ago) by kusanagi
Branch: MAIN
CVS Tags: dataToXML1_02/01, dataToXML1_02/00, dataToXML1_03/00, dataToXML1_03/01, dataToXML1_00/00, firstRelease, dataToXML1_01/00, dataToXML1_03_02, HEAD
Changes since 1.1: +0 -0 lines
File MIME type: text/xml
These program extract in an XML format the info contained into the ROOT files generated by YODA from the PAMELA data. To visualize the XML files in a more human readable format a collection of XSL files are given in the Data subfolder.

1
2 <arrxml>
3
4 <arr>
5 <name>LOG_MASK</name>
6 <n>113</n>
7 <idx>0</idx>
8 <comment><![CDATA[log level mask for each module /RO]]></comment>
9 </arr>
10
11 <arr>
12 <name>THERM_LOW</name>
13 <n>16</n>
14 <idx>1</idx>
15 <comment><![CDATA[Thermistor low limit /RO]]></comment>
16 </arr>
17
18 <arr>
19 <name>THERM_HIGH</name>
20 <n>16</n>
21 <idx>2</idx>
22 <comment><![CDATA[Thermistor high limit /RO]]></comment>
23 </arr>
24
25 <arr>
26 <name>BUF_TRIG_II_INIT</name>
27 <n>3750</n>
28 <idx>3</idx>
29 <comment><![CDATA[TRIG_II init command queue]]></comment>
30 </arr>
31
32 <arr>
33 <name>BUF_TRIG_II_ACQ</name>
34 <n>375</n>
35 <idx>4</idx>
36 <comment><![CDATA[TRIG_II acq command queue]]></comment>
37 </arr>
38
39 <arr>
40 <name>WS_1_SETTING</name>
41 <n>5</n>
42 <idx>5</idx>
43 <comment><![CDATA[Define the Working Schedule #1 values in ms /RO]]></comment>
44 </arr>
45
46 <arr>
47 <name>RM_RATE_METER_S1_TRH</name>
48 <n>2</n>
49 <idx>6</idx>
50 <comment><![CDATA[Rate meter s1 register TRH.used to toggle A/B mode in WS3 mode. the index of the array is related to the current ACQ mode (0=A to B,1=B to A) /RO]]></comment>
51 </arr>
52
53 <arr>
54 <name>PWR_IPM_CONF</name>
55 <n>6</n>
56 <idx>7</idx>
57 <comment><![CDATA[IMP desired configuration for initial poweron 6 bitmask /RO]]></comment>
58 </arr>
59
60 <arr>
61 <name>PWR_VOLTAGE_IPM_RANGE_ON_MAX</name>
62 <n>6</n>
63 <idx>8</idx>
64 <comment><![CDATA[ADC min voltage values if ON /RO]]></comment>
65 </arr>
66
67 <arr>
68 <name>PWR_VOLTAGE_IPM_RANGE_ON_MIN</name>
69 <n>6</n>
70 <idx>9</idx>
71 <comment><![CDATA[ADC min voltage values if ON /RO]]></comment>
72 </arr>
73
74 <arr>
75 <name>PWR_VOLTAGE_IPM_RANGE_OFF_MAX</name>
76 <n>6</n>
77 <idx>10</idx>
78 <comment><![CDATA[ADC min voltage values if OFF /RO]]></comment>
79 </arr>
80
81 <arr>
82 <name>PWR_VOLTAGE_IPM_RANGE_OFF_MIN</name>
83 <n>6</n>
84 <idx>11</idx>
85 <comment><![CDATA[ADC min voltage values if OFF /RO]]></comment>
86 </arr>
87
88 <arr>
89 <name>TM_FILTER_OPERATION</name>
90 <n>78</n>
91 <idx>12</idx>
92 <comment><![CDATA[low level telemetry filter operation: 0->apply no filter 1->set value 2->ORed mask 3->ANDed mask /RO]]></comment>
93 </arr>
94
95 <arr>
96 <name>TM_FILTER_VALUE</name>
97 <n>78</n>
98 <idx>13</idx>
99 <comment><![CDATA[low level telemetry filted values /RO]]></comment>
100 </arr>
101
102 <arr>
103 <name>BUF_TB_SET_ALARM_MASK</name>
104 <n>2</n>
105 <idx>14</idx>
106 <comment><![CDATA[TRG queue]]></comment>
107 </arr>
108
109 <arr>
110 <name>BUF_TB_SET_PMT_MASK</name>
111 <n>3</n>
112 <idx>15</idx>
113 <comment><![CDATA[TRG queue]]></comment>
114 </arr>
115
116 <arr>
117 <name>BUF_TB_SET_S4_CAL_MASK</name>
118 <n>2</n>
119 <idx>16</idx>
120 <comment><![CDATA[TRG queue]]></comment>
121 </arr>
122
123 <arr>
124 <name>BUF_TB_SET_BUSY_MASK_IDAQ_HOT</name>
125 <n>5</n>
126 <idx>17</idx>
127 <comment><![CDATA[ ]]></comment>
128 </arr>
129
130 <arr>
131 <name>BUF_TB_SET_BUSY_MASK_IDAQ_COLD</name>
132 <n>5</n>
133 <idx>18</idx>
134 <comment><![CDATA[ ]]></comment>
135 </arr>
136
137 <arr>
138 <name>TRK_LOAD_PRG</name>
139 <n>2</n>
140 <idx>19</idx>
141 <comment><![CDATA[The way the DSP program is loaded /RO]]></comment>
142 </arr>
143
144 <arr>
145 <name>BUF_TRK_PROGRAM</name>
146 <n>3000</n>
147 <idx>20</idx>
148 <comment><![CDATA[TRK DSP Program /RO]]></comment>
149 </arr>
150
151 <arr>
152 <name>BUF_TRK_TRAILER_PRG_0</name>
153 <n>3</n>
154 <idx>21</idx>
155 <comment><![CDATA[TRK DSP Program Trailer for DSP 0 /RO]]></comment>
156 </arr>
157
158 <arr>
159 <name>BUF_TRK_TRAILER_PRG_1</name>
160 <n>3</n>
161 <idx>22</idx>
162 <comment><![CDATA[TRK DSP Program Trailer for DSP 1 /RO]]></comment>
163 </arr>
164
165 <arr>
166 <name>BUF_TRK_TRAILER_PRG_2</name>
167 <n>3</n>
168 <idx>23</idx>
169 <comment><![CDATA[TRK DSP Program Trailer for DSP 2 /RO]]></comment>
170 </arr>
171
172 <arr>
173 <name>BUF_TRK_TRAILER_PRG_3</name>
174 <n>3</n>
175 <idx>24</idx>
176 <comment><![CDATA[TRK DSP Program Trailer for DSP 3 /RO]]></comment>
177 </arr>
178
179 <arr>
180 <name>BUF_TRK_TRAILER_PRG_4</name>
181 <n>3</n>
182 <idx>25</idx>
183 <comment><![CDATA[TRK DSP Program Trailer for DSP 4 /RO]]></comment>
184 </arr>
185
186 <arr>
187 <name>BUF_TRK_TRAILER_PRG_5</name>
188 <n>3</n>
189 <idx>26</idx>
190 <comment><![CDATA[TRK DSP Program Trailer for DSP 5 /RO]]></comment>
191 </arr>
192
193 <arr>
194 <name>BUF_TRK_NUMBER_DSP_1_0</name>
195 <n>10</n>
196 <idx>27</idx>
197 <comment><![CDATA[TRK command queue /RO]]></comment>
198 </arr>
199
200 <arr>
201 <name>BUF_TRK_NUMBER_DSP_1_1</name>
202 <n>10</n>
203 <idx>28</idx>
204 <comment><![CDATA[TRK command queue /RO]]></comment>
205 </arr>
206
207 <arr>
208 <name>BUF_TRK_NUMBER_DSP_1_2</name>
209 <n>10</n>
210 <idx>29</idx>
211 <comment><![CDATA[TRK command queue /RO]]></comment>
212 </arr>
213
214 <arr>
215 <name>BUF_TRK_NUMBER_DSP_1_3</name>
216 <n>10</n>
217 <idx>30</idx>
218 <comment><![CDATA[TRK command queue /RO]]></comment>
219 </arr>
220
221 <arr>
222 <name>BUF_TRK_NUMBER_DSP_1_4</name>
223 <n>10</n>
224 <idx>31</idx>
225 <comment><![CDATA[TRK command queue /RO]]></comment>
226 </arr>
227
228 <arr>
229 <name>BUF_TRK_NUMBER_DSP_1_5</name>
230 <n>10</n>
231 <idx>32</idx>
232 <comment><![CDATA[TRK command queue /RO]]></comment>
233 </arr>
234
235 <arr>
236 <name>BUF_TRK_NUMBER_DSP_2_0</name>
237 <n>10</n>
238 <idx>33</idx>
239 <comment><![CDATA[TRK command queue /RO]]></comment>
240 </arr>
241
242 <arr>
243 <name>BUF_TRK_NUMBER_DSP_2_1</name>
244 <n>10</n>
245 <idx>34</idx>
246 <comment><![CDATA[TRK command queue /RO]]></comment>
247 </arr>
248
249 <arr>
250 <name>BUF_TRK_NUMBER_DSP_2_2</name>
251 <n>10</n>
252 <idx>35</idx>
253 <comment><![CDATA[TRK command queue /RO]]></comment>
254 </arr>
255
256 <arr>
257 <name>BUF_TRK_NUMBER_DSP_2_3</name>
258 <n>10</n>
259 <idx>36</idx>
260 <comment><![CDATA[TRK command queue /RO]]></comment>
261 </arr>
262
263 <arr>
264 <name>BUF_TRK_NUMBER_DSP_2_4</name>
265 <n>10</n>
266 <idx>37</idx>
267 <comment><![CDATA[TRK command queue /RO]]></comment>
268 </arr>
269
270 <arr>
271 <name>BUF_TRK_NUMBER_DSP_2_5</name>
272 <n>10</n>
273 <idx>38</idx>
274 <comment><![CDATA[TRK command queue /RO]]></comment>
275 </arr>
276
277 <arr>
278 <name>BUF_TRK_OPMODE_COMP_0</name>
279 <n>3</n>
280 <idx>39</idx>
281 <comment><![CDATA[TRK command queue /RO]]></comment>
282 </arr>
283
284 <arr>
285 <name>BUF_TRK_OPMODE_SPEC_0</name>
286 <n>3</n>
287 <idx>40</idx>
288 <comment><![CDATA[TRK command queue /RO]]></comment>
289 </arr>
290
291 <arr>
292 <name>BUF_TRK_OPMODE_COMP_1</name>
293 <n>3</n>
294 <idx>41</idx>
295 <comment><![CDATA[TRK command queue /RO]]></comment>
296 </arr>
297
298 <arr>
299 <name>BUF_TRK_OPMODE_SPEC_1</name>
300 <n>3</n>
301 <idx>42</idx>
302 <comment><![CDATA[TRK command queue /RO]]></comment>
303 </arr>
304
305 <arr>
306 <name>BUF_TRK_OPMODE_COMP_2</name>
307 <n>3</n>
308 <idx>43</idx>
309 <comment><![CDATA[TRK command queue /RO]]></comment>
310 </arr>
311
312 <arr>
313 <name>BUF_TRK_OPMODE_SPEC_2</name>
314 <n>3</n>
315 <idx>44</idx>
316 <comment><![CDATA[TRK command queue /RO]]></comment>
317 </arr>
318
319 <arr>
320 <name>BUF_TRK_OPMODE_COMP_3</name>
321 <n>3</n>
322 <idx>45</idx>
323 <comment><![CDATA[TRK command queue /RO]]></comment>
324 </arr>
325
326 <arr>
327 <name>BUF_TRK_OPMODE_SPEC_3</name>
328 <n>3</n>
329 <idx>46</idx>
330 <comment><![CDATA[TRK command queue /RO]]></comment>
331 </arr>
332
333 <arr>
334 <name>BUF_TRK_OPMODE_COMP_4</name>
335 <n>3</n>
336 <idx>47</idx>
337 <comment><![CDATA[TRK command queue /RO]]></comment>
338 </arr>
339
340 <arr>
341 <name>BUF_TRK_OPMODE_SPEC_4</name>
342 <n>3</n>
343 <idx>48</idx>
344 <comment><![CDATA[TRK command queue /RO]]></comment>
345 </arr>
346
347 <arr>
348 <name>BUF_TRK_OPMODE_COMP_5</name>
349 <n>3</n>
350 <idx>49</idx>
351 <comment><![CDATA[TRK command queue /RO]]></comment>
352 </arr>
353
354 <arr>
355 <name>BUF_TRK_OPMODE_SPEC_5</name>
356 <n>3</n>
357 <idx>50</idx>
358 <comment><![CDATA[TRK command queue /RO]]></comment>
359 </arr>
360
361 <arr>
362 <name>CAL_COUNT</name>
363 <n>4</n>
364 <idx>51</idx>
365 <comment><![CDATA[defines the calorimeter read out repetitions /RO]]></comment>
366 </arr>
367
368 <arr>
369 <name>BUF_CAL_WRITE_FPGA_REG_I211</name>
370 <n>2</n>
371 <idx>52</idx>
372 <comment><![CDATA[write fpga /RO]]></comment>
373 </arr>
374
375 <arr>
376 <name>BUF_CAL_WRITE_FPGA_REG_I221</name>
377 <n>2</n>
378 <idx>53</idx>
379 <comment><![CDATA[write fpga /RO]]></comment>
380 </arr>
381
382 <arr>
383 <name>BUF_CAL_WRITE_FPGA_REG_I231</name>
384 <n>2</n>
385 <idx>54</idx>
386 <comment><![CDATA[write fpga /RO]]></comment>
387 </arr>
388
389 <arr>
390 <name>BUF_CAL_WRITE_DSP_MEM_I41</name>
391 <n>3176</n>
392 <idx>55</idx>
393 <comment><![CDATA[dsp prog i41 /R0]]></comment>
394 </arr>
395
396 <arr>
397 <name>BUF_CAL_WRITE_DSP_MEM_I42</name>
398 <n>2723</n>
399 <idx>56</idx>
400 <comment><![CDATA[dsp prog i42 /RO]]></comment>
401 </arr>
402
403 <arr>
404 <name>BUF_CAL_WRITE_DSP_MEM_I43</name>
405 <n>11</n>
406 <idx>57</idx>
407 <comment><![CDATA[dsp prog i43 /RO]]></comment>
408 </arr>
409
410 <arr>
411 <name>BUF_CAL_READ_DSP_MEM_C31</name>
412 <n>8</n>
413 <idx>58</idx>
414 <comment><![CDATA[dsp prog c31 /RO]]></comment>
415 </arr>
416
417 <arr>
418 <name>BUF_CAL_READ_DSP_MEM_C32</name>
419 <n>8</n>
420 <idx>59</idx>
421 <comment><![CDATA[dsp prog c32 /RO]]></comment>
422 </arr>
423
424 <arr>
425 <name>BUF_CAL_WRITE_FPGA_REG_I241_1</name>
426 <n>2</n>
427 <idx>60</idx>
428 <comment><![CDATA[write fpga i241_1 /RO]]></comment>
429 </arr>
430
431 <arr>
432 <name>BUF_CAL_WRITE_FPGA_REG_I241_2</name>
433 <n>2</n>
434 <idx>61</idx>
435 <comment><![CDATA[write fpga i241_2 /RO]]></comment>
436 </arr>
437
438 <arr>
439 <name>BUF_CAL_WRITE_FPGA_REG_I241_3</name>
440 <n>2</n>
441 <idx>62</idx>
442 <comment><![CDATA[write fpga i241_3 /RO]]></comment>
443 </arr>
444
445 <arr>
446 <name>BUF_CAL_WRITE_FPGA_REG_I241_4</name>
447 <n>2</n>
448 <idx>63</idx>
449 <comment><![CDATA[write fpga i241_4 /RO]]></comment>
450 </arr>
451
452 <arr>
453 <name>BUF_CAL_WRITE_FPGA_REG_I251_1</name>
454 <n>2</n>
455 <idx>64</idx>
456 <comment><![CDATA[write fpga i251_1 /RO]]></comment>
457 </arr>
458
459 <arr>
460 <name>BUF_CAL_WRITE_FPGA_REG_I251_2</name>
461 <n>2</n>
462 <idx>65</idx>
463 <comment><![CDATA[write fpga i251_2 /RO]]></comment>
464 </arr>
465
466 <arr>
467 <name>BUF_CAL_WRITE_FPGA_REG_I251_3</name>
468 <n>2</n>
469 <idx>66</idx>
470 <comment><![CDATA[write fpga i251_3 /RO]]></comment>
471 </arr>
472
473 <arr>
474 <name>BUF_CAL_WRITE_FPGA_REG_I251_4</name>
475 <n>2</n>
476 <idx>67</idx>
477 <comment><![CDATA[write fpga i251_4 /RO]]></comment>
478 </arr>
479
480 <arr>
481 <name>BUF_CAL_WRITE_FPGA_REG_I261_1</name>
482 <n>2</n>
483 <idx>68</idx>
484 <comment><![CDATA[write fpga i261_1 /RO]]></comment>
485 </arr>
486
487 <arr>
488 <name>BUF_CAL_WRITE_FPGA_REG_I261_2</name>
489 <n>2</n>
490 <idx>69</idx>
491 <comment><![CDATA[write fpga i261_2 /RO]]></comment>
492 </arr>
493
494 <arr>
495 <name>BUF_CAL_WRITE_FPGA_REG_I261_3</name>
496 <n>2</n>
497 <idx>70</idx>
498 <comment><![CDATA[write fpga i261_3 /RO]]></comment>
499 </arr>
500
501 <arr>
502 <name>BUF_CAL_WRITE_FPGA_REG_I261_4</name>
503 <n>2</n>
504 <idx>71</idx>
505 <comment><![CDATA[write fpga i261_4 /RO]]></comment>
506 </arr>
507
508 <arr>
509 <name>BUF_CAL_WRITE_FPGA_REG_I260_1</name>
510 <n>2</n>
511 <idx>72</idx>
512 <comment><![CDATA[write fpga i260_1 /RO]]></comment>
513 </arr>
514
515 <arr>
516 <name>BUF_CAL_WRITE_FPGA_REG_I260_2</name>
517 <n>2</n>
518 <idx>73</idx>
519 <comment><![CDATA[write fpga i260_2 /RO]]></comment>
520 </arr>
521
522 <arr>
523 <name>BUF_CAL_WRITE_FPGA_REG_I260_3</name>
524 <n>2</n>
525 <idx>74</idx>
526 <comment><![CDATA[write fpga i260_3 /RO]]></comment>
527 </arr>
528
529 <arr>
530 <name>BUF_CAL_WRITE_FPGA_REG_I260_4</name>
531 <n>2</n>
532 <idx>75</idx>
533 <comment><![CDATA[write fpga i260_4 /RO]]></comment>
534 </arr>
535
536 <arr>
537 <name>BUF_CAL_WRITE_FPGA_REG_I311_1</name>
538 <n>2</n>
539 <idx>76</idx>
540 <comment><![CDATA[write fpga i311_1 /RO]]></comment>
541 </arr>
542
543 <arr>
544 <name>BUF_CAL_WRITE_FPGA_REG_I311_2</name>
545 <n>2</n>
546 <idx>77</idx>
547 <comment><![CDATA[write fpga i311_2 /RO]]></comment>
548 </arr>
549
550 <arr>
551 <name>BUF_CAL_WRITE_FPGA_REG_I311_3</name>
552 <n>2</n>
553 <idx>78</idx>
554 <comment><![CDATA[write fpga i311_3 /RO]]></comment>
555 </arr>
556
557 <arr>
558 <name>BUF_CAL_WRITE_FPGA_REG_I311_4</name>
559 <n>2</n>
560 <idx>79</idx>
561 <comment><![CDATA[write fpga i311_4 /RO]]></comment>
562 </arr>
563
564 <arr>
565 <name>BUF_CAL_WRITE_FPGA_REG_I310_1</name>
566 <n>2</n>
567 <idx>80</idx>
568 <comment><![CDATA[write fpga i310_1 /RO]]></comment>
569 </arr>
570
571 <arr>
572 <name>BUF_CAL_WRITE_FPGA_REG_I310_2</name>
573 <n>2</n>
574 <idx>81</idx>
575 <comment><![CDATA[write fpga i310_2 /RO]]></comment>
576 </arr>
577
578 <arr>
579 <name>BUF_CAL_WRITE_FPGA_REG_I310_3</name>
580 <n>2</n>
581 <idx>82</idx>
582 <comment><![CDATA[write fpga i310_3 /RO]]></comment>
583 </arr>
584
585 <arr>
586 <name>BUF_CAL_WRITE_FPGA_REG_I310_4</name>
587 <n>2</n>
588 <idx>83</idx>
589 <comment><![CDATA[write fpga i310_4 /RO]]></comment>
590 </arr>
591
592 <arr>
593 <name>BUF_CAL_WRITE_FPGA_REG_I321</name>
594 <n>2</n>
595 <idx>84</idx>
596 <comment><![CDATA[write fpga i321 /RO]]></comment>
597 </arr>
598
599 <arr>
600 <name>BUF_CAL_WRITE_FPGA_REG_I331_1</name>
601 <n>2</n>
602 <idx>85</idx>
603 <comment><![CDATA[write fpga i331_1 /RO]]></comment>
604 </arr>
605
606 <arr>
607 <name>BUF_CAL_WRITE_FPGA_REG_I331_2</name>
608 <n>2</n>
609 <idx>86</idx>
610 <comment><![CDATA[write fpga i331_2 /RO]]></comment>
611 </arr>
612
613 <arr>
614 <name>BUF_CAL_WRITE_FPGA_REG_I331_3</name>
615 <n>2</n>
616 <idx>87</idx>
617 <comment><![CDATA[write fpga i331_3 /RO]]></comment>
618 </arr>
619
620 <arr>
621 <name>BUF_CAL_WRITE_FPGA_REG_I331_4</name>
622 <n>2</n>
623 <idx>88</idx>
624 <comment><![CDATA[write fpga i331_4 /RO]]></comment>
625 </arr>
626
627 <arr>
628 <name>BUF_CAL_WRITE_FPGA_REG_OFF</name>
629 <n>2</n>
630 <idx>89</idx>
631 <comment><![CDATA[write fpga reg off /RO]]></comment>
632 </arr>
633
634 <arr>
635 <name>BUF_CAL_WRITE_FPGA_REG_I341_1</name>
636 <n>2</n>
637 <idx>90</idx>
638 <comment><![CDATA[write fpga i341_1 /RO]]></comment>
639 </arr>
640
641 <arr>
642 <name>BUF_CAL_WRITE_FPGA_REG_I341_2</name>
643 <n>2</n>
644 <idx>91</idx>
645 <comment><![CDATA[write fpga i341_2 /RO]]></comment>
646 </arr>
647
648 <arr>
649 <name>BUF_CAL_WRITE_FPGA_REG_I341_3</name>
650 <n>2</n>
651 <idx>92</idx>
652 <comment><![CDATA[write fpga i341_3 /RO]]></comment>
653 </arr>
654
655 <arr>
656 <name>BUF_CAL_WRITE_FPGA_REG_I341_4</name>
657 <n>2</n>
658 <idx>93</idx>
659 <comment><![CDATA[write fpga i341_4 /RO]]></comment>
660 </arr>
661
662 <arr>
663 <name>BUF_AC_1_SET_DAQ</name>
664 <n>35</n>
665 <idx>94</idx>
666 <comment><![CDATA[SET DAQ command /RO]]></comment>
667 </arr>
668
669 <arr>
670 <name>BUF_AC_2_SET_DAQ</name>
671 <n>35</n>
672 <idx>95</idx>
673 <comment><![CDATA[SET DAQ command /RO]]></comment>
674 </arr>
675
676 <arr>
677 <name>BUF_AC_SEND_DSP_PROG1</name>
678 <n>5010</n>
679 <idx>96</idx>
680 <comment><![CDATA[DSP Program 1 /RO]]></comment>
681 </arr>
682
683 <arr>
684 <name>BUF_AC_1_SEND_DSP_PROG2</name>
685 <n>3800</n>
686 <idx>97</idx>
687 <comment><![CDATA[ /RO]]></comment>
688 </arr>
689
690 <arr>
691 <name>BUF_AC_2_SEND_DSP_PROG2</name>
692 <n>3800</n>
693 <idx>98</idx>
694 <comment><![CDATA[ /RO]]></comment>
695 </arr>
696
697 <arr>
698 <name>BUF_AC_2_WRITE_REG</name>
699 <n>15</n>
700 <idx>99</idx>
701 <comment><![CDATA[/RO]]></comment>
702 </arr>
703
704 <arr>
705 <name>BUF_AC_1_WRITE_REG</name>
706 <n>15</n>
707 <idx>100</idx>
708 <comment><![CDATA[/RO]]></comment>
709 </arr>
710
711 <arr>
712 <name>BUF_AC_READ_DSP_MEM</name>
713 <n>3</n>
714 <idx>101</idx>
715 <comment><![CDATA[ /RO]]></comment>
716 </arr>
717
718 <arr>
719 <name>BUF_TOF_WRITE_PMT_THR_1</name>
720 <n>2</n>
721 <idx>102</idx>
722 <comment><![CDATA[TOF set THR front end 1 /RO]]></comment>
723 </arr>
724
725 <arr>
726 <name>BUF_TOF_WRITE_PMT_THR_2</name>
727 <n>2</n>
728 <idx>103</idx>
729 <comment><![CDATA[TOF set THR front end 2 /RO]]></comment>
730 </arr>
731
732 <arr>
733 <name>BUF_TOF_WRITE_PMT_THR_3</name>
734 <n>2</n>
735 <idx>104</idx>
736 <comment><![CDATA[TOF set THR front end 3 /RO]]></comment>
737 </arr>
738
739 <arr>
740 <name>BUF_TOF_WRITE_PMT_THR_4</name>
741 <n>2</n>
742 <idx>105</idx>
743 <comment><![CDATA[TOF set THR front end 4 /RO]]></comment>
744 </arr>
745
746 <arr>
747 <name>BUF_TOF_WRITE_PMT_THR_5</name>
748 <n>2</n>
749 <idx>106</idx>
750 <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
751 </arr>
752
753 <arr>
754 <name>BUF_TOF_WRITE_PMT_THR_6</name>
755 <n>2</n>
756 <idx>107</idx>
757 <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
758 </arr>
759
760 <arr>
761 <name>TOF_PLAN</name>
762 <n>6</n>
763 <idx>108</idx>
764 <comment><![CDATA[TOF Plans selectors /RO]]></comment>
765 </arr>
766
767 <arr>
768 <name>PM_PERIODIC_DELAY</name>
769 <n>4</n>
770 <idx>109</idx>
771 <comment><![CDATA[Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations, /RO]]></comment>
772 </arr>
773
774 <arr>
775 <name>PSB_COMMANDS</name>
776 <n>29</n>
777 <idx>110</idx>
778 <comment><![CDATA[Command for PSB /RO]]></comment>
779 </arr>
780
781 <arr>
782 <name>PSB_CALO_FE_ON</name>
783 <n>4</n>
784 <idx>111</idx>
785 <comment><![CDATA[Command for PSB /RO]]></comment>
786 </arr>
787
788 <arr>
789 <name>PSB_CALO_FE_OFF</name>
790 <n>4</n>
791 <idx>112</idx>
792 <comment><![CDATA[Command for PSB /RO]]></comment>
793 </arr>
794
795 <arr>
796 <name>PSB_CALO_FE</name>
797 <n>4</n>
798 <idx>113</idx>
799 <comment><![CDATA[Command for PSB /RO]]></comment>
800 </arr>
801
802 <arr>
803 <name>HVB_COMMANDS</name>
804 <n>12</n>
805 <idx>114</idx>
806 <comment><![CDATA[Command for HVB /RO]]></comment>
807 </arr>
808
809 <arr>
810 <name>TSB_BOARD_OK</name>
811 <n>2</n>
812 <idx>115</idx>
813 <comment><![CDATA[User TSB Board no 0/1 flags /RO]]></comment>
814 </arr>
815
816 </arrxml>

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