
<arrxml>

<arr>
  <name>LOG_MASK</name>
  <n>113</n>
  <idx>0</idx>
  <comment><![CDATA[log level mask for each module /RO]]></comment>
</arr>

<arr>
  <name>THERM_LOW</name>
  <n>16</n>
  <idx>1</idx>
  <comment><![CDATA[Thermistor low limit /RO]]></comment>
</arr>

<arr>
  <name>THERM_HIGH</name>
  <n>16</n>
  <idx>2</idx>
  <comment><![CDATA[Thermistor high limit /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRIG_II_INIT</name>
  <n>3750</n>
  <idx>3</idx>
  <comment><![CDATA[TRIG_II init command queue]]></comment>
</arr>

<arr>
  <name>BUF_TRIG_II_ACQ</name>
  <n>375</n>
  <idx>4</idx>
  <comment><![CDATA[TRIG_II acq command queue]]></comment>
</arr>

<arr>
  <name>WS_1_SETTING</name>
  <n>5</n>
  <idx>5</idx>
  <comment><![CDATA[Define the Working Schedule #1 values in ms /RO]]></comment>
</arr>

<arr>
  <name>RM_RATE_METER_S1_TRH</name>
  <n>2</n>
  <idx>6</idx>
  <comment><![CDATA[Rate meter s1  register TRH.used to toggle A/B mode in WS3 mode. the index of the array is related to the current ACQ mode (0=A to B,1=B to A) /RO]]></comment>
</arr>

<arr>
  <name>PWR_IPM_CONF</name>
  <n>6</n>
  <idx>7</idx>
  <comment><![CDATA[IMP desired configuration for initial poweron 6 bitmask /RO]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_ON_MAX</name>
  <n>6</n>
  <idx>8</idx>
  <comment><![CDATA[ADC min voltage values if ON /RO]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_ON_MIN</name>
  <n>6</n>
  <idx>9</idx>
  <comment><![CDATA[ADC min voltage values if ON /RO]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_OFF_MAX</name>
  <n>6</n>
  <idx>10</idx>
  <comment><![CDATA[ADC min voltage values if OFF /RO]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_OFF_MIN</name>
  <n>6</n>
  <idx>11</idx>
  <comment><![CDATA[ADC min voltage values if OFF /RO]]></comment>
</arr>

<arr>
  <name>TM_FILTER_OPERATION</name>
  <n>78</n>
  <idx>12</idx>
  <comment><![CDATA[low level telemetry filter operation: 0->apply no filter 1->set value 2->ORed mask 3->ANDed mask /RO]]></comment>
</arr>

<arr>
  <name>TM_FILTER_VALUE</name>
  <n>78</n>
  <idx>13</idx>
  <comment><![CDATA[low level telemetry filted values /RO]]></comment>
</arr>

<arr>
  <name>BUF_TB_SET_ALARM_MASK</name>
  <n>2</n>
  <idx>14</idx>
  <comment><![CDATA[TRG queue]]></comment>
</arr>

<arr>
  <name>BUF_TB_SET_PMT_MASK</name>
  <n>3</n>
  <idx>15</idx>
  <comment><![CDATA[TRG queue]]></comment>
</arr>

<arr>
  <name>BUF_TB_SET_S4_CAL_MASK</name>
  <n>2</n>
  <idx>16</idx>
  <comment><![CDATA[TRG queue]]></comment>
</arr>

<arr>
  <name>BUF_TB_SET_BUSY_MASK_IDAQ_HOT</name>
  <n>5</n>
  <idx>17</idx>
  <comment><![CDATA[ ]]></comment>
</arr>

<arr>
  <name>BUF_TB_SET_BUSY_MASK_IDAQ_COLD</name>
  <n>5</n>
  <idx>18</idx>
  <comment><![CDATA[ ]]></comment>
</arr>

<arr>
  <name>TRK_LOAD_PRG</name>
  <n>2</n>
  <idx>19</idx>
  <comment><![CDATA[The way the DSP program is loaded /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_PROGRAM</name>
  <n>3000</n>
  <idx>20</idx>
  <comment><![CDATA[TRK DSP Program /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_TRAILER_PRG_0</name>
  <n>3</n>
  <idx>21</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 0 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_TRAILER_PRG_1</name>
  <n>3</n>
  <idx>22</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_TRAILER_PRG_2</name>
  <n>3</n>
  <idx>23</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_TRAILER_PRG_3</name>
  <n>3</n>
  <idx>24</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_TRAILER_PRG_4</name>
  <n>3</n>
  <idx>25</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_TRAILER_PRG_5</name>
  <n>3</n>
  <idx>26</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 5 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_0</name>
  <n>10</n>
  <idx>27</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_1</name>
  <n>10</n>
  <idx>28</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_2</name>
  <n>10</n>
  <idx>29</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_3</name>
  <n>10</n>
  <idx>30</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_4</name>
  <n>10</n>
  <idx>31</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_5</name>
  <n>10</n>
  <idx>32</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_0</name>
  <n>10</n>
  <idx>33</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_1</name>
  <n>10</n>
  <idx>34</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_2</name>
  <n>10</n>
  <idx>35</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_3</name>
  <n>10</n>
  <idx>36</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_4</name>
  <n>10</n>
  <idx>37</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_5</name>
  <n>10</n>
  <idx>38</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_COMP_0</name>
  <n>3</n>
  <idx>39</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_0</name>
  <n>3</n>
  <idx>40</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_COMP_1</name>
  <n>3</n>
  <idx>41</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_1</name>
  <n>3</n>
  <idx>42</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_COMP_2</name>
  <n>3</n>
  <idx>43</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_2</name>
  <n>3</n>
  <idx>44</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_COMP_3</name>
  <n>3</n>
  <idx>45</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_3</name>
  <n>3</n>
  <idx>46</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_COMP_4</name>
  <n>3</n>
  <idx>47</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_4</name>
  <n>3</n>
  <idx>48</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_COMP_5</name>
  <n>3</n>
  <idx>49</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_5</name>
  <n>3</n>
  <idx>50</idx>
  <comment><![CDATA[TRK command queue /RO]]></comment>
</arr>

<arr>
  <name>CAL_COUNT</name>
  <n>4</n>
  <idx>51</idx>
  <comment><![CDATA[defines the calorimeter read out repetitions /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I211</name>
  <n>2</n>
  <idx>52</idx>
  <comment><![CDATA[write fpga /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I221</name>
  <n>2</n>
  <idx>53</idx>
  <comment><![CDATA[write fpga /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I231</name>
  <n>2</n>
  <idx>54</idx>
  <comment><![CDATA[write fpga /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_DSP_MEM_I41</name>
  <n>3176</n>
  <idx>55</idx>
  <comment><![CDATA[dsp prog i41 /R0]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_DSP_MEM_I42</name>
  <n>2723</n>
  <idx>56</idx>
  <comment><![CDATA[dsp prog i42 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_DSP_MEM_I43</name>
  <n>11</n>
  <idx>57</idx>
  <comment><![CDATA[dsp prog i43 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_READ_DSP_MEM_C31</name>
  <n>8</n>
  <idx>58</idx>
  <comment><![CDATA[dsp prog c31 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_READ_DSP_MEM_C32</name>
  <n>8</n>
  <idx>59</idx>
  <comment><![CDATA[dsp prog c32 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_1</name>
  <n>2</n>
  <idx>60</idx>
  <comment><![CDATA[write fpga i241_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_2</name>
  <n>2</n>
  <idx>61</idx>
  <comment><![CDATA[write fpga i241_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_3</name>
  <n>2</n>
  <idx>62</idx>
  <comment><![CDATA[write fpga i241_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_4</name>
  <n>2</n>
  <idx>63</idx>
  <comment><![CDATA[write fpga i241_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_1</name>
  <n>2</n>
  <idx>64</idx>
  <comment><![CDATA[write fpga i251_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_2</name>
  <n>2</n>
  <idx>65</idx>
  <comment><![CDATA[write fpga i251_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_3</name>
  <n>2</n>
  <idx>66</idx>
  <comment><![CDATA[write fpga i251_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_4</name>
  <n>2</n>
  <idx>67</idx>
  <comment><![CDATA[write fpga i251_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_1</name>
  <n>2</n>
  <idx>68</idx>
  <comment><![CDATA[write fpga i261_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_2</name>
  <n>2</n>
  <idx>69</idx>
  <comment><![CDATA[write fpga i261_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_3</name>
  <n>2</n>
  <idx>70</idx>
  <comment><![CDATA[write fpga i261_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_4</name>
  <n>2</n>
  <idx>71</idx>
  <comment><![CDATA[write fpga i261_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_1</name>
  <n>2</n>
  <idx>72</idx>
  <comment><![CDATA[write fpga i260_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_2</name>
  <n>2</n>
  <idx>73</idx>
  <comment><![CDATA[write fpga i260_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_3</name>
  <n>2</n>
  <idx>74</idx>
  <comment><![CDATA[write fpga i260_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_4</name>
  <n>2</n>
  <idx>75</idx>
  <comment><![CDATA[write fpga i260_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_1</name>
  <n>2</n>
  <idx>76</idx>
  <comment><![CDATA[write fpga i311_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_2</name>
  <n>2</n>
  <idx>77</idx>
  <comment><![CDATA[write fpga i311_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_3</name>
  <n>2</n>
  <idx>78</idx>
  <comment><![CDATA[write fpga i311_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_4</name>
  <n>2</n>
  <idx>79</idx>
  <comment><![CDATA[write fpga i311_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_1</name>
  <n>2</n>
  <idx>80</idx>
  <comment><![CDATA[write fpga i310_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_2</name>
  <n>2</n>
  <idx>81</idx>
  <comment><![CDATA[write fpga i310_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_3</name>
  <n>2</n>
  <idx>82</idx>
  <comment><![CDATA[write fpga i310_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_4</name>
  <n>2</n>
  <idx>83</idx>
  <comment><![CDATA[write fpga i310_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I321</name>
  <n>2</n>
  <idx>84</idx>
  <comment><![CDATA[write fpga i321 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_1</name>
  <n>2</n>
  <idx>85</idx>
  <comment><![CDATA[write fpga i331_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_2</name>
  <n>2</n>
  <idx>86</idx>
  <comment><![CDATA[write fpga i331_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_3</name>
  <n>2</n>
  <idx>87</idx>
  <comment><![CDATA[write fpga i331_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_4</name>
  <n>2</n>
  <idx>88</idx>
  <comment><![CDATA[write fpga i331_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_OFF</name>
  <n>2</n>
  <idx>89</idx>
  <comment><![CDATA[write fpga reg off /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_1</name>
  <n>2</n>
  <idx>90</idx>
  <comment><![CDATA[write fpga i341_1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_2</name>
  <n>2</n>
  <idx>91</idx>
  <comment><![CDATA[write fpga i341_2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_3</name>
  <n>2</n>
  <idx>92</idx>
  <comment><![CDATA[write fpga i341_3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_4</name>
  <n>2</n>
  <idx>93</idx>
  <comment><![CDATA[write fpga i341_4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_1_SET_DAQ</name>
  <n>35</n>
  <idx>94</idx>
  <comment><![CDATA[SET DAQ command /RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_2_SET_DAQ</name>
  <n>35</n>
  <idx>95</idx>
  <comment><![CDATA[SET DAQ command /RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_SEND_DSP_PROG1</name>
  <n>5010</n>
  <idx>96</idx>
  <comment><![CDATA[DSP Program 1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_1_SEND_DSP_PROG2</name>
  <n>3800</n>
  <idx>97</idx>
  <comment><![CDATA[ /RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_2_SEND_DSP_PROG2</name>
  <n>3800</n>
  <idx>98</idx>
  <comment><![CDATA[ /RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_2_WRITE_REG</name>
  <n>15</n>
  <idx>99</idx>
  <comment><![CDATA[/RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_1_WRITE_REG</name>
  <n>15</n>
  <idx>100</idx>
  <comment><![CDATA[/RO]]></comment>
</arr>

<arr>
  <name>BUF_AC_READ_DSP_MEM</name>
  <n>3</n>
  <idx>101</idx>
  <comment><![CDATA[ /RO]]></comment>
</arr>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_1</name>
  <n>2</n>
  <idx>102</idx>
  <comment><![CDATA[TOF set THR front end 1 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_2</name>
  <n>2</n>
  <idx>103</idx>
  <comment><![CDATA[TOF set THR front end 2 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_3</name>
  <n>2</n>
  <idx>104</idx>
  <comment><![CDATA[TOF set THR front end 3 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_4</name>
  <n>2</n>
  <idx>105</idx>
  <comment><![CDATA[TOF set THR front end 4 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_5</name>
  <n>2</n>
  <idx>106</idx>
  <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
</arr>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_6</name>
  <n>2</n>
  <idx>107</idx>
  <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
</arr>

<arr>
  <name>TOF_PLAN</name>
  <n>6</n>
  <idx>108</idx>
  <comment><![CDATA[TOF Plans selectors /RO]]></comment>
</arr>

<arr>
  <name>PM_PERIODIC_DELAY</name>
  <n>4</n>
  <idx>109</idx>
  <comment><![CDATA[Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations, /RO]]></comment>
</arr>

<arr>
  <name>PSB_COMMANDS</name>
  <n>29</n>
  <idx>110</idx>
  <comment><![CDATA[Command for PSB /RO]]></comment>
</arr>

<arr>
  <name>PSB_CALO_FE_ON</name>
  <n>4</n>
  <idx>111</idx>
  <comment><![CDATA[Command for PSB /RO]]></comment>
</arr>

<arr>
  <name>PSB_CALO_FE_OFF</name>
  <n>4</n>
  <idx>112</idx>
  <comment><![CDATA[Command for PSB /RO]]></comment>
</arr>

<arr>
  <name>PSB_CALO_FE</name>
  <n>4</n>
  <idx>113</idx>
  <comment><![CDATA[Command for PSB /RO]]></comment>
</arr>

<arr>
  <name>HVB_COMMANDS</name>
  <n>12</n>
  <idx>114</idx>
  <comment><![CDATA[Command for HVB /RO]]></comment>
</arr>

<arr>
  <name>TSB_BOARD_OK</name>
  <n>2</n>
  <idx>115</idx>
  <comment><![CDATA[User TSB Board no 0/1 flags /RO]]></comment>
</arr>

</arrxml>
