# Pamela General Parameters Table

### this file have been generated: Tue May 17 09:26:57 2005

## NAME | ## TYPE | ## DEFAULT | ## COMMENT
LOG_MASK | ARR [113] |  | log level mask for each module /RO
LU_WRITE_ON_UART | VAR | 1 | enable[1]/disable[0] the UART writing /RO
VERBOSE_DEBUG | VAR | 0 | Verbose Debug mode
DOWNLOAD_HEADER | VAR | 0 | download counter, to be written in Download header info /RW-E2P
KHB_ALARM_REG_LOW_LEVEL_MASK | VAR | 0 | mask of KHB Alarm register to be low-level masked /RO
KHB_STATUS_REG_LOW_LEVEL_MASK | VAR | 0 | mask of KHB status register to be low-level masked /RO
PULSER_ACTION | VAR | 0 | pulser action at startup; [0=none,1=Reset,2:0.25Hz,3:100Hz] /RO
N_BOOT | VAR | 0 | Boot Counter /RW-E2P
THERMISTORS_CHECK | VAR | 1 | Check if thermistor are going to be checked /RO
THERM_MASK | VAR | 65535 | Thermistors mask /RO
THERM_LOW | ARR [16] |  | Thermistor low limit /RO
THERM_HIGH | ARR [16] |  | Thermistor high limit /RO
IPM_VOLTAGES_CHECK | VAR | 1 | Check if ipm are going to be checked /RO
KHB_IDAQ_CHECK | VAR | 1 | Check if khb&idaq are going to be checked /RO
NTRIG | VAR | 3 | Max Number of Lacks of Triggers /RO
TRIG | VAR | 0 | Counter of lacks of triggers /RW
CONF | TAB [5][6] |  | active sensors - first dimention is the number of the incrementing configuration. second dimention is the number of FE /RO
CONF_SEL | VAR | 0 | active sensor selector /RW
CONFOK | VAR | 1 | whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON /RO
OFF | VAR | 0 | Counter of ON/OFF /RW
NOFF | VAR | 2 | Max Number of ON/OFF /RO
NRES | VAR | 6 | Max number of reset /RO
RES | VAR | 0 | Counter of reset /RW
WATCHDOG_RESET_DISABLE | VAR | 0 | disable watchdog reset: only for debugging!
NFAILED_POWER_ON | VAR | 3 | max number of failed power_on, before STOP&WAIT /RO
AUTO_RM_MODE | VAR | 0 | define the Automatic Mode for RM /RO
AUTO_SCM_MODE | VAR | 1 | define the Automatic Mode for scm /RO
MASK_ACQ_ALARM | VAR | 65535 | Alarm mask /RO
GOM_DURING_ALARM | VAR | 0 | General operation mode during alarm revelation /RW
PM_FORCE_RUNNING_TIMEOUT | VAR | 3600000 | waiting for start select mode before force go to running
PAMELA_ON | VAR | 0 | Pamela status [0=OFF-1:OFF] /RW
N_CALIB | VAR | 0 | Counter of calibratrion since start up /RW
AC_1_ON | VAR | 0 | AC 1 on from initialization /RW
AC_2_ON | VAR | 0 | AC 2 on from initialization /RW
POWER_MODE | VAR | 1 | Power mode of PAMELA /RW
TRIG_II | VAR | 0 | TRIGGER II level mode on/off /RO
BUF_LEN_TRIG_II_INIT | VAR | 199 | TRIG_II init command queue
BUF_TRIG_II_INIT | ARR [3750] |  | TRIG_II init command queue
BUF_LEN_TRIG_II_ACQ | VAR | 561 | TRIG_II acq command queue
BUF_TRIG_II_ACQ | ARR [375] |  | TRIG_II acq command queue
EXP64_MODE | VAR | 1 | if TRUE, working in exp 64 mode /RO
EXP64_MODE_DELAY | VAR | 0 | delay for exp 64 mode acquiring /RO
MH_END_OF_DOWNLOAD_TIMEOUT | VAR | 60000 | time out of the end of download /RO
PM_STOP_RUNMANAGER_TIMEOUT | VAR | 1000 | the maximu time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager /RO
PM_STOP_RUNMANAGER_TIMES_RETRY | VAR | 5 | The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle. /RO
PM_N_ORBIT_CALIB | VAR | 1 | Number of orbits per calibration /RO
WS_1_SETTING | ARR [5] |  | Define the Working Schedule #1 values in ms /RO
WS_TIME_ORBIT | VAR | 5670000 | The duration in millisencond of the full orbit in ms /RO
WS_FAVOURITE_WS | VAR | 0 | The Favourite Pamela Working Schedule /RO
RM_N_TRIES_PREPARE_PAGE | VAR | 100 | Number of attempts to try to exec the prepar page before exit from the run procedure with an error /RO
RM_TRIES_PREPARE_PAGE_SLEEP | VAR | 2 | Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure /RO
RM_WS3_TIMER_FIRE_AFTER | VAR | 8000 | Time to wait for the WS3 timer to fire /RO
RM_RATE_METER_S1_TRH | ARR [2] |  | Rate meter s1 register TRH.used to toggle A/B mode in WS3 mode. the index of the array is related to the current ACQ mode (0=A to B,1=B to A) /RO
RM_TIME_MAX_RUN | VAR | 1800000 | Max duration for an ordinary Run in milliseconds /RO
RM_TIME_SPECIAL_RUN | VAR | 100000 | duration for the special run in milliseconds /RO
RM_ACQCHECK_PERIOD | VAR | 1000 | period of acquisition check in milliseconds /RO
RM_FLUSH_TIMEOUT | VAR | 20000 | timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT /RO
RM_NO_FLUSH_PARAM_DUMP | VAR | 200 | Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never. /RO
RM_DUMP_ALL_PARAMS | VAR | 0 | dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs /RO
RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ | VAR | 70 | number of release busy inserted in the ACQ command queue in After_Calib mode /RO
PWR_IPM_CONF | ARR [6] |  | IMP desired configuration for initial poweron 6 bitmask /RO
PWR_WAIT_BEFORE_SENDTC | VAR | 110 | time to wait before send 2 successive HL /RO
PWR_CMD2PSB_DELAY | VAR | 100 | time to wait before every CMD2PSB
PWR_TRB_READ_ATTEMPTS | VAR | 10 | number of attempts to sent a command to the TRB before a timeout /RO
PWR_KHB_INITBOARD_TWICE_DELAY | VAR | 500 | milliseconds to wait between two KHB Init Board in PWR_DcdcON /RO
PWR_IPM_WAIT_OK_N_ATTEMPT | VAR | 150 | attempts of ipm check ok at power on /RO
PWR_IPM_WAIT_OK_DELAY_ATTEMPT | VAR | 1000 | attempts of ipm check ok at power on /RO
PWR_VOLTAGE_N_ATTEMPT | VAR | 10 | no of millisecond to wait in VOLTAGE IPM procedure /RO
PWR_VOLTAGE_DELAY_ATTEMPT | VAR | 1000 | no of millisecond to wain in VOLTAGE IPM procedure /RO
PWR_VOLTAGE_IPM_RANGE_ON_MAX | ARR [6] |  | ADC min voltage values if ON /RO
PWR_VOLTAGE_IPM_RANGE_ON_MIN | ARR [6] |  | ADC min voltage values if ON /RO
PWR_VOLTAGE_IPM_RANGE_OFF_MAX | ARR [6] |  | ADC min voltage values if OFF /RO
PWR_VOLTAGE_IPM_RANGE_OFF_MIN | ARR [6] |  | ADC min voltage values if OFF /RO
PWR_TRB1_SET | VAR | 16383 | trb 1 setting /RO
PWR_TRB2_SET | VAR | 16383 | trb 2 setting /RO
PWR_TRB_SET_DELAY | VAR | 20 | delay after trb set cmd /RO
PWR_TRB_READ_DELAY | VAR | 20 | delay after trb read cmd /RO
PWR_IPM_ACTION | TAB [3][64] |  | Main Table for actions to be done in IPM Check procedure
HB_N_ATTEMPT_WRITE2PIF | VAR | 2 | Number of attempt to write on PIF after return an error /RO
HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF | VAR | 100 | Waint time after a failed attempt on PIF write /RO
HB_WRITE2PIF_TIMEOUT | VAR | 1000 | timeout time time to wait a sketchboard free in Write2PIF /RO
HB_ALMOST_FULL | VAR | 80 | says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage. /RM
TM_FILTER_OPERATION | ARR [78] |  | low level telemetry filter operation: 0->apply no filter 1->set value 2->ORed mask 3->ANDed mask /RO
TM_FILTER_VALUE | ARR [78] |  | low level telemetry filted values /RO
TM_VRL_SUSPEND_HCL | VAR | 110 | wait time between two HCL commands for the VRL /RO
TM_VRL_SUSPEND_BEFORE_START | VAR | 1 | wait time before start VRL /RO
DAQ_EVENT_RECEIVE_TIMEOUT | VAR | 20000 | PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply /RO
DAQ_WAITFREECMDIF_N | VAR | 4 | Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched /RO
TRB_OK | VAR | 1 | Use ON_OFF tracker in ACQ /RO
TRIGGER_MODE_A | VAR | 1 | Trigger type for acq mode A /RO
TRIGGER_MODE_B | VAR | 3 | Trigger type for acq mode B /RO
TRIGGER_BUSY_CONTROL | VAR | 0 | Select the check mask of the busy alaarm /RO
TB_LINK | VAR | 1 | Trigger Board to use 1 or 2 /RO
TB_LINK_CUSTOM | VAR | 1 | Trigger Board CUSTOMto use 1 or 2 /RO
BUF_LEN_TB_SET_ALARM_MASK | VAR | 8 | TRG queue
BUF_TB_SET_ALARM_MASK | ARR [2] |  | TRG queue
BUF_LEN_TB_SET_PMT_MASK | VAR | 12 | TRG queue
BUF_TB_SET_PMT_MASK | ARR [3] |  | TRG queue
BUF_LEN_TB_SET_S4_CAL_MASK | VAR | 7 | TRG queue
BUF_TB_SET_S4_CAL_MASK | ARR [2] |  | TRG queue
BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT | VAR | 9 |
BUF_TB_SET_BUSY_MASK_IDAQ_HOT | ARR [5] |  |
BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD | VAR | 9 |
BUF_TB_SET_BUSY_MASK_IDAQ_COLD | ARR [5] |  |
TRK_OK | VAR | 1 | Use ON_OFF tracker in ACQ /RO
TRK_DSP_OK | TAB [2][6] |  | Tracker dsp ON_OFF in ACQ /RO
TRK_CALIB_MODE | VAR | 1 | Tracker calibration mode /RO
TRK_TIME_SHORT | VAR | 13 | Tracker wait loop for 128 loop /RO
TRK_TIME_LONG | VAR | 0 | Tracker wait loop for 8 loop /RO
TRK_DSP_MASK | TAB [2][6] |  | Traker dsp mask /RO
TRK_LOAD_PRG | ARR [2] |  | The way the DSP program is loaded /RO
TRK_CALIB_INIT | VAR | 104 | modality of calibration /RO
TRK_NLOOP | VAR | 12 | macro loop number /RO
TRK_PED_MIN_0 | TAB [3][6] |  | Tracker 0 ped min value /RO
TRK_PED_MIN_1 | TAB [3][6] |  | Tracker 1 ped min value /RO
TRK_PED_MAX_0 | TAB [3][6] |  | Tracker 0 ped max value /RO
TRK_PED_MAX_1 | TAB [3][6] |  | Tracker 1 ped max value /RO
TRK_SIG_MIN_0 | TAB [3][6] |  | Tracker 0 sig min value /RO
TRK_SIG_MIN_1 | TAB [3][6] |  | Tracker 1 sig min value /RO
TRK_SIG_MAX_0 | TAB [3][6] |  | Tracker 0 sig min value /RO
TRK_SIG_MAX_1 | TAB [3][6] |  | Tracker 1 sig min value /RO
TRK_BAD_MAX_0 | TAB [3][6] |  | Tracker 0 bad max value /RO
TRK_BAD_MAX_1 | TAB [3][6] |  | Tracker 1 bad max value /RO
BUF_LEN_TRK_PROGRAM | VAR | 10644 | TRK DSP Program /RO
BUF_TRK_PROGRAM | ARR [3000] |  | TRK DSP Program /RO
BUF_LEN_TRK_TRAILER_PRG_0 | VAR | 1 | TRK DSP Program Trailer for DSP 0 /RO
BUF_TRK_TRAILER_PRG_0 | ARR [3] |  | TRK DSP Program Trailer for DSP 0 /RO
BUF_LEN_TRK_TRAILER_PRG_1 | VAR | 1 | TRK DSP Program Trailer for DSP 1 /RO
BUF_TRK_TRAILER_PRG_1 | ARR [3] |  | TRK DSP Program Trailer for DSP 1 /RO
BUF_LEN_TRK_TRAILER_PRG_2 | VAR | 1 | TRK DSP Program Trailer for DSP 2 /RO
BUF_TRK_TRAILER_PRG_2 | ARR [3] |  | TRK DSP Program Trailer for DSP 2 /RO
BUF_LEN_TRK_TRAILER_PRG_3 | VAR | 1 | TRK DSP Program Trailer for DSP 3 /RO
BUF_TRK_TRAILER_PRG_3 | ARR [3] |  | TRK DSP Program Trailer for DSP 3 /RO
BUF_LEN_TRK_TRAILER_PRG_4 | VAR | 1 | TRK DSP Program Trailer for DSP 4 /RO
BUF_TRK_TRAILER_PRG_4 | ARR [3] |  | TRK DSP Program Trailer for DSP 4 /RO
BUF_LEN_TRK_TRAILER_PRG_5 | VAR | 1 | TRK DSP Program Trailer for DSP 5 /RO
BUF_TRK_TRAILER_PRG_5 | ARR [3] |  | TRK DSP Program Trailer for DSP 5 /RO
BUF_LEN_TRK_NUMBER_DSP_1_0 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_1_0 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_1_1 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_1_1 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_1_2 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_1_2 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_1_3 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_1_3 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_1_4 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_1_4 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_1_5 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_1_5 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_2_0 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_2_0 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_2_1 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_2_1 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_2_2 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_2_2 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_2_3 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_2_3 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_2_4 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_2_4 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_NUMBER_DSP_2_5 | VAR | 30 | TRK command queue /RO
BUF_TRK_NUMBER_DSP_2_5 | ARR [10] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_COMP_0 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_COMP_0 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_SPEC_0 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_SPEC_0 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_COMP_1 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_COMP_1 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_SPEC_1 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_SPEC_1 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_COMP_2 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_COMP_2 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_SPEC_2 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_SPEC_2 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_COMP_3 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_COMP_3 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_SPEC_3 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_SPEC_3 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_COMP_4 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_COMP_4 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_SPEC_4 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_SPEC_4 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_COMP_5 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_COMP_5 | ARR [3] |  | TRK command queue /RO
BUF_LEN_TRK_OPMODE_SPEC_5 | VAR | 10 | TRK command queue /RO
BUF_TRK_OPMODE_SPEC_5 | ARR [3] |  | TRK command queue /RO
S4_OK | VAR | 1 | S4 enable/disable /RO
S4_TRH | VAR | 16384 | S4 command /RO
S4_ATTEMPT | VAR | 0 | S4 force check /RO
S4_WORKING | VAR | 1 | check if S4 is working or not /RO
CAL_UPLOAD_CAL_FE_MASK | VAR | 15 | Defines the working read-out of calorimeter /RO
CAL_UPLOAD_CAL_DSP_MASK | VAR | 15 | Defines the workings dsps of calorimeter /RO
CAL_VCAL | VAR | 32773 | Variable modified by pulse calibration /RW
CAL_CH | VAR | 1 | Variable modified by pulse calibration /RW
CAL_TEMP | VAR | 5 | Maximum calorimeter temperature alarms /RO
CAL_COUNT | ARR [4] |  | defines the calorimeter read out repetitions /RO
CAL_OK | VAR | 1 | calo ON_OFF in ACQ /RW
CAL_CHECK_FE | VAR | 0 | calo check FE /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I211 | VAR | 8 | write fpga /RO
BUF_CAL_WRITE_FPGA_REG_I211 | ARR [2] |  | write fpga /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I221 | VAR | 8 | write fpga /RO
BUF_CAL_WRITE_FPGA_REG_I221 | ARR [2] |  | write fpga /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I231 | VAR | 8 | write fpga /RO
BUF_CAL_WRITE_FPGA_REG_I231 | ARR [2] |  | write fpga /RO
BUF_LEN_CAL_WRITE_DSP_MEM_I41 | VAR | 4234 | dsp prog i41 /R0
BUF_CAL_WRITE_DSP_MEM_I41 | ARR [3176] |  | dsp prog i41 /R0
BUF_LEN_CAL_WRITE_DSP_MEM_I42 | VAR | 3646 | dsp prog i42 /RO
BUF_CAL_WRITE_DSP_MEM_I42 | ARR [2723] |  | dsp prog i42 /RO
BUF_LEN_CAL_WRITE_DSP_MEM_I43 | VAR | 14 | dsp prog i43 /RO
BUF_CAL_WRITE_DSP_MEM_I43 | ARR [11] |  | dsp prog i43 /RO
BUF_LEN_CAL_READ_DSP_MEM_C31 | VAR | 10 | dsp prog c31 /RO
BUF_CAL_READ_DSP_MEM_C31 | ARR [8] |  | dsp prog c31 /RO
BUF_LEN_CAL_READ_DSP_MEM_C32 | VAR | 10 | dsp prog c32 /RO
BUF_CAL_READ_DSP_MEM_C32 | ARR [8] |  | dsp prog c32 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I241_1 | VAR | 8 | write fpga i241_1 /RO
BUF_CAL_WRITE_FPGA_REG_I241_1 | ARR [2] |  | write fpga i241_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I241_2 | VAR | 8 | write fpga i241_2 /RO
BUF_CAL_WRITE_FPGA_REG_I241_2 | ARR [2] |  | write fpga i241_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I241_3 | VAR | 8 | write fpga i241_3 /RO
BUF_CAL_WRITE_FPGA_REG_I241_3 | ARR [2] |  | write fpga i241_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I241_4 | VAR | 8 | write fpga i241_4 /RO
BUF_CAL_WRITE_FPGA_REG_I241_4 | ARR [2] |  | write fpga i241_4 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I251_1 | VAR | 8 | write fpga i251_1 /RO
BUF_CAL_WRITE_FPGA_REG_I251_1 | ARR [2] |  | write fpga i251_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I251_2 | VAR | 8 | write fpga i251_2 /RO
BUF_CAL_WRITE_FPGA_REG_I251_2 | ARR [2] |  | write fpga i251_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I251_3 | VAR | 8 | write fpga i251_3 /RO
BUF_CAL_WRITE_FPGA_REG_I251_3 | ARR [2] |  | write fpga i251_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I251_4 | VAR | 8 | write fpga i251_4 /RO
BUF_CAL_WRITE_FPGA_REG_I251_4 | ARR [2] |  | write fpga i251_4 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I261_1 | VAR | 8 | write fpga i261_1 /RO
BUF_CAL_WRITE_FPGA_REG_I261_1 | ARR [2] |  | write fpga i261_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I261_2 | VAR | 8 | write fpga i261_2 /RO
BUF_CAL_WRITE_FPGA_REG_I261_2 | ARR [2] |  | write fpga i261_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I261_3 | VAR | 8 | write fpga i261_3 /RO
BUF_CAL_WRITE_FPGA_REG_I261_3 | ARR [2] |  | write fpga i261_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I261_4 | VAR | 8 | write fpga i261_4 /RO
BUF_CAL_WRITE_FPGA_REG_I261_4 | ARR [2] |  | write fpga i261_4 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I260_1 | VAR | 8 | write fpga i260_1 /RO
BUF_CAL_WRITE_FPGA_REG_I260_1 | ARR [2] |  | write fpga i260_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I260_2 | VAR | 8 | write fpga i260_2 /RO
BUF_CAL_WRITE_FPGA_REG_I260_2 | ARR [2] |  | write fpga i260_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I260_3 | VAR | 8 | write fpga i260_3 /RO
BUF_CAL_WRITE_FPGA_REG_I260_3 | ARR [2] |  | write fpga i260_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I260_4 | VAR | 8 | write fpga i260_4 /RO
BUF_CAL_WRITE_FPGA_REG_I260_4 | ARR [2] |  | write fpga i260_4 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I311_1 | VAR | 8 | write fpga i311_1 /RO
BUF_CAL_WRITE_FPGA_REG_I311_1 | ARR [2] |  | write fpga i311_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I311_2 | VAR | 8 | write fpga i311_2 /RO
BUF_CAL_WRITE_FPGA_REG_I311_2 | ARR [2] |  | write fpga i311_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I311_3 | VAR | 8 | write fpga i311_3 /RO
BUF_CAL_WRITE_FPGA_REG_I311_3 | ARR [2] |  | write fpga i311_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I311_4 | VAR | 8 | write fpga i311_4 /RO
BUF_CAL_WRITE_FPGA_REG_I311_4 | ARR [2] |  | write fpga i311_4 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I310_1 | VAR | 8 | write fpga i310_1 /RO
BUF_CAL_WRITE_FPGA_REG_I310_1 | ARR [2] |  | write fpga i310_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I310_2 | VAR | 8 | write fpga i310_2 /RO
BUF_CAL_WRITE_FPGA_REG_I310_2 | ARR [2] |  | write fpga i310_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I310_3 | VAR | 8 | write fpga i310_3 /RO
BUF_CAL_WRITE_FPGA_REG_I310_3 | ARR [2] |  | write fpga i310_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I310_4 | VAR | 8 | write fpga i310_4 /RO
BUF_CAL_WRITE_FPGA_REG_I310_4 | ARR [2] |  | write fpga i310_4 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I321 | VAR | 8 | write fpga i321 /RO
BUF_CAL_WRITE_FPGA_REG_I321 | ARR [2] |  | write fpga i321 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I331_1 | VAR | 8 | write fpga i331_1 /RO
BUF_CAL_WRITE_FPGA_REG_I331_1 | ARR [2] |  | write fpga i331_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I331_2 | VAR | 8 | write fpga i331_2 /RO
BUF_CAL_WRITE_FPGA_REG_I331_2 | ARR [2] |  | write fpga i331_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I331_3 | VAR | 8 | write fpga i331_3 /RO
BUF_CAL_WRITE_FPGA_REG_I331_3 | ARR [2] |  | write fpga i331_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I331_4 | VAR | 8 | write fpga i331_4 /RO
BUF_CAL_WRITE_FPGA_REG_I331_4 | ARR [2] |  | write fpga i331_4 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_OFF | VAR | 8 | write fpga reg off /RO
BUF_CAL_WRITE_FPGA_REG_OFF | ARR [2] |  | write fpga reg off /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I341_1 | VAR | 8 | write fpga i341_1 /RO
BUF_CAL_WRITE_FPGA_REG_I341_1 | ARR [2] |  | write fpga i341_1 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I341_2 | VAR | 8 | write fpga i341_2 /RO
BUF_CAL_WRITE_FPGA_REG_I341_2 | ARR [2] |  | write fpga i341_2 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I341_3 | VAR | 8 | write fpga i341_3 /RO
BUF_CAL_WRITE_FPGA_REG_I341_3 | ARR [2] |  | write fpga i341_3 /RO
BUF_LEN_CAL_WRITE_FPGA_REG_I341_4 | VAR | 8 | write fpga i341_4 /RO
BUF_CAL_WRITE_FPGA_REG_I341_4 | ARR [2] |  | write fpga i341_4 /RO
AC_1_OK | VAR | 1 | AC ON_OFF in ACQ /RW
AC_2_OK | VAR | 1 | AC ON_OFF in ACQ /RW
AC_1_CHECK | VAR | 0 | AC check /RO
AC_2_CHECK | VAR | 0 | AC check /RO
AC_LOOP | VAR | 3 | AC max loop /RO
AC_LOOP2 | VAR | 3 | AC max loop 2 /RO
BUF_LEN_AC_1_SET_DAQ | VAR | 132 | SET DAQ command /RO
BUF_AC_1_SET_DAQ | ARR [35] |  | SET DAQ command /RO
BUF_LEN_AC_2_SET_DAQ | VAR | 132 | SET DAQ command /RO
BUF_AC_2_SET_DAQ | ARR [35] |  | SET DAQ command /RO
BUF_LEN_AC_SEND_DSP_PROG1 | VAR | 17034 | DSP Program 1 /RO
BUF_AC_SEND_DSP_PROG1 | ARR [5010] |  | DSP Program 1 /RO
BUF_LEN_AC_1_SEND_DSP_PROG2 | VAR | 11156 | /RO
BUF_AC_1_SEND_DSP_PROG2 | ARR [3800] |  | /RO
BUF_LEN_AC_2_SEND_DSP_PROG2 | VAR | 11156 | /RO
BUF_AC_2_SEND_DSP_PROG2 | ARR [3800] |  | /RO
BUF_LEN_AC_2_WRITE_REG | VAR | 54 | /RO
BUF_AC_2_WRITE_REG | ARR [15] |  | /RO
BUF_LEN_AC_1_WRITE_REG | VAR | 54 | /RO
BUF_AC_1_WRITE_REG | ARR [15] |  | /RO
BUF_LEN_AC_READ_DSP_MEM | VAR | 10 | /RO
BUF_AC_READ_DSP_MEM | ARR [3] |  | /RO
BUF_LEN_TOF_WRITE_PMT_THR_1 | VAR | 7 | TOF set THR front end 1 /RO
BUF_TOF_WRITE_PMT_THR_1 | ARR [2] |  | TOF set THR front end 1 /RO
BUF_LEN_TOF_WRITE_PMT_THR_2 | VAR | 7 | TOF set THR front end 2 /RO
BUF_TOF_WRITE_PMT_THR_2 | ARR [2] |  | TOF set THR front end 2 /RO
BUF_LEN_TOF_WRITE_PMT_THR_3 | VAR | 7 | TOF set THR front end 3 /RO
BUF_TOF_WRITE_PMT_THR_3 | ARR [2] |  | TOF set THR front end 3 /RO
BUF_LEN_TOF_WRITE_PMT_THR_4 | VAR | 7 | TOF set THR front end 4 /RO
BUF_TOF_WRITE_PMT_THR_4 | ARR [2] |  | TOF set THR front end 4 /RO
BUF_LEN_TOF_WRITE_PMT_THR_5 | VAR | 7 | TOF set THR front end 5 /RO
BUF_TOF_WRITE_PMT_THR_5 | ARR [2] |  | TOF set THR front end 5 /RO
BUF_LEN_TOF_WRITE_PMT_THR_6 | VAR | 7 | TOF set THR front end 5 /RO
BUF_TOF_WRITE_PMT_THR_6 | ARR [2] |  | TOF set THR front end 5 /RO
TOF_OK | VAR | 1 | TOF ON_OFF in ACQ /RW
TOF_PLAN | ARR [6] |  | TOF Plans selectors /RO
ND_OK | VAR | 1 | ND ON_OFF in ACQ /RW
ND_ATTEMPT | VAR | 0 | Force ND in ACQ (1), unless ND_OK is FALSE /RO
ND_CMDS | VAR | 3 | Force ND in ACQ, unless ND_OK is FALSE /RO
PM_PERIODIC_DELAY | ARR [4] |  | Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations, /RO
SCM_TM_DO_CHECK_VALUES_FREQ | VAR | 1 | Do a Check on TM values every XXX Number of cyc acq done /RO
POWER_KHB | VAR | 0 | Select KHB board 0==>HOT else COLD
PSB_TRB_S9004_ALL_ON_DELAY | VAR | 1000 | milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on) /RO
PSB_TRB_BIAS_WAIT | VAR | 3000 | wait between bias TRB switch on/off /RO
PSB_COMMANDS | ARR [29] |  | Command for PSB /RO
PSB_CALO_FE_ON | ARR [4] |  | Command for PSB /RO
PSB_CALO_FE_OFF | ARR [4] |  | Command for PSB /RO
PSB_CALO_FE | ARR [4] |  | Command for PSB /RO
PSB_CALOFE_DELAY | VAR | 1000 | Delay before power on CALO 5.7 /RO
HV_OK | VAR | 1 | call HV settings after TRB setting at start-up /RO
HVB_COMMANDS | ARR [12] |  | Command for HVB /RO
TSB_BOARD_OK | ARR [2] |  | User TSB Board no 0/1 flags /RO
TSB_T_OK | VAR | 1 | Do TSB Temperature check /RO
TSB_B_OK | VAR | 1 | Do B-field TSB check /RO
ALLPAGEAVAIL_ATTEMPT | VAR | 50 | ATTEMP TO ALLPAGE AVAILABLE