
<rootparams>

<arr>
  <name>LOG_MASK</name>
  <n>113</n>
  <idx>0</idx>
  <comment><![CDATA[log level mask for each module]]></comment>
</arr>

<var>
  <name>LU_WRITE_ON_UART</name>
  <idx>0</idx> 
  <comment><![CDATA[enable/disable the UART writing]]></comment>
</var>

<var>
  <name>KHB_ALARM_REG_LOW_LEVEL_MASK</name>
  <idx>1</idx> 
  <comment><![CDATA[mask of KHB Alarm register to be low-level masked]]></comment>
</var>

<var>
  <name>KHB_STATUS_REG_LOW_LEVEL_MASK</name>
  <idx>2</idx> 
  <comment><![CDATA[mask of KHB status register to be low-level masked]]></comment>
</var>

<var>
  <name>N_BOOT</name>
  <idx>3</idx> 
  <comment><![CDATA[Boot Counter]]></comment>
</var>

<var>
  <name>THERMISTORS_CHECK</name>
  <idx>4</idx> 
  <comment><![CDATA[Check if thermistor are going to be checked]]></comment>
</var>

<var>
  <name>THERM_MASK</name>
  <idx>5</idx> 
  <comment><![CDATA[Thermistors mask]]></comment>
</var>

<var>
  <name>THERM_VAL</name>
  <idx>6</idx> 
  <comment><![CDATA[Maximum number of wrong themperature measures]]></comment>
</var>

<arr>
  <name>THERM_LOW</name>
  <n>16</n>
  <idx>1</idx>
  <comment><![CDATA[Thermistor low limit]]></comment>
</arr>

<arr>
  <name>THERM_HIGH</name>
  <n>16</n>
  <idx>2</idx>
  <comment><![CDATA[Thermistor high limit]]></comment>
</arr>

<var>
  <name>IPM_VOLTAGES_CHECK</name>
  <idx>7</idx> 
  <comment><![CDATA[Check if ipm are going to be checked]]></comment>
</var>

<var>
  <name>KHB_IDAQ_CHECK</name>
  <idx>8</idx> 
  <comment><![CDATA[Check if khb&idaq are going to be checked]]></comment>
</var>

<var>
  <name>NTRIG</name>
  <idx>9</idx> 
  <comment><![CDATA[Trig Counter]]></comment>
</var>

<tab>
  <name>CONF</name>
  <rows>5</rows>
  <cols>6</cols>
  <idx>0</idx>
  <comment><![CDATA[active sensors - first dimention is the number of the incrementing configuration. second dimention is the number of FE]]></comment>
</tab>

<var>
  <name>CONF_SEL</name>
  <idx>10</idx> 
  <comment><![CDATA[active sensor selector]]></comment>
</var>

<var>
  <name>NOFF</name>
  <idx>11</idx> 
  <comment><![CDATA[On Off Counter]]></comment>
</var>

<var>
  <name>CONFOK</name>
  <idx>12</idx> 
  <comment><![CDATA[whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON]]></comment>
</var>

<var>
  <name>OFF</name>
  <idx>13</idx> 
  <comment><![CDATA[Trig Counter]]></comment>
</var>

<var>
  <name>NFAILED_POWER_ON</name>
  <idx>14</idx> 
  <comment><![CDATA[max number of failed power_on, before STOP&WAIT]]></comment>
</var>

<var>
  <name>NRES</name>
  <idx>15</idx> 
  <comment><![CDATA[Max number of reset]]></comment>
</var>

<var>
  <name>RES</name>
  <idx>16</idx> 
  <comment><![CDATA[current number of reset]]></comment>
</var>

<var>
  <name>AUTO_RM_MODE</name>
  <idx>17</idx> 
  <comment><![CDATA[define the Automatic Mode]]></comment>
</var>

<var>
  <name>AUTO_SCM_MODE</name>
  <idx>18</idx> 
  <comment><![CDATA[define the Automatic Mode for scm]]></comment>
</var>

<var>
  <name>MASK_ACQ_ALARM</name>
  <idx>19</idx> 
  <comment><![CDATA[Alarm mask ]]></comment>
</var>

<var>
  <name>GOM_DURING_ALARM</name>
  <idx>20</idx> 
  <comment><![CDATA[General operation mode during alarm revelation]]></comment>
</var>

<var>
  <name>TRIG</name>
  <idx>21</idx> 
  <comment><![CDATA[Trigger counter]]></comment>
</var>

<var>
  <name>PAMELA_ON</name>
  <idx>22</idx> 
  <comment><![CDATA[Pamela status]]></comment>
</var>

<var>
  <name>N_CALIB</name>
  <idx>23</idx> 
  <comment><![CDATA[Number of calibratrion since start up]]></comment>
</var>

<var>
  <name>AC_1_ON</name>
  <idx>24</idx> 
  <comment><![CDATA[AC on]]></comment>
</var>

<var>
  <name>AC_2_ON</name>
  <idx>25</idx> 
  <comment><![CDATA[AC on]]></comment>
</var>

<var>
  <name>POWER_MODE</name>
  <idx>26</idx> 
  <comment><![CDATA[Power mode]]></comment>
</var>

<var>
  <name>VERBOSE_DEBUG</name>
  <idx>27</idx> 
  <comment><![CDATA[Verbose Debug mode]]></comment>
</var>

<var>
  <name>EXP64_MODE</name>
  <idx>28</idx> 
  <comment><![CDATA[if TRUE, working in exp 64 mode]]></comment>
</var>

<var>
  <name>EXP64_MODE_DELAY</name>
  <idx>29</idx> 
  <comment><![CDATA[delay for exp 64 mode acquiring...]]></comment>
</var>

<var>
  <name>PM_STOP_RUNMANAGER_TIMEOUT</name>
  <idx>30</idx> 
  <comment><![CDATA[the maximult time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager]]></comment>
</var>

<var>
  <name>PM_STOP_RUNMANAGER_TIMES_RETRY</name>
  <idx>31</idx> 
  <comment><![CDATA[The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle.]]></comment>
</var>

<var>
  <name>PM_N_ORBIT_CALIB</name>
  <idx>32</idx> 
  <comment><![CDATA[Number of orbits per calibration]]></comment>
</var>

<arr>
  <name>WS_1_SETTING</name>
  <n>5</n>
  <idx>3</idx>
  <comment><![CDATA[Define the Working Schedule #1 values in ms]]></comment>
</arr>

<var>
  <name>WS_TIME_ORBIT</name>
  <idx>33</idx> 
  <comment><![CDATA[The duration in millisencond of the full orbit in ms]]></comment>
</var>

<var>
  <name>WS_FAVOURITE_WS</name>
  <idx>34</idx> 
  <comment><![CDATA[The Favourite Pamela Working Schedule]]></comment>
</var>

<var>
  <name>MH_SINTOKTIMEOUT</name>
  <idx>35</idx> 
  <comment><![CDATA[Timeout for the event receive SINT_OK]]></comment>
</var>

<var>
  <name>RM_RUNTIMEOUT</name>
  <idx>40</idx> 
  <comment><![CDATA[The timeout for an event to come (software timeout)]]></comment>
</var>

<var>
  <name>RM_RUNHEADER_TIMEOUT</name>
  <idx>41</idx> 
  <comment><![CDATA[The timeout for writing a Run Header pkt]]></comment>
</var>

<var>
  <name>RM_RUNTRAILER_TIMEOUT</name>
  <idx>42</idx> 
  <comment><![CDATA[The timeout for writing a Run Trailer pkt]]></comment>
</var>

<var>
  <name>RM_STOP_FULL_ACQ_SECS</name>
  <idx>43</idx> 
  <comment><![CDATA[number of seconds after the starting of the first run after an ascending node must stop the full acquisition]]></comment>
</var>

<var>
  <name>RM_SUSPEND_IN_RUN_LOOP</name>
  <idx>44</idx> 
  <comment><![CDATA[Suspend time in the ACQ-Run Loop before get a new event]]></comment>
</var>

<var>
  <name>RM_ETO_COUNTER_IN_RUN_LOOP</name>
  <idx>45</idx> 
  <comment><![CDATA[Number or Acq attempts in the run loob in case of HW/SW event time out]]></comment>
</var>

<var>
  <name>RM_N_TRIES_PREPARE_PAGE</name>
  <idx>46</idx> 
  <comment><![CDATA[Number of attempts to try to exec the prepar page before exit from the run procedure with an error]]></comment>
</var>

<var>
  <name>RM_TRIES_PREPARE_PAGE_SLEEP</name>
  <idx>47</idx> 
  <comment><![CDATA[Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure]]></comment>
</var>

<var>
  <name>RM_WS3_TIMER_FIRE_AFTER</name>
  <idx>48</idx> 
  <comment><![CDATA[Time to wait for the WS3 timer to fire]]></comment>
</var>

<var>
  <name>RM_RATE_METER_S1_TRH</name>
  <idx>49</idx> 
  <comment><![CDATA[Rate meter s1 s1 register TRH]]></comment>
</var>

<var>
  <name>RM_TIME_MAX_RUN</name>
  <idx>50</idx> 
  <comment><![CDATA[Max duration for an ordinary Run in milliseconds]]></comment>
</var>

<var>
  <name>RM_TIME_SPECIAL_RUN</name>
  <idx>51</idx> 
  <comment><![CDATA[duration for the special run in milliseconds]]></comment>
</var>

<var>
  <name>RM_ACQCHECK_PERIOD</name>
  <idx>52</idx> 
  <comment><![CDATA[period of acquisition check in milliseconds]]></comment>
</var>

<var>
  <name>RM_FLUSH_TIMEOUT</name>
  <idx>53</idx> 
  <comment><![CDATA[timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT]]></comment>
</var>

<var>
  <name>RM_NO_FLUSH_PARAM_DUMP</name>
  <idx>54</idx> 
  <comment><![CDATA[Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never.]]></comment>
</var>

<var>
  <name>RM_DUMP_ALL_PARAMS</name>
  <idx>55</idx> 
  <comment><![CDATA[dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs]]></comment>
</var>

<var>
  <name>RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ</name>
  <idx>56</idx> 
  <comment><![CDATA[number of release busy inserted in the ACQ command queue in After_Calib mode]]></comment>
</var>

<arr>
  <name>PWR_IPM_CONF</name>
  <n>6</n>
  <idx>4</idx>
  <comment><![CDATA[IMP desired configuration for initial poweron 6 bitmask]]></comment>
</arr>

<var>
  <name>PWR_WAIT_BEFORE_SENDTC</name>
  <idx>57</idx> 
  <comment><![CDATA[time to wait before send 2 successive HL]]></comment>
</var>

<var>
  <name>PWR_TRB_READ_ATTEMPTS</name>
  <idx>58</idx> 
  <comment><![CDATA[number of attempts to sent a command to the TRB before a timeout]]></comment>
</var>

<var>
  <name>PWR_KHB_INITBOARD_TWICE_DELAY</name>
  <idx>59</idx> 
  <comment><![CDATA[milliseconds to wait between two KHB Init Board in PWR_DcdcON]]></comment>
</var>

<var>
  <name>PWR_IPM_WAIT_OK_N_ATTEMPT</name>
  <idx>60</idx> 
  <comment><![CDATA[attempts of ipm check ok at power on]]></comment>
</var>

<var>
  <name>PWR_IPM_WAIT_OK_DELAY_ATTEMPT</name>
  <idx>61</idx> 
  <comment><![CDATA[attempts of ipm check ok at power on]]></comment>
</var>

<var>
  <name>PWR_VOLTAGE_N_ATTEMPT</name>
  <idx>62</idx> 
  <comment><![CDATA[no of millisecond to wain in VOLTAGE IPM procedure]]></comment>
</var>

<var>
  <name>PWR_VOLTAGE_DELAY_ATTEMPT</name>
  <idx>63</idx> 
  <comment><![CDATA[no of millisecond to wain in VOLTAGE IPM procedure]]></comment>
</var>

<arr>
  <name>PWR_VOLTAGE_IPM_CONF</name>
  <n>6</n>
  <idx>5</idx>
  <comment><![CDATA[ADC desider configuration for inital poweron - OBSOLETE ]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_ON_MAX</name>
  <n>6</n>
  <idx>6</idx>
  <comment><![CDATA[ADC min voltage values if ON]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_ON_MIN</name>
  <n>6</n>
  <idx>7</idx>
  <comment><![CDATA[ADC min voltage values if ON]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_OFF_MAX</name>
  <n>6</n>
  <idx>8</idx>
  <comment><![CDATA[ADC min voltage values if OFF]]></comment>
</arr>

<arr>
  <name>PWR_VOLTAGE_IPM_RANGE_OFF_MIN</name>
  <n>6</n>
  <idx>9</idx>
  <comment><![CDATA[ADC min voltage values if OFF]]></comment>
</arr>

<var>
  <name>PWR_TRB1_SET</name>
  <idx>64</idx> 
  <comment><![CDATA[trb 1 setting]]></comment>
</var>

<var>
  <name>PWR_TRB2_SET</name>
  <idx>65</idx> 
  <comment><![CDATA[trb 2 setting]]></comment>
</var>

<var>
  <name>PWR_TRB_SET_DELAY</name>
  <idx>66</idx> 
  <comment><![CDATA[delay after trb set cmd]]></comment>
</var>

<var>
  <name>PWR_TRB_READ_DELAY</name>
  <idx>67</idx> 
  <comment><![CDATA[delay after trb read cmd]]></comment>
</var>

<tab>
  <name>PWR_IPM_ACTION</name>
  <rows>3</rows>
  <cols>64</cols>
  <idx>1</idx>
  <comment><![CDATA[Main Table for actions to be done in IPM Check procedure]]></comment>
</tab>

<var>
  <name>HB_N_ATTEMPT_WRITE2PIF</name>
  <idx>68</idx> 
  <comment><![CDATA[Number of attempt to write on PIF after return an error]]></comment>
</var>

<var>
  <name>HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF</name>
  <idx>69</idx> 
  <comment><![CDATA[Waint time after a failed attempt on PIF write]]></comment>
</var>

<var>
  <name>HB_WRITE2PIF_TIMEOUT</name>
  <idx>70</idx> 
  <comment><![CDATA[timeout time  time to wait a sketchboard free in Write2PIF]]></comment>
</var>

<var>
  <name>HB_ALMOST_FULL</name>
  <idx>71</idx> 
  <comment><![CDATA[says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage.]]></comment>
</var>

<arr>
  <name>TM_FILTER_OPERATION</name>
  <n>78</n>
  <idx>10</idx>
  <comment><![CDATA[low level telemetry filter operation: 0->nooperation 1->set value 2->ORed mask 3->ANDed mask]]></comment>
</arr>

<arr>
  <name>TM_FILTER_VALUE</name>
  <n>78</n>
  <idx>11</idx>
  <comment><![CDATA[low level telemetry filted values]]></comment>
</arr>

<var>
  <name>TM_VRL_SUSPEND_HCL</name>
  <idx>72</idx> 
  <comment><![CDATA[wait time between two HCL commands for the VRL]]></comment>
</var>

<var>
  <name>TM_VRL_SUSPEND_BEFORE_START</name>
  <idx>73</idx> 
  <comment><![CDATA[wait time before start VRL]]></comment>
</var>

<var>
  <name>DAQ_EVENT_RECEIVE_TIMEOUT</name>
  <idx>74</idx> 
  <comment><![CDATA[PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply]]></comment>
</var>

<var>
  <name>DAQ_WAITFREECMDIF_N</name>
  <idx>75</idx> 
  <comment><![CDATA[Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched]]></comment>
</var>

<var>
  <name>BUF_LEN_IDAQ_DSP_SET</name>
  <idx>76</idx> 
  <comment><![CDATA[IDAQ DSP SET]]></comment>
</var>

<arr>
  <name>BUF_IDAQ_DSP_SET</name>
  <n>2</n>
  <idx>12</idx>
  <comment><![CDATA[IDAQ DSP SET]]></comment>
</arr>

<var>
  <name>TRB_OK</name>
  <idx>77</idx> 
  <comment><![CDATA[Use ON_OFF tracker in ACQ]]></comment>
</var>

<var>
  <name>TRIGGER_MODE_A</name>
  <idx>78</idx> 
  <comment><![CDATA[Trigger type for acq mode A]]></comment>
</var>

<var>
  <name>TRIGGER_MODE_B</name>
  <idx>79</idx> 
  <comment><![CDATA[Trigger type for acq mode B]]></comment>
</var>

<var>
  <name>TRIGGER_BUSY_CONTROL</name>
  <idx>80</idx> 
  <comment><![CDATA[Select the check mask of the busy alaarm]]></comment>
</var>

<var>
  <name>TB_LINK</name>
  <idx>81</idx> 
  <comment><![CDATA[Trigger Board to use 1 or 2]]></comment>
</var>

<var>
  <name>BUF_LEN_TB_SET_ALARM_MASK</name>
  <idx>82</idx> 
  <comment><![CDATA[TRG queue]]></comment>
</var>

<arr>
  <name>BUF_TB_SET_ALARM_MASK</name>
  <n>2</n>
  <idx>13</idx>
  <comment><![CDATA[TRG queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TB_SET_PMT_MASK</name>
  <idx>83</idx> 
  <comment><![CDATA[TRG queue]]></comment>
</var>

<arr>
  <name>BUF_TB_SET_PMT_MASK</name>
  <n>3</n>
  <idx>14</idx>
  <comment><![CDATA[TRG queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TB_SET_S4_CAL_MASK</name>
  <idx>84</idx> 
  <comment><![CDATA[TRG queue]]></comment>
</var>

<arr>
  <name>BUF_TB_SET_S4_CAL_MASK</name>
  <n>2</n>
  <idx>15</idx>
  <comment><![CDATA[TRG queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT</name>
  <idx>85</idx> 
  <comment><![CDATA[ ]]></comment>
</var>

<arr>
  <name>BUF_TB_SET_BUSY_MASK_IDAQ_HOT</name>
  <n>5</n>
  <idx>16</idx>
  <comment><![CDATA[ ]]></comment>
</arr>

<var>
  <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD</name>
  <idx>86</idx> 
  <comment><![CDATA[ ]]></comment>
</var>

<arr>
  <name>BUF_TB_SET_BUSY_MASK_IDAQ_COLD</name>
  <n>5</n>
  <idx>17</idx>
  <comment><![CDATA[ ]]></comment>
</arr>

<var>
  <name>TRK_OK</name>
  <idx>87</idx> 
  <comment><![CDATA[Use ON_OFF tracker in ACQ]]></comment>
</var>

<tab>
  <name>TRK_DSP_OK</name>
  <rows>2</rows>
  <cols>6</cols>
  <idx>2</idx>
  <comment><![CDATA[Tracker dsp ON_OFF in ACQ]]></comment>
</tab>

<var>
  <name>TRK_CALIB_MODE</name>
  <idx>88</idx> 
  <comment><![CDATA[Tracker calibration mode]]></comment>
</var>

<var>
  <name>TRK_TIME_SHORT</name>
  <idx>89</idx> 
  <comment><![CDATA[Tracker wait loop for 128 loop]]></comment>
</var>

<var>
  <name>TRK_TIME_LONG</name>
  <idx>90</idx> 
  <comment><![CDATA[Tracker wait loop for 8 loop]]></comment>
</var>

<tab>
  <name>TRK_DSP_MASK</name>
  <rows>2</rows>
  <cols>6</cols>
  <idx>3</idx>
  <comment><![CDATA[Traker dsp mask]]></comment>
</tab>

<arr>
  <name>TRK_LOAD_PRG</name>
  <n>2</n>
  <idx>18</idx>
  <comment><![CDATA[The way the DSP program is loaded]]></comment>
</arr>

<var>
  <name>TRK_CALIB_INIT</name>
  <idx>91</idx> 
  <comment><![CDATA[modality of calibration]]></comment>
</var>

<var>
  <name>TRK_NLOOP</name>
  <idx>92</idx> 
  <comment><![CDATA[macro loop number]]></comment>
</var>

<var>
  <name>MMSU_DMA_DELAY</name>
  <idx>93</idx> 
  <comment><![CDATA[MMSU DELAY]]></comment>
</var>

<tab>
  <name>TRK_PED_MIN_0</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>4</idx>
  <comment><![CDATA[Tracker 0 ped min value]]></comment>
</tab>

<tab>
  <name>TRK_PED_MIN_1</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>5</idx>
  <comment><![CDATA[Tracker 1 ped min value]]></comment>
</tab>

<tab>
  <name>TRK_PED_MAX_0</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>6</idx>
  <comment><![CDATA[Tracker 0 ped max value]]></comment>
</tab>

<tab>
  <name>TRK_PED_MAX_1</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>7</idx>
  <comment><![CDATA[Tracker 1 ped max value]]></comment>
</tab>

<tab>
  <name>TRK_SIG_MIN_0</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>8</idx>
  <comment><![CDATA[Tracker 0 sig min value]]></comment>
</tab>

<tab>
  <name>TRK_SIG_MIN_1</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>9</idx>
  <comment><![CDATA[Tracker 1 sig min value]]></comment>
</tab>

<tab>
  <name>TRK_SIG_MAX_0</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>10</idx>
  <comment><![CDATA[Tracker 0 sig min value]]></comment>
</tab>

<tab>
  <name>TRK_SIG_MAX_1</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>11</idx>
  <comment><![CDATA[Tracker 1 sig min value]]></comment>
</tab>

<tab>
  <name>TRK_BAD_MAX_0</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>12</idx>
  <comment><![CDATA[Tracker 0 bad max value]]></comment>
</tab>

<tab>
  <name>TRK_BAD_MAX_1</name>
  <rows>3</rows>
  <cols>6</cols>
  <idx>13</idx>
  <comment><![CDATA[Tracker 1 bad max value]]></comment>
</tab>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_0</name>
  <idx>96</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 0]]></comment>
</var>

<arr>
  <name>BUF_TRK_TRAILER_PRG_0</name>
  <n>3</n>
  <idx>20</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 0]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_1</name>
  <idx>97</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 1]]></comment>
</var>

<arr>
  <name>BUF_TRK_TRAILER_PRG_1</name>
  <n>3</n>
  <idx>21</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 1]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_2</name>
  <idx>98</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 2]]></comment>
</var>

<arr>
  <name>BUF_TRK_TRAILER_PRG_2</name>
  <n>3</n>
  <idx>22</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 2]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_3</name>
  <idx>99</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 3]]></comment>
</var>

<arr>
  <name>BUF_TRK_TRAILER_PRG_3</name>
  <n>3</n>
  <idx>23</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 3]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_4</name>
  <idx>100</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 4]]></comment>
</var>

<arr>
  <name>BUF_TRK_TRAILER_PRG_4</name>
  <n>3</n>
  <idx>24</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 4]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_5</name>
  <idx>101</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 5]]></comment>
</var>

<arr>
  <name>BUF_TRK_TRAILER_PRG_5</name>
  <n>3</n>
  <idx>25</idx>
  <comment><![CDATA[TRK DSP Program Trailer for DSP 5]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_0</name>
  <idx>102</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_0</name>
  <n>8</n>
  <idx>26</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_1</name>
  <idx>103</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_1</name>
  <n>8</n>
  <idx>27</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_2</name>
  <idx>104</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_2</name>
  <n>8</n>
  <idx>28</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_3</name>
  <idx>105</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_3</name>
  <n>8</n>
  <idx>29</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_4</name>
  <idx>106</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_4</name>
  <n>8</n>
  <idx>30</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_5</name>
  <idx>107</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_1_5</name>
  <n>8</n>
  <idx>31</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_0</name>
  <idx>108</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_0</name>
  <n>8</n>
  <idx>32</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_1</name>
  <idx>109</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_1</name>
  <n>8</n>
  <idx>33</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_2</name>
  <idx>110</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_2</name>
  <n>8</n>
  <idx>34</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_3</name>
  <idx>111</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_3</name>
  <n>8</n>
  <idx>35</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_4</name>
  <idx>112</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_4</name>
  <n>8</n>
  <idx>36</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_5</name>
  <idx>113</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_NUMBER_DSP_2_5</name>
  <n>8</n>
  <idx>37</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_0</name>
  <idx>114</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_COMP_0</name>
  <n>8</n>
  <idx>38</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_0</name>
  <idx>115</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_0</name>
  <n>8</n>
  <idx>39</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_1</name>
  <idx>116</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_COMP_1</name>
  <n>8</n>
  <idx>40</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_1</name>
  <idx>117</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_1</name>
  <n>8</n>
  <idx>41</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_2</name>
  <idx>118</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_COMP_2</name>
  <n>8</n>
  <idx>42</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_2</name>
  <idx>119</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_2</name>
  <n>8</n>
  <idx>43</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_3</name>
  <idx>120</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_COMP_3</name>
  <n>8</n>
  <idx>44</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_3</name>
  <idx>121</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_3</name>
  <n>8</n>
  <idx>45</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_4</name>
  <idx>122</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_COMP_4</name>
  <n>8</n>
  <idx>46</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_4</name>
  <idx>123</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_4</name>
  <n>8</n>
  <idx>47</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_5</name>
  <idx>124</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_COMP_5</name>
  <n>8</n>
  <idx>48</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_5</name>
  <idx>125</idx> 
  <comment><![CDATA[TRK command queue]]></comment>
</var>

<arr>
  <name>BUF_TRK_OPMODE_SPEC_5</name>
  <n>8</n>
  <idx>49</idx>
  <comment><![CDATA[TRK command queue]]></comment>
</arr>

<var>
  <name>S4_OK</name>
  <idx>126</idx> 
  <comment><![CDATA[S4 enable/disable]]></comment>
</var>

<var>
  <name>S4_TRH</name>
  <idx>127</idx> 
  <comment><![CDATA[S4 command]]></comment>
</var>

<var>
  <name>S4_ATTEND</name>
  <idx>128</idx> 
  <comment><![CDATA[S4 force check]]></comment>
</var>

<var>
  <name>S4_WORKING</name>
  <idx>129</idx> 
  <comment><![CDATA[check if S4 is working or not]]></comment>
</var>

<arr>
  <name>TRK_SENSOR_MASK_Y</name>
  <n>6</n>
  <idx>50</idx>
  <comment><![CDATA[Mask of the power on/off of the sensor of the Y view.One for each plane ]]></comment>
</arr>

<arr>
  <name>TRK_SENSOR_TAB_Y_INDEX</name>
  <n>6</n>
  <idx>51</idx>
  <comment><![CDATA[Default raw value of the power on/off of the sensor of the Y view. Each value is in the range 0-7 (the raw index of TRK_SENSOR_TAB_Y)]]></comment>
</arr>

<arr>
  <name>TRK_SENSOR_TAB_X</name>
  <n>2</n>
  <idx>52</idx>
  <comment><![CDATA[Table of the power on/off of thesensor in the X view. One for each view]]></comment>
</arr>

<arr>
  <name>TRK_SENSOR_TAB_X_INDEX</name>
  <n>6</n>
  <idx>53</idx>
  <comment><![CDATA[Default raw value of the power on/off of thesensor in the X view. Each value is in the range 0-1 (the raw index of TRK_SENSOR_TAB_X). default all "0"]]></comment>
</arr>

<arr>
  <name>TRK_BIAS_TAB</name>
  <n>2</n>
  <idx>54</idx>
  <comment><![CDATA[Table of the power on/off of the bias]]></comment>
</arr>

<var>
  <name>TRK_BIAS_TAB_INDEX</name>
  <idx>130</idx> 
  <comment><![CDATA[the default value of the BIAS TAB value to use. can be 0 or 1]]></comment>
</var>

<var>
  <name>TRK_BIAS_MASK</name>
  <idx>131</idx> 
  <comment><![CDATA[Mask of the linear regulator of the bias. (18 bit) ]]></comment>
</var>

<arr>
  <name>TRK_LOAD_DSP_FROM</name>
  <n>24</n>
  <idx>55</idx>
  <comment><![CDATA[Load DSP From: TRK_LOCAL_FLASH(0),TRK_IDAQ_FLASH(1),TRK_PSCU_EPROM(2)
          index:
             0-5   Hot,X
             6-11  Hot,Y
             12-17 Cold,X
             18-23 Cold,Y
]]></comment>
</arr>

<var>
  <name>TRK_N_TR_FULL</name>
  <idx>132</idx> 
  <comment><![CDATA[number of events to be acquired in  FULL+COMPRESSION mode]]></comment>
</var>

<var>
  <name>TRK_N_TR_COMP</name>
  <idx>133</idx> 
  <comment><![CDATA[number of events to be acquired in COMPRESSION mode]]></comment>
</var>

<var>
  <name>TRK_MAX_COMPR_LENGTH</name>
  <idx>134</idx> 
  <comment><![CDATA[maximum number of word of an event in compression modo (for alarm generation)]]></comment>
</var>

<var>
  <name>TRK_MAX_COMPR_TIME</name>
  <idx>135</idx> 
  <comment><![CDATA[maximum time of an event analysis in compression mode (for alarm generation)]]></comment>
</var>

<var>
  <name>TRK_TIME_TR_CAL_SHORT</name>
  <idx>136</idx> 
  <comment><![CDATA[time between two triggers during the block of 128 events in calibration phase]]></comment>
</var>

<var>
  <name>TRK_TIME_TR_CAL_LONG</name>
  <idx>137</idx> 
  <comment><![CDATA[time between two block of 128 events in calibration phase]]></comment>
</var>

<var>
  <name>TRK_TIME_TR_CAL_READY</name>
  <idx>138</idx> 
  <comment><![CDATA[timing check of DSP ready register during calibration phase]]></comment>
</var>

<var>
  <name>TRK_MAX_TR_CAL_READY</name>
  <idx>139</idx> 
  <comment><![CDATA[maximum number of reading of the ready register during the calibration phase]]></comment>
</var>

<var>
  <name>TRK_N_TR_CAL_FULL</name>
  <idx>140</idx> 
  <comment><![CDATA[number of tracker calibration before a calibration with full acquisition]]></comment>
</var>

<var>
  <name>CAL_UPLOAD_CAL_FE_MASK</name>
  <idx>141</idx> 
  <comment><![CDATA[Defines the working read-out of calorimeter]]></comment>
</var>

<var>
  <name>CAL_UPLOAD_CAL_DSP_MASK</name>
  <idx>142</idx> 
  <comment><![CDATA[Defines the workings dsps of calorimeter]]></comment>
</var>

<arr>
  <name>CAL_STRIP_SKIP</name>
  <n>66</n>
  <idx>56</idx>
  <comment><![CDATA[Preamplifier vector]]></comment>
</arr>

<var>
  <name>CAL_VCAL</name>
  <idx>143</idx> 
  <comment><![CDATA[Variable modified by pulse calibration]]></comment>
</var>

<var>
  <name>CAL_CH</name>
  <idx>144</idx> 
  <comment><![CDATA[Variable modified by pulse calibration]]></comment>
</var>

<var>
  <name>CAL_TEMP</name>
  <idx>145</idx> 
  <comment><![CDATA[Maximum calorimeter temperature alarms]]></comment>
</var>

<arr>
  <name>CAL_COUNT</name>
  <n>4</n>
  <idx>57</idx>
  <comment><![CDATA[defines the calorimeter read out repetitions]]></comment>
</arr>

<var>
  <name>CAL_LOOP4</name>
  <idx>146</idx> 
  <comment><![CDATA[defines the calorimeter read out repetitions]]></comment>
</var>

<var>
  <name>CAL_OK</name>
  <idx>147</idx> 
  <comment><![CDATA[calo ON_OFF in ACQ]]></comment>
</var>

<var>
  <name>CAL_CHECK_FE</name>
  <idx>148</idx> 
  <comment><![CDATA[calo check FE]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I211</name>
  <idx>149</idx> 
  <comment><![CDATA[write fpga]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I211</name>
  <n>2</n>
  <idx>58</idx>
  <comment><![CDATA[write fpga]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I221</name>
  <idx>150</idx> 
  <comment><![CDATA[write fpga]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I221</name>
  <n>2</n>
  <idx>59</idx>
  <comment><![CDATA[write fpga]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I231</name>
  <idx>151</idx> 
  <comment><![CDATA[write fpga]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I231</name>
  <n>2</n>
  <idx>60</idx>
  <comment><![CDATA[write fpga]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_DSP_MEM_I43</name>
  <idx>154</idx> 
  <comment><![CDATA[dsp prog i43]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_DSP_MEM_I43</name>
  <n>11</n>
  <idx>63</idx>
  <comment><![CDATA[dsp prog i43]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_READ_DSP_MEM_C31</name>
  <idx>155</idx> 
  <comment><![CDATA[dsp prog c31]]></comment>
</var>

<arr>
  <name>BUF_CAL_READ_DSP_MEM_C31</name>
  <n>8</n>
  <idx>64</idx>
  <comment><![CDATA[dsp prog c31]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_READ_DSP_MEM_C32</name>
  <idx>156</idx> 
  <comment><![CDATA[dsp prog c32]]></comment>
</var>

<arr>
  <name>BUF_CAL_READ_DSP_MEM_C32</name>
  <n>8</n>
  <idx>65</idx>
  <comment><![CDATA[dsp prog c32]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_1</name>
  <idx>157</idx> 
  <comment><![CDATA[write fpga i241_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_1</name>
  <n>2</n>
  <idx>66</idx>
  <comment><![CDATA[write fpga i241_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_2</name>
  <idx>158</idx> 
  <comment><![CDATA[write fpga i241_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_2</name>
  <n>2</n>
  <idx>67</idx>
  <comment><![CDATA[write fpga i241_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_3</name>
  <idx>159</idx> 
  <comment><![CDATA[write fpga i241_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_3</name>
  <n>2</n>
  <idx>68</idx>
  <comment><![CDATA[write fpga i241_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_4</name>
  <idx>160</idx> 
  <comment><![CDATA[write fpga i241_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I241_4</name>
  <n>2</n>
  <idx>69</idx>
  <comment><![CDATA[write fpga i241_4]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_1</name>
  <idx>161</idx> 
  <comment><![CDATA[write fpga i251_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_1</name>
  <n>2</n>
  <idx>70</idx>
  <comment><![CDATA[write fpga i251_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_2</name>
  <idx>162</idx> 
  <comment><![CDATA[write fpga i251_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_2</name>
  <n>2</n>
  <idx>71</idx>
  <comment><![CDATA[write fpga i251_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_3</name>
  <idx>163</idx> 
  <comment><![CDATA[write fpga i251_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_3</name>
  <n>2</n>
  <idx>72</idx>
  <comment><![CDATA[write fpga i251_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_4</name>
  <idx>164</idx> 
  <comment><![CDATA[write fpga i251_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I251_4</name>
  <n>2</n>
  <idx>73</idx>
  <comment><![CDATA[write fpga i251_4]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_1</name>
  <idx>165</idx> 
  <comment><![CDATA[write fpga i261_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_1</name>
  <n>2</n>
  <idx>74</idx>
  <comment><![CDATA[write fpga i261_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_2</name>
  <idx>166</idx> 
  <comment><![CDATA[write fpga i261_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_2</name>
  <n>2</n>
  <idx>75</idx>
  <comment><![CDATA[write fpga i261_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_3</name>
  <idx>167</idx> 
  <comment><![CDATA[write fpga i261_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_3</name>
  <n>2</n>
  <idx>76</idx>
  <comment><![CDATA[write fpga i261_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_4</name>
  <idx>168</idx> 
  <comment><![CDATA[write fpga i261_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I261_4</name>
  <n>2</n>
  <idx>77</idx>
  <comment><![CDATA[write fpga i261_4]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_1</name>
  <idx>169</idx> 
  <comment><![CDATA[write fpga i260_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_1</name>
  <n>2</n>
  <idx>78</idx>
  <comment><![CDATA[write fpga i260_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_2</name>
  <idx>170</idx> 
  <comment><![CDATA[write fpga i260_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_2</name>
  <n>2</n>
  <idx>79</idx>
  <comment><![CDATA[write fpga i260_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_3</name>
  <idx>171</idx> 
  <comment><![CDATA[write fpga i260_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_3</name>
  <n>2</n>
  <idx>80</idx>
  <comment><![CDATA[write fpga i260_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_4</name>
  <idx>172</idx> 
  <comment><![CDATA[write fpga i260_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I260_4</name>
  <n>2</n>
  <idx>81</idx>
  <comment><![CDATA[write fpga i260_4]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_1</name>
  <idx>173</idx> 
  <comment><![CDATA[write fpga i311_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_1</name>
  <n>2</n>
  <idx>82</idx>
  <comment><![CDATA[write fpga i311_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_2</name>
  <idx>174</idx> 
  <comment><![CDATA[write fpga i311_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_2</name>
  <n>2</n>
  <idx>83</idx>
  <comment><![CDATA[write fpga i311_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_3</name>
  <idx>175</idx> 
  <comment><![CDATA[write fpga i311_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_3</name>
  <n>2</n>
  <idx>84</idx>
  <comment><![CDATA[write fpga i311_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_4</name>
  <idx>176</idx> 
  <comment><![CDATA[write fpga i311_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I311_4</name>
  <n>2</n>
  <idx>85</idx>
  <comment><![CDATA[write fpga i311_4]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_1</name>
  <idx>177</idx> 
  <comment><![CDATA[write fpga i310_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_1</name>
  <n>2</n>
  <idx>86</idx>
  <comment><![CDATA[write fpga i310_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_2</name>
  <idx>178</idx> 
  <comment><![CDATA[write fpga i310_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_2</name>
  <n>2</n>
  <idx>87</idx>
  <comment><![CDATA[write fpga i310_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_3</name>
  <idx>179</idx> 
  <comment><![CDATA[write fpga i310_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_3</name>
  <n>2</n>
  <idx>88</idx>
  <comment><![CDATA[write fpga i310_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_4</name>
  <idx>180</idx> 
  <comment><![CDATA[write fpga i310_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I310_4</name>
  <n>2</n>
  <idx>89</idx>
  <comment><![CDATA[write fpga i310_4]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I321</name>
  <idx>181</idx> 
  <comment><![CDATA[write fpga i321]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I321</name>
  <n>2</n>
  <idx>90</idx>
  <comment><![CDATA[write fpga i321]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_1</name>
  <idx>182</idx> 
  <comment><![CDATA[write fpga i331_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_1</name>
  <n>2</n>
  <idx>91</idx>
  <comment><![CDATA[write fpga i331_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_2</name>
  <idx>183</idx> 
  <comment><![CDATA[write fpga i331_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_2</name>
  <n>2</n>
  <idx>92</idx>
  <comment><![CDATA[write fpga i331_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_3</name>
  <idx>184</idx> 
  <comment><![CDATA[write fpga i331_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_3</name>
  <n>2</n>
  <idx>93</idx>
  <comment><![CDATA[write fpga i331_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_4</name>
  <idx>185</idx> 
  <comment><![CDATA[write fpga i331_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I331_4</name>
  <n>2</n>
  <idx>94</idx>
  <comment><![CDATA[write fpga i331_4]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_OFF</name>
  <idx>186</idx> 
  <comment><![CDATA[write fpga reg off]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_OFF</name>
  <n>2</n>
  <idx>95</idx>
  <comment><![CDATA[write fpga reg off]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_1</name>
  <idx>187</idx> 
  <comment><![CDATA[write fpga i341_1]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_1</name>
  <n>2</n>
  <idx>96</idx>
  <comment><![CDATA[write fpga i341_1]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_2</name>
  <idx>188</idx> 
  <comment><![CDATA[write fpga i341_2]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_2</name>
  <n>2</n>
  <idx>97</idx>
  <comment><![CDATA[write fpga i341_2]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_3</name>
  <idx>189</idx> 
  <comment><![CDATA[write fpga i341_3]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_3</name>
  <n>2</n>
  <idx>98</idx>
  <comment><![CDATA[write fpga i341_3]]></comment>
</arr>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_4</name>
  <idx>190</idx> 
  <comment><![CDATA[write fpga i341_4]]></comment>
</var>

<arr>
  <name>BUF_CAL_WRITE_FPGA_REG_I341_4</name>
  <n>2</n>
  <idx>99</idx>
  <comment><![CDATA[write fpga i341_4]]></comment>
</arr>

<var>
  <name>AC_1_OK</name>
  <idx>191</idx> 
  <comment><![CDATA[AC ON_OFF in ACQ]]></comment>
</var>

<var>
  <name>AC_2_OK</name>
  <idx>192</idx> 
  <comment><![CDATA[AC ON_OFF in ACQ]]></comment>
</var>

<var>
  <name>AC_1_CHECK</name>
  <idx>193</idx> 
  <comment><![CDATA[AC check]]></comment>
</var>

<var>
  <name>AC_2_CHECK</name>
  <idx>194</idx> 
  <comment><![CDATA[AC check]]></comment>
</var>

<var>
  <name>AC_LOOP</name>
  <idx>195</idx> 
  <comment><![CDATA[AC max loop]]></comment>
</var>

<var>
  <name>AC_LOOP2</name>
  <idx>196</idx> 
  <comment><![CDATA[AC max loop 2]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_1_SET_DAQ</name>
  <idx>197</idx> 
  <comment><![CDATA[SET DAQ command]]></comment>
</var>

<arr>
  <name>BUF_AC_1_SET_DAQ</name>
  <n>35</n>
  <idx>100</idx>
  <comment><![CDATA[SET DAQ command]]></comment>
</arr>

<var>
  <name>BUF_LEN_AC_2_SET_DAQ</name>
  <idx>198</idx> 
  <comment><![CDATA[SET DAQ command]]></comment>
</var>

<arr>
  <name>BUF_AC_2_SET_DAQ</name>
  <n>35</n>
  <idx>101</idx>
  <comment><![CDATA[SET DAQ command]]></comment>
</arr>

<var>
  <name>BUF_LEN_AC_2_WRITE_REG</name>
  <idx>202</idx> 
  <comment><![CDATA[]]></comment>
</var>

<arr>
  <name>BUF_AC_2_WRITE_REG</name>
  <n>15</n>
  <idx>105</idx>
  <comment><![CDATA[]]></comment>
</arr>

<var>
  <name>BUF_LEN_AC_1_WRITE_REG</name>
  <idx>203</idx> 
  <comment><![CDATA[]]></comment>
</var>

<arr>
  <name>BUF_AC_1_WRITE_REG</name>
  <n>15</n>
  <idx>106</idx>
  <comment><![CDATA[]]></comment>
</arr>

<var>
  <name>BUF_LEN_AC_READ_DSP_MEM</name>
  <idx>204</idx> 
  <comment><![CDATA[]]></comment>
</var>

<arr>
  <name>BUF_AC_READ_DSP_MEM</name>
  <n>3</n>
  <idx>107</idx>
  <comment><![CDATA[]]></comment>
</arr>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_1</name>
  <idx>205</idx> 
  <comment><![CDATA[TOF set THR front end 1]]></comment>
</var>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_1</name>
  <n>2</n>
  <idx>108</idx>
  <comment><![CDATA[TOF set THR front end 1]]></comment>
</arr>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_2</name>
  <idx>206</idx> 
  <comment><![CDATA[TOF set THR front end 2]]></comment>
</var>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_2</name>
  <n>2</n>
  <idx>109</idx>
  <comment><![CDATA[TOF set THR front end 2]]></comment>
</arr>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_3</name>
  <idx>207</idx> 
  <comment><![CDATA[TOF set THR front end 3]]></comment>
</var>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_3</name>
  <n>2</n>
  <idx>110</idx>
  <comment><![CDATA[TOF set THR front end 3]]></comment>
</arr>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_4</name>
  <idx>208</idx> 
  <comment><![CDATA[TOF set THR front end 4]]></comment>
</var>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_4</name>
  <n>2</n>
  <idx>111</idx>
  <comment><![CDATA[TOF set THR front end 4]]></comment>
</arr>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_5</name>
  <idx>209</idx> 
  <comment><![CDATA[TOF set THR front end 5]]></comment>
</var>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_5</name>
  <n>2</n>
  <idx>112</idx>
  <comment><![CDATA[TOF set THR front end 5]]></comment>
</arr>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_6</name>
  <idx>210</idx> 
  <comment><![CDATA[TOF set THR front end 5]]></comment>
</var>

<arr>
  <name>BUF_TOF_WRITE_PMT_THR_6</name>
  <n>2</n>
  <idx>113</idx>
  <comment><![CDATA[TOF set THR front end 5]]></comment>
</arr>

<var>
  <name>TOF_OK</name>
  <idx>211</idx> 
  <comment><![CDATA[TOF ON_OFF in ACQ]]></comment>
</var>

<arr>
  <name>TOF_PLAN</name>
  <n>6</n>
  <idx>114</idx>
  <comment><![CDATA[TOF Plans selectors]]></comment>
</arr>

<var>
  <name>TOF_ACTION</name>
  <idx>212</idx> 
  <comment><![CDATA[TOF alarm action code]]></comment>
</var>

<var>
  <name>ND_OK</name>
  <idx>213</idx> 
  <comment><![CDATA[ND ON_OFF in ACQ]]></comment>
</var>

<var>
  <name>ND_ATTEMPT</name>
  <idx>214</idx> 
  <comment><![CDATA[Force ND in ACQ, unless ND_OK is FALSE]]></comment>
</var>

<var>
  <name>ND_CMDS</name>
  <idx>215</idx> 
  <comment><![CDATA[Force ND in ACQ, unless ND_OK is FALSE]]></comment>
</var>

<var>
  <name>SM_WAIT_TRIG_EVENT</name>
  <idx>216</idx> 
  <comment><![CDATA[Time to wait between DAQ DMA programming and the CMD I/F DMA programming (as Laben suggested)]]></comment>
</var>

<arr>
  <name>PM_PERIODIC_DELAY</name>
  <n>4</n>
  <idx>115</idx>
  <comment><![CDATA[Define frequency in milliseconds for periodic actions: PM_ACQUISITION,PM_CYCLIC_ACQUISITION,PM_SAVE_TMTC_VALUES,PM_TSB_T_CHECK,PM_TSB_B_CHECK. see PM_INFN_COMMAND enum declarations,]]></comment>
</arr>

<var>
  <name>SCM_TM_DO_CHECK_VALUES_FREQ</name>
  <idx>217</idx> 
  <comment><![CDATA[Do a Check on TM values every XXX Number of cyc acq done]]></comment>
</var>

<var>
  <name>POWER_KHB</name>
  <idx>218</idx> 
  <comment><![CDATA[Select KHB board 0==>HOT else COLD]]></comment>
</var>

<var>
  <name>PSB_TRB_S9004_ALL_ON_DELAY</name>
  <idx>219</idx> 
  <comment><![CDATA[milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on)]]></comment>
</var>

<var>
  <name>PSB_TRB_BIAS_WAIT</name>
  <idx>220</idx> 
  <comment><![CDATA[wait between bias TRB switch on/off]]></comment>
</var>

<arr>
  <name>PSB_COMMANDS</name>
  <n>28</n>
  <idx>116</idx>
  <comment><![CDATA[Command for PSB]]></comment>
</arr>

<arr>
  <name>PSB_CALO_FE_ON</name>
  <n>4</n>
  <idx>117</idx>
  <comment><![CDATA[Command for PSB]]></comment>
</arr>

<arr>
  <name>PSB_CALO_FE_OFF</name>
  <n>4</n>
  <idx>118</idx>
  <comment><![CDATA[Command for PSB]]></comment>
</arr>

<arr>
  <name>PSB_CALO_FE</name>
  <n>4</n>
  <idx>119</idx>
  <comment><![CDATA[Command for PSB]]></comment>
</arr>

<var>
  <name>PSB_CALOFE_DELAY</name>
  <idx>221</idx> 
  <comment><![CDATA[Delay before power on CALO 5.7]]></comment>
</var>

<var>
  <name>HV_OK</name>
  <idx>222</idx> 
  <comment><![CDATA[call HV settings after TRB setting at start-up]]></comment>
</var>

<arr>
  <name>HVB_COMMANDS</name>
  <n>12</n>
  <idx>120</idx>
  <comment><![CDATA[Command for HVB]]></comment>
</arr>

<var>
  <name>TRB1_HOT</name>
  <idx>223</idx> 
  <comment><![CDATA[Command for TRB]]></comment>
</var>

<var>
  <name>TRB1_COLD</name>
  <idx>224</idx> 
  <comment><![CDATA[Command for TRB]]></comment>
</var>

<var>
  <name>TRB2_HOT</name>
  <idx>225</idx> 
  <comment><![CDATA[Command for TRB]]></comment>
</var>

<var>
  <name>TRB2_COLD</name>
  <idx>226</idx> 
  <comment><![CDATA[Command for TRB]]></comment>
</var>

<arr>
  <name>TSB_BOARD_OK</name>
  <n>2</n>
  <idx>121</idx>
  <comment><![CDATA[User TSB Board no 0/1 flags]]></comment>
</arr>

<var>
  <name>TSB_T_OK</name>
  <idx>227</idx> 
  <comment><![CDATA[Do TSB Temperature check]]></comment>
</var>

<var>
  <name>TSB_B_OK</name>
  <idx>228</idx> 
  <comment><![CDATA[Do B-field TSB check]]></comment>
</var>

<var>
  <name>ALLPAGEAVAIL_ATTEMPT</name>
  <idx>229</idx> 
  <comment><![CDATA[ATTEMP TO ALLPAGE AVAILABLE]]></comment>
</var>
