
<varxml>

<var>
  <name>LU_WRITE_ON_UART</name>
  <idx>0</idx> 
  <comment><![CDATA[enable[1]/disable[0] the UART writing /RO]]></comment>
</var>

<var>
  <name>VERBOSE_DEBUG</name>
  <idx>1</idx> 
  <comment><![CDATA[Verbose Debug mode]]></comment>
</var>

<var>
  <name>DOWNLOAD_HEADER</name>
  <idx>2</idx> 
  <comment><![CDATA[download counter, to be written in Download header info /RW-E2P]]></comment>
</var>

<var>
  <name>KHB_ALARM_REG_LOW_LEVEL_MASK</name>
  <idx>3</idx> 
  <comment><![CDATA[mask of KHB Alarm register to be low-level masked /RO]]></comment>
</var>

<var>
  <name>KHB_STATUS_REG_LOW_LEVEL_MASK</name>
  <idx>4</idx> 
  <comment><![CDATA[mask of KHB status register to be low-level masked /RO]]></comment>
</var>

<var>
  <name>PULSER_ACTION</name>
  <idx>5</idx> 
  <comment><![CDATA[pulser action at startup; [0=none,1=Reset,2:0.25Hz,3:100Hz] /RO]]></comment>
</var>

<var>
  <name>N_BOOT</name>
  <idx>6</idx> 
  <comment><![CDATA[Boot Counter /RW-E2P]]></comment>
</var>

<var>
  <name>THERMISTORS_CHECK</name>
  <idx>7</idx> 
  <comment><![CDATA[Check if thermistor are going to be checked /RO]]></comment>
</var>

<var>
  <name>THERM_MASK</name>
  <idx>8</idx> 
  <comment><![CDATA[Thermistors mask /RO]]></comment>
</var>

<var>
  <name>IPM_VOLTAGES_CHECK</name>
  <idx>9</idx> 
  <comment><![CDATA[Check if ipm are going to be checked /RO]]></comment>
</var>

<var>
  <name>KHB_IDAQ_CHECK</name>
  <idx>10</idx> 
  <comment><![CDATA[Check if khb&idaq are going to be checked /RO]]></comment>
</var>

<var>
  <name>NTRIG</name>
  <idx>11</idx> 
  <comment><![CDATA[Max Number of Lacks of Triggers /RO]]></comment>
</var>

<var>
  <name>TRIG</name>
  <idx>12</idx> 
  <comment><![CDATA[Counter of lacks of triggers /RW]]></comment>
</var>

<var>
  <name>CONF_SEL</name>
  <idx>13</idx> 
  <comment><![CDATA[active sensor selector /RW]]></comment>
</var>

<var>
  <name>CONFOK</name>
  <idx>14</idx> 
  <comment><![CDATA[whether to hange configuration from ground or onboard too: 0:dont increment CONF_SEL 1:increment CONF_SEL 2:do POWER_OFF_ON /RO]]></comment>
</var>

<var>
  <name>OFF</name>
  <idx>15</idx> 
  <comment><![CDATA[Counter of ON/OFF /RW]]></comment>
</var>

<var>
  <name>NOFF</name>
  <idx>16</idx> 
  <comment><![CDATA[Max Number of ON/OFF /RO]]></comment>
</var>

<var>
  <name>NRES</name>
  <idx>17</idx> 
  <comment><![CDATA[Max number of reset /RO]]></comment>
</var>

<var>
  <name>RES</name>
  <idx>18</idx> 
  <comment><![CDATA[Counter of reset /RW]]></comment>
</var>

<var>
  <name>WATCHDOG_RESET_DISABLE</name>
  <idx>19</idx> 
  <comment><![CDATA[disable watchdog reset: only for debugging!]]></comment>
</var>

<var>
  <name>NFAILED_POWER_ON</name>
  <idx>20</idx> 
  <comment><![CDATA[max number of failed power_on, before STOP&WAIT /RO]]></comment>
</var>

<var>
  <name>AUTO_RM_MODE</name>
  <idx>21</idx> 
  <comment><![CDATA[define the Automatic Mode for RM /RO]]></comment>
</var>

<var>
  <name>AUTO_SCM_MODE</name>
  <idx>22</idx> 
  <comment><![CDATA[define the Automatic Mode for scm /RO]]></comment>
</var>

<var>
  <name>MASK_ACQ_ALARM</name>
  <idx>23</idx> 
  <comment><![CDATA[Alarm mask /RO]]></comment>
</var>

<var>
  <name>GOM_DURING_ALARM</name>
  <idx>24</idx> 
  <comment><![CDATA[General operation mode during alarm revelation /RW]]></comment>
</var>

<var>
  <name>PM_FORCE_RUNNING_TIMEOUT</name>
  <idx>25</idx> 
  <comment><![CDATA[waiting for start select mode before force go to running]]></comment>
</var>

<var>
  <name>PAMELA_ON</name>
  <idx>26</idx> 
  <comment><![CDATA[Pamela status [0=OFF-1:OFF] /RW]]></comment>
</var>

<var>
  <name>N_CALIB</name>
  <idx>27</idx> 
  <comment><![CDATA[Counter of calibratrion since start up /RW]]></comment>
</var>

<var>
  <name>AC_1_ON</name>
  <idx>28</idx> 
  <comment><![CDATA[AC 1 on from initialization /RW]]></comment>
</var>

<var>
  <name>AC_2_ON</name>
  <idx>29</idx> 
  <comment><![CDATA[AC 2 on from initialization /RW]]></comment>
</var>

<var>
  <name>POWER_MODE</name>
  <idx>30</idx> 
  <comment><![CDATA[Power mode of PAMELA /RW]]></comment>
</var>

<var>
  <name>TRIG_II</name>
  <idx>31</idx> 
  <comment><![CDATA[TRIGGER II level mode on/off /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRIG_II_INIT</name>
  <idx>32</idx> 
  <comment><![CDATA[TRIG_II init command queue]]></comment>
</var>

<var>
  <name>BUF_LEN_TRIG_II_ACQ</name>
  <idx>33</idx> 
  <comment><![CDATA[TRIG_II acq command queue]]></comment>
</var>

<var>
  <name>EXP64_MODE</name>
  <idx>34</idx> 
  <comment><![CDATA[if TRUE, working in exp 64 mode /RO]]></comment>
</var>

<var>
  <name>EXP64_MODE_DELAY</name>
  <idx>35</idx> 
  <comment><![CDATA[delay for exp 64 mode acquiring /RO]]></comment>
</var>

<var>
  <name>MH_END_OF_DOWNLOAD_TIMEOUT</name>
  <idx>36</idx> 
  <comment><![CDATA[time out of the end of download /RO]]></comment>
</var>

<var>
  <name>PM_STOP_RUNMANAGER_TIMEOUT</name>
  <idx>37</idx> 
  <comment><![CDATA[the maximu time to wait for the pam manager the notification of SINT_OK from the run manager, when a SINT is sent. This avoids the pam manager waits forever when it wants to stop the run manager /RO]]></comment>
</var>

<var>
  <name>PM_STOP_RUNMANAGER_TIMES_RETRY</name>
  <idx>38</idx> 
  <comment><![CDATA[The Number of times the PamManager tries to repeat the stop request to the RunManager, before exit of the cycle. /RO]]></comment>
</var>

<var>
  <name>PM_N_ORBIT_CALIB</name>
  <idx>39</idx> 
  <comment><![CDATA[Number of orbits per calibration /RO]]></comment>
</var>

<var>
  <name>WS_TIME_ORBIT</name>
  <idx>40</idx> 
  <comment><![CDATA[The duration in millisencond of the full orbit in ms /RO]]></comment>
</var>

<var>
  <name>WS_FAVOURITE_WS</name>
  <idx>41</idx> 
  <comment><![CDATA[The Favourite Pamela Working Schedule /RO]]></comment>
</var>

<var>
  <name>RM_N_TRIES_PREPARE_PAGE</name>
  <idx>42</idx> 
  <comment><![CDATA[Number of attempts to try to exec the prepar page before exit from the run procedure with an error /RO]]></comment>
</var>

<var>
  <name>RM_TRIES_PREPARE_PAGE_SLEEP</name>
  <idx>43</idx> 
  <comment><![CDATA[Number of ticks to suspend the RM task if the PIF is full before another attempt to execute the PreparePage procedure /RO]]></comment>
</var>

<var>
  <name>RM_WS3_TIMER_FIRE_AFTER</name>
  <idx>44</idx> 
  <comment><![CDATA[Time to wait for the WS3 timer to fire /RO]]></comment>
</var>

<var>
  <name>RM_TIME_MAX_RUN</name>
  <idx>45</idx> 
  <comment><![CDATA[Max duration for an ordinary Run in milliseconds /RO]]></comment>
</var>

<var>
  <name>RM_TIME_SPECIAL_RUN</name>
  <idx>46</idx> 
  <comment><![CDATA[duration for the special run in milliseconds /RO]]></comment>
</var>

<var>
  <name>RM_ACQCHECK_PERIOD</name>
  <idx>47</idx> 
  <comment><![CDATA[period of acquisition check in milliseconds /RO]]></comment>
</var>

<var>
  <name>RM_FLUSH_TIMEOUT</name>
  <idx>48</idx> 
  <comment><![CDATA[timeout for the flush operation check after a certain inactivity of the rum nanager. if zero means RTEMS_NO_TIMEOUT /RO]]></comment>
</var>

<var>
  <name>RM_NO_FLUSH_PARAM_DUMP</name>
  <idx>49</idx> 
  <comment><![CDATA[Number of automatic flusches after wich also VAR/ARR/TAB dump is done. If zero means never. /RO]]></comment>
</var>

<var>
  <name>RM_DUMP_ALL_PARAMS</name>
  <idx>50</idx> 
  <comment><![CDATA[dump also parameters tagget as not storend in MM stored. BITMASK : bit 0 -> store variables , bit 1 -> store arrays , bit 3 -> store tabs /RO]]></comment>
</var>

<var>
  <name>RM_NO_DUMMY_CMD_BEFORE_SPECIAL_TRK_ACQ</name>
  <idx>51</idx> 
  <comment><![CDATA[number of release busy inserted in the ACQ command queue in After_Calib mode /RO]]></comment>
</var>

<var>
  <name>PWR_WAIT_BEFORE_SENDTC</name>
  <idx>52</idx> 
  <comment><![CDATA[time to wait before send 2 successive HL /RO]]></comment>
</var>

<var>
  <name>PWR_CMD2PSB_DELAY</name>
  <idx>53</idx> 
  <comment><![CDATA[time to wait before every CMD2PSB]]></comment>
</var>

<var>
  <name>PWR_TRB_READ_ATTEMPTS</name>
  <idx>54</idx> 
  <comment><![CDATA[number of attempts to sent a command to the TRB before a timeout /RO]]></comment>
</var>

<var>
  <name>PWR_KHB_INITBOARD_TWICE_DELAY</name>
  <idx>55</idx> 
  <comment><![CDATA[milliseconds to wait between two KHB Init Board in PWR_DcdcON /RO]]></comment>
</var>

<var>
  <name>PWR_IPM_WAIT_OK_N_ATTEMPT</name>
  <idx>56</idx> 
  <comment><![CDATA[attempts of ipm check ok at power on /RO]]></comment>
</var>

<var>
  <name>PWR_IPM_WAIT_OK_DELAY_ATTEMPT</name>
  <idx>57</idx> 
  <comment><![CDATA[attempts of ipm check ok at power on /RO]]></comment>
</var>

<var>
  <name>PWR_VOLTAGE_N_ATTEMPT</name>
  <idx>58</idx> 
  <comment><![CDATA[no of millisecond to wait in VOLTAGE IPM procedure /RO]]></comment>
</var>

<var>
  <name>PWR_VOLTAGE_DELAY_ATTEMPT</name>
  <idx>59</idx> 
  <comment><![CDATA[no of millisecond to wain in VOLTAGE IPM procedure /RO]]></comment>
</var>

<var>
  <name>PWR_TRB1_SET</name>
  <idx>60</idx> 
  <comment><![CDATA[trb 1 setting /RO]]></comment>
</var>

<var>
  <name>PWR_TRB2_SET</name>
  <idx>61</idx> 
  <comment><![CDATA[trb 2 setting /RO]]></comment>
</var>

<var>
  <name>PWR_TRB_SET_DELAY</name>
  <idx>62</idx> 
  <comment><![CDATA[delay after trb set cmd /RO]]></comment>
</var>

<var>
  <name>PWR_TRB_READ_DELAY</name>
  <idx>63</idx> 
  <comment><![CDATA[delay after trb read cmd /RO]]></comment>
</var>

<var>
  <name>HB_N_ATTEMPT_WRITE2PIF</name>
  <idx>64</idx> 
  <comment><![CDATA[Number of attempt to write on PIF after return an error /RO]]></comment>
</var>

<var>
  <name>HB_WAIT_ON_FAILED_ATTEMPT_WRITE2PIF</name>
  <idx>65</idx> 
  <comment><![CDATA[Waint time after a failed attempt on PIF write /RO]]></comment>
</var>

<var>
  <name>HB_WRITE2PIF_TIMEOUT</name>
  <idx>66</idx> 
  <comment><![CDATA[timeout time  time to wait a sketchboard free in Write2PIF /RO]]></comment>
</var>

<var>
  <name>HB_ALMOST_FULL</name>
  <idx>67</idx> 
  <comment><![CDATA[says when a specific internal buffer is condierered almost full and a FLUSH_HB request can be done. Unit is a percentage. /RM]]></comment>
</var>

<var>
  <name>TM_VRL_SUSPEND_HCL</name>
  <idx>68</idx> 
  <comment><![CDATA[wait time between two HCL commands for the VRL /RO]]></comment>
</var>

<var>
  <name>TM_VRL_SUSPEND_BEFORE_START</name>
  <idx>69</idx> 
  <comment><![CDATA[wait time before start VRL /RO]]></comment>
</var>

<var>
  <name>DAQ_EVENT_RECEIVE_TIMEOUT</name>
  <idx>70</idx> 
  <comment><![CDATA[PIF Timeout of DAQ_SendCmd2PIFWaitDAQReply /RO]]></comment>
</var>

<var>
  <name>DAQ_WAITFREECMDIF_N</name>
  <idx>71</idx> 
  <comment><![CDATA[Number of times the polling on SD_piGetCMDCounterLeft must be done before timeout when waiting the che CMDIF to be finisched /RO]]></comment>
</var>

<var>
  <name>TRB_OK</name>
  <idx>72</idx> 
  <comment><![CDATA[Use ON_OFF tracker in ACQ /RO]]></comment>
</var>

<var>
  <name>TRIGGER_MODE_A</name>
  <idx>73</idx> 
  <comment><![CDATA[Trigger type for acq mode A /RO]]></comment>
</var>

<var>
  <name>TRIGGER_MODE_B</name>
  <idx>74</idx> 
  <comment><![CDATA[Trigger type for acq mode B /RO]]></comment>
</var>

<var>
  <name>TRIGGER_BUSY_CONTROL</name>
  <idx>75</idx> 
  <comment><![CDATA[Select the check mask of the busy alaarm /RO]]></comment>
</var>

<var>
  <name>TB_LINK</name>
  <idx>76</idx> 
  <comment><![CDATA[Trigger Board to use 1 or 2 /RO]]></comment>
</var>

<var>
  <name>TB_LINK_CUSTOM</name>
  <idx>77</idx> 
  <comment><![CDATA[Trigger Board CUSTOMto use 1 or 2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TB_SET_ALARM_MASK</name>
  <idx>78</idx> 
  <comment><![CDATA[TRG queue]]></comment>
</var>

<var>
  <name>BUF_LEN_TB_SET_PMT_MASK</name>
  <idx>79</idx> 
  <comment><![CDATA[TRG queue]]></comment>
</var>

<var>
  <name>BUF_LEN_TB_SET_S4_CAL_MASK</name>
  <idx>80</idx> 
  <comment><![CDATA[TRG queue]]></comment>
</var>

<var>
  <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_HOT</name>
  <idx>81</idx> 
  <comment><![CDATA[ ]]></comment>
</var>

<var>
  <name>BUF_LEN_TB_SET_BUSY_MASK_IDAQ_COLD</name>
  <idx>82</idx> 
  <comment><![CDATA[ ]]></comment>
</var>

<var>
  <name>TRK_OK</name>
  <idx>83</idx> 
  <comment><![CDATA[Use ON_OFF tracker in ACQ /RO]]></comment>
</var>

<var>
  <name>TRK_CALIB_MODE</name>
  <idx>84</idx> 
  <comment><![CDATA[Tracker calibration mode /RO]]></comment>
</var>

<var>
  <name>TRK_TIME_SHORT</name>
  <idx>85</idx> 
  <comment><![CDATA[Tracker wait loop for 128 loop /RO]]></comment>
</var>

<var>
  <name>TRK_TIME_LONG</name>
  <idx>86</idx> 
  <comment><![CDATA[Tracker wait loop for 8 loop /RO]]></comment>
</var>

<var>
  <name>TRK_CALIB_INIT</name>
  <idx>87</idx> 
  <comment><![CDATA[modality of calibration /RO]]></comment>
</var>

<var>
  <name>TRK_NLOOP</name>
  <idx>88</idx> 
  <comment><![CDATA[macro loop number /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_PROGRAM</name>
  <idx>89</idx> 
  <comment><![CDATA[TRK DSP Program /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_0</name>
  <idx>90</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 0 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_1</name>
  <idx>91</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_2</name>
  <idx>92</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_3</name>
  <idx>93</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_4</name>
  <idx>94</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_TRAILER_PRG_5</name>
  <idx>95</idx> 
  <comment><![CDATA[TRK DSP Program Trailer for DSP 5 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_0</name>
  <idx>96</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_1</name>
  <idx>97</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_2</name>
  <idx>98</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_3</name>
  <idx>99</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_4</name>
  <idx>100</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_1_5</name>
  <idx>101</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_0</name>
  <idx>102</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_1</name>
  <idx>103</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_2</name>
  <idx>104</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_3</name>
  <idx>105</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_4</name>
  <idx>106</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_NUMBER_DSP_2_5</name>
  <idx>107</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_0</name>
  <idx>108</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_0</name>
  <idx>109</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_1</name>
  <idx>110</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_1</name>
  <idx>111</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_2</name>
  <idx>112</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_2</name>
  <idx>113</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_3</name>
  <idx>114</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_3</name>
  <idx>115</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_4</name>
  <idx>116</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_4</name>
  <idx>117</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_COMP_5</name>
  <idx>118</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TRK_OPMODE_SPEC_5</name>
  <idx>119</idx> 
  <comment><![CDATA[TRK command queue /RO]]></comment>
</var>

<var>
  <name>S4_OK</name>
  <idx>120</idx> 
  <comment><![CDATA[S4 enable/disable /RO]]></comment>
</var>

<var>
  <name>S4_TRH</name>
  <idx>121</idx> 
  <comment><![CDATA[S4 command /RO]]></comment>
</var>

<var>
  <name>S4_ATTEMPT</name>
  <idx>122</idx> 
  <comment><![CDATA[S4 force check /RO]]></comment>
</var>

<var>
  <name>S4_WORKING</name>
  <idx>123</idx> 
  <comment><![CDATA[check if S4 is working or not /RO]]></comment>
</var>

<var>
  <name>CAL_UPLOAD_CAL_FE_MASK</name>
  <idx>124</idx> 
  <comment><![CDATA[Defines the working read-out of calorimeter /RO]]></comment>
</var>

<var>
  <name>CAL_UPLOAD_CAL_DSP_MASK</name>
  <idx>125</idx> 
  <comment><![CDATA[Defines the workings dsps of calorimeter /RO]]></comment>
</var>

<var>
  <name>CAL_VCAL</name>
  <idx>126</idx> 
  <comment><![CDATA[Variable modified by pulse calibration /RW]]></comment>
</var>

<var>
  <name>CAL_CH</name>
  <idx>127</idx> 
  <comment><![CDATA[Variable modified by pulse calibration /RW]]></comment>
</var>

<var>
  <name>CAL_TEMP</name>
  <idx>128</idx> 
  <comment><![CDATA[Maximum calorimeter temperature alarms /RO]]></comment>
</var>

<var>
  <name>CAL_OK</name>
  <idx>129</idx> 
  <comment><![CDATA[calo ON_OFF in ACQ /RW]]></comment>
</var>

<var>
  <name>CAL_CHECK_FE</name>
  <idx>130</idx> 
  <comment><![CDATA[calo check FE /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I211</name>
  <idx>131</idx> 
  <comment><![CDATA[write fpga /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I221</name>
  <idx>132</idx> 
  <comment><![CDATA[write fpga /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I231</name>
  <idx>133</idx> 
  <comment><![CDATA[write fpga /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_DSP_MEM_I41</name>
  <idx>134</idx> 
  <comment><![CDATA[dsp prog i41 /R0]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_DSP_MEM_I42</name>
  <idx>135</idx> 
  <comment><![CDATA[dsp prog i42 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_DSP_MEM_I43</name>
  <idx>136</idx> 
  <comment><![CDATA[dsp prog i43 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_READ_DSP_MEM_C31</name>
  <idx>137</idx> 
  <comment><![CDATA[dsp prog c31 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_READ_DSP_MEM_C32</name>
  <idx>138</idx> 
  <comment><![CDATA[dsp prog c32 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_1</name>
  <idx>139</idx> 
  <comment><![CDATA[write fpga i241_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_2</name>
  <idx>140</idx> 
  <comment><![CDATA[write fpga i241_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_3</name>
  <idx>141</idx> 
  <comment><![CDATA[write fpga i241_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I241_4</name>
  <idx>142</idx> 
  <comment><![CDATA[write fpga i241_4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_1</name>
  <idx>143</idx> 
  <comment><![CDATA[write fpga i251_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_2</name>
  <idx>144</idx> 
  <comment><![CDATA[write fpga i251_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_3</name>
  <idx>145</idx> 
  <comment><![CDATA[write fpga i251_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I251_4</name>
  <idx>146</idx> 
  <comment><![CDATA[write fpga i251_4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_1</name>
  <idx>147</idx> 
  <comment><![CDATA[write fpga i261_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_2</name>
  <idx>148</idx> 
  <comment><![CDATA[write fpga i261_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_3</name>
  <idx>149</idx> 
  <comment><![CDATA[write fpga i261_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I261_4</name>
  <idx>150</idx> 
  <comment><![CDATA[write fpga i261_4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_1</name>
  <idx>151</idx> 
  <comment><![CDATA[write fpga i260_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_2</name>
  <idx>152</idx> 
  <comment><![CDATA[write fpga i260_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_3</name>
  <idx>153</idx> 
  <comment><![CDATA[write fpga i260_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I260_4</name>
  <idx>154</idx> 
  <comment><![CDATA[write fpga i260_4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_1</name>
  <idx>155</idx> 
  <comment><![CDATA[write fpga i311_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_2</name>
  <idx>156</idx> 
  <comment><![CDATA[write fpga i311_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_3</name>
  <idx>157</idx> 
  <comment><![CDATA[write fpga i311_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I311_4</name>
  <idx>158</idx> 
  <comment><![CDATA[write fpga i311_4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_1</name>
  <idx>159</idx> 
  <comment><![CDATA[write fpga i310_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_2</name>
  <idx>160</idx> 
  <comment><![CDATA[write fpga i310_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_3</name>
  <idx>161</idx> 
  <comment><![CDATA[write fpga i310_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I310_4</name>
  <idx>162</idx> 
  <comment><![CDATA[write fpga i310_4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I321</name>
  <idx>163</idx> 
  <comment><![CDATA[write fpga i321 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_1</name>
  <idx>164</idx> 
  <comment><![CDATA[write fpga i331_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_2</name>
  <idx>165</idx> 
  <comment><![CDATA[write fpga i331_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_3</name>
  <idx>166</idx> 
  <comment><![CDATA[write fpga i331_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I331_4</name>
  <idx>167</idx> 
  <comment><![CDATA[write fpga i331_4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_OFF</name>
  <idx>168</idx> 
  <comment><![CDATA[write fpga reg off /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_1</name>
  <idx>169</idx> 
  <comment><![CDATA[write fpga i341_1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_2</name>
  <idx>170</idx> 
  <comment><![CDATA[write fpga i341_2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_3</name>
  <idx>171</idx> 
  <comment><![CDATA[write fpga i341_3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_CAL_WRITE_FPGA_REG_I341_4</name>
  <idx>172</idx> 
  <comment><![CDATA[write fpga i341_4 /RO]]></comment>
</var>

<var>
  <name>AC_1_OK</name>
  <idx>173</idx> 
  <comment><![CDATA[AC ON_OFF in ACQ /RW]]></comment>
</var>

<var>
  <name>AC_2_OK</name>
  <idx>174</idx> 
  <comment><![CDATA[AC ON_OFF in ACQ /RW]]></comment>
</var>

<var>
  <name>AC_1_CHECK</name>
  <idx>175</idx> 
  <comment><![CDATA[AC check /RO]]></comment>
</var>

<var>
  <name>AC_2_CHECK</name>
  <idx>176</idx> 
  <comment><![CDATA[AC check /RO]]></comment>
</var>

<var>
  <name>AC_LOOP</name>
  <idx>177</idx> 
  <comment><![CDATA[AC max loop /RO]]></comment>
</var>

<var>
  <name>AC_LOOP2</name>
  <idx>178</idx> 
  <comment><![CDATA[AC max loop 2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_1_SET_DAQ</name>
  <idx>179</idx> 
  <comment><![CDATA[SET DAQ command /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_2_SET_DAQ</name>
  <idx>180</idx> 
  <comment><![CDATA[SET DAQ command /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_SEND_DSP_PROG1</name>
  <idx>181</idx> 
  <comment><![CDATA[DSP Program 1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_1_SEND_DSP_PROG2</name>
  <idx>182</idx> 
  <comment><![CDATA[ /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_2_SEND_DSP_PROG2</name>
  <idx>183</idx> 
  <comment><![CDATA[ /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_2_WRITE_REG</name>
  <idx>184</idx> 
  <comment><![CDATA[/RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_1_WRITE_REG</name>
  <idx>185</idx> 
  <comment><![CDATA[/RO]]></comment>
</var>

<var>
  <name>BUF_LEN_AC_READ_DSP_MEM</name>
  <idx>186</idx> 
  <comment><![CDATA[ /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_1</name>
  <idx>187</idx> 
  <comment><![CDATA[TOF set THR front end 1 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_2</name>
  <idx>188</idx> 
  <comment><![CDATA[TOF set THR front end 2 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_3</name>
  <idx>189</idx> 
  <comment><![CDATA[TOF set THR front end 3 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_4</name>
  <idx>190</idx> 
  <comment><![CDATA[TOF set THR front end 4 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_5</name>
  <idx>191</idx> 
  <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
</var>

<var>
  <name>BUF_LEN_TOF_WRITE_PMT_THR_6</name>
  <idx>192</idx> 
  <comment><![CDATA[TOF set THR front end 5 /RO]]></comment>
</var>

<var>
  <name>TOF_OK</name>
  <idx>193</idx> 
  <comment><![CDATA[TOF ON_OFF in ACQ /RW]]></comment>
</var>

<var>
  <name>ND_OK</name>
  <idx>194</idx> 
  <comment><![CDATA[ND ON_OFF in ACQ /RW]]></comment>
</var>

<var>
  <name>ND_ATTEMPT</name>
  <idx>195</idx> 
  <comment><![CDATA[Force ND in ACQ (1), unless ND_OK is FALSE /RO]]></comment>
</var>

<var>
  <name>ND_CMDS</name>
  <idx>196</idx> 
  <comment><![CDATA[Force ND in ACQ, unless ND_OK is FALSE /RO]]></comment>
</var>

<var>
  <name>SCM_TM_DO_CHECK_VALUES_FREQ</name>
  <idx>197</idx> 
  <comment><![CDATA[Do a Check on TM values every XXX Number of cyc acq done /RO]]></comment>
</var>

<var>
  <name>POWER_KHB</name>
  <idx>198</idx> 
  <comment><![CDATA[Select KHB board 0==>HOT else COLD]]></comment>
</var>

<var>
  <name>PSB_TRB_S9004_ALL_ON_DELAY</name>
  <idx>199</idx> 
  <comment><![CDATA[milliseconds to wait after PSB_TRB_S9004_ALL_ON (board need to be switched on) /RO]]></comment>
</var>

<var>
  <name>PSB_TRB_BIAS_WAIT</name>
  <idx>200</idx> 
  <comment><![CDATA[wait between bias TRB switch on/off /RO]]></comment>
</var>

<var>
  <name>PSB_CALOFE_DELAY</name>
  <idx>201</idx> 
  <comment><![CDATA[Delay before power on CALO 5.7 /RO]]></comment>
</var>

<var>
  <name>HV_OK</name>
  <idx>202</idx> 
  <comment><![CDATA[call HV settings after TRB setting at start-up /RO]]></comment>
</var>

<var>
  <name>TSB_T_OK</name>
  <idx>203</idx> 
  <comment><![CDATA[Do TSB Temperature check /RO]]></comment>
</var>

<var>
  <name>TSB_B_OK</name>
  <idx>204</idx> 
  <comment><![CDATA[Do B-field TSB check /RO]]></comment>
</var>

<var>
  <name>ALLPAGEAVAIL_ATTEMPT</name>
  <idx>205</idx> 
  <comment><![CDATA[ATTEMP TO ALLPAGE AVAILABLE]]></comment>
</var>

</varxml>
