116 |
do iv=1,nviews |
do iv=1,nviews |
117 |
ima=0 |
ima=0 |
118 |
do ik=1,nva1_view |
do ik=1,nva1_view |
119 |
cn(iv,ik) = 0 |
cn(iv,ik) = 0 |
120 |
cnrms(iv,ik) = 0 |
cnrms(iv,ik) = 0 |
121 |
cnn(iv,ik) = -1 |
cnn(iv,ik) = -1 |
122 |
iflag=0 |
iflag = 0 |
123 |
mask_vk_ev(iv,ik)=1 |
mask_vk_ev(iv,ik) = 1 |
124 |
call stripmask(iv,ik) !compute mask(i,j,k), combining VA1-masks |
call stripmask(iv,ik) !compute mask(i,j,k), combining VA1-masks |
125 |
c NBNBNBNBNB mask per la striscia 1 !!!!!!!! |
* -------------------------------------- |
126 |
if(mask(iv,ik,1).eq.1)call cncomp(iv,ik,iflag) |
* if chip is not masked ---> evaluate CN |
127 |
if(iflag.ne.0)then |
* -------------------------------------- |
128 |
ima=ima+1 |
if( mask(iv,ik,1).eq.1 ) then !!!NBNB mask per la striscia 1 !!!!!!!! |
129 |
mask_vk_ev(iv,ik)=0 |
call cncomp(iv,ik,iflag) |
130 |
ierror = 220 |
if(iflag.ne.0)then |
131 |
|
ima=ima+1 |
132 |
|
mask_vk_ev(iv,ik)=0 |
133 |
|
ierror = 220 |
134 |
|
endif |
135 |
|
call stripmask(iv,ik) !compute mask(i,j,k), combining VA1-masks |
136 |
endif |
endif |
|
call stripmask(iv,ik) !compute mask(i,j,k), combining VA1-masks |
|
|
|
|
137 |
enddo |
enddo |
138 |
100 format(' * WARNING * Event ',i7,' view',i3,': VK MASK ',24i1) |
100 format(' * WARNING * Event ',i7,' view',i3,': VK MASK ',24i1) |
139 |
if(ima.ne.0.and.debug)write(*,100)eventn(1),iv |
if(ima.ne.0.and.debug)write(*,100)eventn(1),iv |
140 |
$ ,(mask_vk_ev(iv,ik),ik=1,nva1_view) |
$ ,(mask_vk_ev(iv,ik),ik=1,nva1_view) |
141 |
|
c if(ima.ne.0)write(*,100)eventn(1),iv |
142 |
|
c $ ,(mask_vk_ev(iv,ik),ik=1,nva1_view) |
143 |
enddo |
enddo |
144 |
|
|
145 |
cc call stripmask !compute mask(i,j,k), combining mask_vk_ev and mask_vk |
cc call stripmask !compute mask(i,j,k), combining mask_vk_ev and mask_vk |
637 |
|
|
638 |
subroutine stripmask(iv,ivk) |
subroutine stripmask(iv,ivk) |
639 |
|
|
640 |
|
* ----------------------------------------------- |
641 |
* this routine set va1 and single-strip masks, |
* this routine set va1 and single-strip masks, |
642 |
* on the basis of the VA1 mask saved in the DB |
* on the basis of the VA1 mask saved in the DB |
643 |
* |
* |
644 |
* mask(nviews,nva1_view,nstrips_va1) !strip mask |
* mask(nviews,nva1_view,nstrips_va1) !strip mask |
645 |
* mask_vk(nviews,nva1_view) !VA1 mask |
* mask_vk(nviews,nva1_view) !VA1 mask |
646 |
* |
* ----------------------------------------------- |
647 |
include 'commontracker.f' |
include 'commontracker.f' |
648 |
include 'level1.f' |
include 'level1.f' |
649 |
include 'common_reduction.f' |
include 'common_reduction.f' |
651 |
|
|
652 |
* init mask |
* init mask |
653 |
do is=1,nstrips_va1 |
do is=1,nstrips_va1 |
654 |
|
* -------------------------------------------------------- |
655 |
|
* if VA1-mask from DB is 0 or 1, three masks are combined: |
656 |
|
* - from DB (a-priori mask) |
657 |
|
* - run-based (chip declared bad on the basis of <SIG>) |
658 |
|
* - event-based (failure in CN computation) |
659 |
|
* -------------------------------------------------------- |
660 |
if( mask_vk(iv,ivk) .ne. -1)then |
if( mask_vk(iv,ivk) .ne. -1)then |
661 |
mask(iv,ivk,is) = 1 |
mask(iv,ivk,is) = 1 |
662 |
$ * mask_vk(iv,ivk) !from DB |
$ * mask_vk(iv,ivk) !from DB |
663 |
$ * mask_vk_ev(iv,ivk) !from <SIG> |
$ * mask_vk_ev(iv,ivk) !from <SIG> |
664 |
$ * mask_vk_run(iv,ivk) !from CN |
$ * mask_vk_run(iv,ivk) !from CN |
665 |
|
* ----------------------------------------------------------- |
666 |
|
* if VA1-mask from DB is -1 only event-based mask is applied |
667 |
|
* ----------------------------------------------------------- |
668 |
else |
else |
669 |
mask(iv,ivk,is) = -1 |
mask(iv,ivk,is) = -1 |
670 |
$ * mask_vk(iv,ivk) !from DB |
$ * mask_vk(iv,ivk) !from DB |
671 |
$ * mask_vk_ev(iv,ivk) !from CN |
$ * mask_vk_ev(iv,ivk) !from CN |
672 |
endif |
endif |
673 |
enddo |
enddo |
674 |
|
|